1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2010-2011 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * QorIQ RDB boards configuration file 8 */ 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #if defined(CONFIG_TARGET_P1020MBG) 13 #define CONFIG_BOARDNAME "P1020MBG-PC" 14 #define CONFIG_VSC7385_ENET 15 #define CONFIG_SLIC 16 #define __SW_BOOT_MASK 0x03 17 #define __SW_BOOT_NOR 0xe4 18 #define __SW_BOOT_SD 0x54 19 #define CONFIG_SYS_L2_SIZE (256 << 10) 20 #endif 21 22 #if defined(CONFIG_TARGET_P1020UTM) 23 #define CONFIG_BOARDNAME "P1020UTM-PC" 24 #define __SW_BOOT_MASK 0x03 25 #define __SW_BOOT_NOR 0xe0 26 #define __SW_BOOT_SD 0x50 27 #define CONFIG_SYS_L2_SIZE (256 << 10) 28 #endif 29 30 #if defined(CONFIG_TARGET_P1020RDB_PC) 31 #define CONFIG_BOARDNAME "P1020RDB-PC" 32 #define CONFIG_NAND_FSL_ELBC 33 #define CONFIG_VSC7385_ENET 34 #define CONFIG_SLIC 35 #define __SW_BOOT_MASK 0x03 36 #define __SW_BOOT_NOR 0x5c 37 #define __SW_BOOT_SPI 0x1c 38 #define __SW_BOOT_SD 0x9c 39 #define __SW_BOOT_NAND 0xec 40 #define __SW_BOOT_PCIE 0x6c 41 #define CONFIG_SYS_L2_SIZE (256 << 10) 42 #endif 43 44 /* 45 * P1020RDB-PD board has user selectable switches for evaluating different 46 * frequency and boot options for the P1020 device. The table that 47 * follow describe the available options. The front six binary number was in 48 * accordance with SW3[1:6]. 49 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 50 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 51 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 52 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 53 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 54 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 55 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 56 */ 57 #if defined(CONFIG_TARGET_P1020RDB_PD) 58 #define CONFIG_BOARDNAME "P1020RDB-PD" 59 #define CONFIG_NAND_FSL_ELBC 60 #define CONFIG_VSC7385_ENET 61 #define CONFIG_SLIC 62 #define __SW_BOOT_MASK 0x03 63 #define __SW_BOOT_NOR 0x64 64 #define __SW_BOOT_SPI 0x34 65 #define __SW_BOOT_SD 0x24 66 #define __SW_BOOT_NAND 0x44 67 #define __SW_BOOT_PCIE 0x74 68 #define CONFIG_SYS_L2_SIZE (256 << 10) 69 /* 70 * Dynamic MTD Partition support with mtdparts 71 */ 72 #define CONFIG_FLASH_CFI_MTD 73 #endif 74 75 #if defined(CONFIG_TARGET_P1021RDB) 76 #define CONFIG_BOARDNAME "P1021RDB-PC" 77 #define CONFIG_NAND_FSL_ELBC 78 #define CONFIG_QE 79 #define CONFIG_VSC7385_ENET 80 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 81 addresses in the LBC */ 82 #define __SW_BOOT_MASK 0x03 83 #define __SW_BOOT_NOR 0x5c 84 #define __SW_BOOT_SPI 0x1c 85 #define __SW_BOOT_SD 0x9c 86 #define __SW_BOOT_NAND 0xec 87 #define __SW_BOOT_PCIE 0x6c 88 #define CONFIG_SYS_L2_SIZE (256 << 10) 89 /* 90 * Dynamic MTD Partition support with mtdparts 91 */ 92 #define CONFIG_FLASH_CFI_MTD 93 #endif 94 95 #if defined(CONFIG_TARGET_P1024RDB) 96 #define CONFIG_BOARDNAME "P1024RDB" 97 #define CONFIG_NAND_FSL_ELBC 98 #define CONFIG_SLIC 99 #define __SW_BOOT_MASK 0xf3 100 #define __SW_BOOT_NOR 0x00 101 #define __SW_BOOT_SPI 0x08 102 #define __SW_BOOT_SD 0x04 103 #define __SW_BOOT_NAND 0x0c 104 #define CONFIG_SYS_L2_SIZE (256 << 10) 105 #endif 106 107 #if defined(CONFIG_TARGET_P1025RDB) 108 #define CONFIG_BOARDNAME "P1025RDB" 109 #define CONFIG_NAND_FSL_ELBC 110 #define CONFIG_QE 111 #define CONFIG_SLIC 112 113 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 114 addresses in the LBC */ 115 #define __SW_BOOT_MASK 0xf3 116 #define __SW_BOOT_NOR 0x00 117 #define __SW_BOOT_SPI 0x08 118 #define __SW_BOOT_SD 0x04 119 #define __SW_BOOT_NAND 0x0c 120 #define CONFIG_SYS_L2_SIZE (256 << 10) 121 #endif 122 123 #if defined(CONFIG_TARGET_P2020RDB) 124 #define CONFIG_BOARDNAME "P2020RDB-PC" 125 #define CONFIG_NAND_FSL_ELBC 126 #define CONFIG_VSC7385_ENET 127 #define __SW_BOOT_MASK 0x03 128 #define __SW_BOOT_NOR 0xc8 129 #define __SW_BOOT_SPI 0x28 130 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 131 #define __SW_BOOT_NAND 0xe8 132 #define __SW_BOOT_PCIE 0xa8 133 #define CONFIG_SYS_L2_SIZE (512 << 10) 134 /* 135 * Dynamic MTD Partition support with mtdparts 136 */ 137 #define CONFIG_FLASH_CFI_MTD 138 #endif 139 140 #ifdef CONFIG_SDCARD 141 #define CONFIG_SPL_FLUSH_IMAGE 142 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 143 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 144 #define CONFIG_SPL_PAD_TO 0x20000 145 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 146 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 147 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 148 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 149 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 150 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 151 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 152 #define CONFIG_SPL_MMC_BOOT 153 #ifdef CONFIG_SPL_BUILD 154 #define CONFIG_SPL_COMMON_INIT_DDR 155 #endif 156 #endif 157 158 #ifdef CONFIG_SPIFLASH 159 #define CONFIG_SPL_SPI_FLASH_MINIMAL 160 #define CONFIG_SPL_FLUSH_IMAGE 161 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 162 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 163 #define CONFIG_SPL_PAD_TO 0x20000 164 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 165 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 166 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 167 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 168 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 169 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 170 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 171 #define CONFIG_SPL_SPI_BOOT 172 #ifdef CONFIG_SPL_BUILD 173 #define CONFIG_SPL_COMMON_INIT_DDR 174 #endif 175 #endif 176 177 #ifdef CONFIG_NAND 178 #ifdef CONFIG_TPL_BUILD 179 #define CONFIG_SPL_NAND_BOOT 180 #define CONFIG_SPL_FLUSH_IMAGE 181 #define CONFIG_SPL_NAND_INIT 182 #define CONFIG_SPL_COMMON_INIT_DDR 183 #define CONFIG_SPL_MAX_SIZE (128 << 10) 184 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 185 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 186 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 187 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 188 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 189 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 190 #elif defined(CONFIG_SPL_BUILD) 191 #define CONFIG_SPL_INIT_MINIMAL 192 #define CONFIG_SPL_FLUSH_IMAGE 193 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 194 #define CONFIG_SPL_TEXT_BASE 0xff800000 195 #define CONFIG_SPL_MAX_SIZE 4096 196 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 197 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 198 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 199 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 200 #endif /* not CONFIG_TPL_BUILD */ 201 202 #define CONFIG_SPL_PAD_TO 0x20000 203 #define CONFIG_TPL_PAD_TO 0x20000 204 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 205 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 206 #endif 207 208 #ifndef CONFIG_RESET_VECTOR_ADDRESS 209 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 210 #endif 211 212 #ifndef CONFIG_SYS_MONITOR_BASE 213 #ifdef CONFIG_SPL_BUILD 214 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 215 #else 216 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 217 #endif 218 #endif 219 220 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 221 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 222 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 223 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 224 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 225 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 226 227 #define CONFIG_ENV_OVERWRITE 228 229 #define CONFIG_SYS_SATA_MAX_DEVICE 2 230 #define CONFIG_LBA48 231 232 #if defined(CONFIG_TARGET_P2020RDB) 233 #define CONFIG_SYS_CLK_FREQ 100000000 234 #else 235 #define CONFIG_SYS_CLK_FREQ 66666666 236 #endif 237 #define CONFIG_DDR_CLK_FREQ 66666666 238 239 #define CONFIG_HWCONFIG 240 /* 241 * These can be toggled for performance analysis, otherwise use default. 242 */ 243 #define CONFIG_L2_CACHE 244 #define CONFIG_BTB 245 246 #define CONFIG_ENABLE_36BIT_PHYS 247 248 #ifdef CONFIG_PHYS_64BIT 249 #define CONFIG_ADDR_MAP 1 250 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 251 #endif 252 253 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 254 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 255 256 #define CONFIG_SYS_CCSRBAR 0xffe00000 257 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 258 259 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 260 SPL code*/ 261 #ifdef CONFIG_SPL_BUILD 262 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 263 #endif 264 265 /* DDR Setup */ 266 #define CONFIG_SYS_DDR_RAW_TIMING 267 #define CONFIG_DDR_SPD 268 #define CONFIG_SYS_SPD_BUS_NUM 1 269 #define SPD_EEPROM_ADDRESS 0x52 270 #undef CONFIG_FSL_DDR_INTERACTIVE 271 272 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 273 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 274 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 275 #else 276 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 277 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 278 #endif 279 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 280 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 281 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 282 283 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 284 285 /* Default settings for DDR3 */ 286 #ifndef CONFIG_TARGET_P2020RDB 287 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 288 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 289 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 290 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 291 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 292 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 293 294 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 295 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 296 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 297 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 298 299 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 300 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 301 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 302 #define CONFIG_SYS_DDR_RCW_1 0x00000000 303 #define CONFIG_SYS_DDR_RCW_2 0x00000000 304 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 305 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 306 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 307 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 308 309 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 310 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 311 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 312 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 313 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 314 #define CONFIG_SYS_DDR_MODE_1 0x40461520 315 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 316 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 317 #endif 318 319 #undef CONFIG_CLOCKS_IN_MHZ 320 321 /* 322 * Memory map 323 * 324 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 325 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 326 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 327 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 328 * (early boot only) 329 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 330 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 331 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 332 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 333 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 334 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 335 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 336 */ 337 338 /* 339 * Local Bus Definitions 340 */ 341 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 342 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 343 #define CONFIG_SYS_FLASH_BASE 0xec000000 344 #elif defined(CONFIG_TARGET_P1020UTM) 345 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 346 #define CONFIG_SYS_FLASH_BASE 0xee000000 347 #else 348 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 349 #define CONFIG_SYS_FLASH_BASE 0xef000000 350 #endif 351 352 #ifdef CONFIG_PHYS_64BIT 353 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 354 #else 355 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 356 #endif 357 358 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 359 | BR_PS_16 | BR_V) 360 361 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 362 363 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 364 #define CONFIG_SYS_FLASH_QUIET_TEST 365 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 366 367 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 368 369 #undef CONFIG_SYS_FLASH_CHECKSUM 370 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 371 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 372 373 #define CONFIG_FLASH_CFI_DRIVER 374 #define CONFIG_SYS_FLASH_CFI 375 #define CONFIG_SYS_FLASH_EMPTY_INFO 376 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 377 378 /* Nand Flash */ 379 #ifdef CONFIG_NAND_FSL_ELBC 380 #define CONFIG_SYS_NAND_BASE 0xff800000 381 #ifdef CONFIG_PHYS_64BIT 382 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 383 #else 384 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 385 #endif 386 387 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 388 #define CONFIG_SYS_MAX_NAND_DEVICE 1 389 #if defined(CONFIG_TARGET_P1020RDB_PD) 390 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 391 #else 392 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 393 #endif 394 395 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 396 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 397 | BR_PS_8 /* Port Size = 8 bit */ \ 398 | BR_MS_FCM /* MSEL = FCM */ \ 399 | BR_V) /* valid */ 400 #if defined(CONFIG_TARGET_P1020RDB_PD) 401 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 402 | OR_FCM_PGS /* Large Page*/ \ 403 | OR_FCM_CSCT \ 404 | OR_FCM_CST \ 405 | OR_FCM_CHT \ 406 | OR_FCM_SCY_1 \ 407 | OR_FCM_TRLX \ 408 | OR_FCM_EHTR) 409 #else 410 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 411 | OR_FCM_CSCT \ 412 | OR_FCM_CST \ 413 | OR_FCM_CHT \ 414 | OR_FCM_SCY_1 \ 415 | OR_FCM_TRLX \ 416 | OR_FCM_EHTR) 417 #endif 418 #endif /* CONFIG_NAND_FSL_ELBC */ 419 420 #define CONFIG_SYS_INIT_RAM_LOCK 421 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 422 #ifdef CONFIG_PHYS_64BIT 423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 424 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 425 /* The assembler doesn't like typecast */ 426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 427 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 428 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 429 #else 430 /* Initial L1 address */ 431 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 432 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 433 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 434 #endif 435 /* Size of used area in RAM */ 436 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 437 438 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 439 GENERATED_GBL_DATA_SIZE) 440 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 441 442 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 443 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 444 445 #define CONFIG_SYS_CPLD_BASE 0xffa00000 446 #ifdef CONFIG_PHYS_64BIT 447 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 448 #else 449 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 450 #endif 451 /* CPLD config size: 1Mb */ 452 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 453 BR_PS_8 | BR_V) 454 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 455 456 #define CONFIG_SYS_PMC_BASE 0xff980000 457 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 458 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 459 BR_PS_8 | BR_V) 460 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 461 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 462 OR_GPCM_EAD) 463 464 #ifdef CONFIG_NAND 465 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 466 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 467 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 468 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 469 #else 470 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 471 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 472 #ifdef CONFIG_NAND_FSL_ELBC 473 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 474 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 475 #endif 476 #endif 477 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 478 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 479 480 /* Vsc7385 switch */ 481 #ifdef CONFIG_VSC7385_ENET 482 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 483 484 #ifdef CONFIG_PHYS_64BIT 485 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 486 #else 487 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 488 #endif 489 490 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 491 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 492 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 493 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 494 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 495 496 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 497 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 498 499 /* The size of the VSC7385 firmware image */ 500 #define CONFIG_VSC7385_IMAGE_SIZE 8192 501 #endif 502 503 /* 504 * Config the L2 Cache as L2 SRAM 505 */ 506 #if defined(CONFIG_SPL_BUILD) 507 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 508 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 509 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 510 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 511 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 512 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 513 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 514 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 515 #if defined(CONFIG_TARGET_P2020RDB) 516 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 517 #else 518 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 519 #endif 520 #elif defined(CONFIG_NAND) 521 #ifdef CONFIG_TPL_BUILD 522 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 523 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 524 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 525 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 526 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 527 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 528 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 529 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 530 #else 531 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 532 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 533 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 534 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 535 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 536 #endif /* CONFIG_TPL_BUILD */ 537 #endif 538 #endif 539 540 /* Serial Port - controlled on board with jumper J8 541 * open - index 2 542 * shorted - index 1 543 */ 544 #undef CONFIG_SERIAL_SOFTWARE_FIFO 545 #define CONFIG_SYS_NS16550_SERIAL 546 #define CONFIG_SYS_NS16550_REG_SIZE 1 547 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 548 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 549 #define CONFIG_NS16550_MIN_FUNCTIONS 550 #endif 551 552 #define CONFIG_SYS_BAUDRATE_TABLE \ 553 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 554 555 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 556 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 557 558 /* I2C */ 559 #define CONFIG_SYS_I2C 560 #define CONFIG_SYS_I2C_FSL 561 #define CONFIG_SYS_FSL_I2C_SPEED 400000 562 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 563 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 564 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 565 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 566 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 567 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 568 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 569 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 570 571 /* 572 * I2C2 EEPROM 573 */ 574 #undef CONFIG_ID_EEPROM 575 576 #define CONFIG_RTC_PT7C4338 577 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 578 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 579 580 /* enable read and write access to EEPROM */ 581 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 582 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 583 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 584 585 /* 586 * eSPI - Enhanced SPI 587 */ 588 #define CONFIG_HARD_SPI 589 590 #if defined(CONFIG_SPI_FLASH) 591 #define CONFIG_SF_DEFAULT_SPEED 10000000 592 #define CONFIG_SF_DEFAULT_MODE 0 593 #endif 594 595 #if defined(CONFIG_PCI) 596 /* 597 * General PCI 598 * Memory space is mapped 1-1, but I/O space must start from 0. 599 */ 600 601 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 602 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 603 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 604 #ifdef CONFIG_PHYS_64BIT 605 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 606 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 607 #else 608 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 609 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 610 #endif 611 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 612 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 613 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 614 #ifdef CONFIG_PHYS_64BIT 615 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 616 #else 617 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 618 #endif 619 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 620 621 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 622 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 623 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 624 #ifdef CONFIG_PHYS_64BIT 625 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 626 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 627 #else 628 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 629 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 630 #endif 631 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 632 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 633 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 634 #ifdef CONFIG_PHYS_64BIT 635 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 636 #else 637 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 638 #endif 639 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 640 641 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 642 #endif /* CONFIG_PCI */ 643 644 #if defined(CONFIG_TSEC_ENET) 645 #define CONFIG_MII /* MII PHY management */ 646 #define CONFIG_TSEC1 647 #define CONFIG_TSEC1_NAME "eTSEC1" 648 #define CONFIG_TSEC2 649 #define CONFIG_TSEC2_NAME "eTSEC2" 650 #define CONFIG_TSEC3 651 #define CONFIG_TSEC3_NAME "eTSEC3" 652 653 #define TSEC1_PHY_ADDR 2 654 #define TSEC2_PHY_ADDR 0 655 #define TSEC3_PHY_ADDR 1 656 657 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 658 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 659 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 660 661 #define TSEC1_PHYIDX 0 662 #define TSEC2_PHYIDX 0 663 #define TSEC3_PHYIDX 0 664 665 #define CONFIG_ETHPRIME "eTSEC1" 666 667 #define CONFIG_HAS_ETH0 668 #define CONFIG_HAS_ETH1 669 #define CONFIG_HAS_ETH2 670 #endif /* CONFIG_TSEC_ENET */ 671 672 #ifdef CONFIG_QE 673 /* QE microcode/firmware address */ 674 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 675 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 676 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 677 #endif /* CONFIG_QE */ 678 679 #ifdef CONFIG_TARGET_P1025RDB 680 /* 681 * QE UEC ethernet configuration 682 */ 683 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 684 685 #undef CONFIG_UEC_ETH 686 #define CONFIG_PHY_MODE_NEED_CHANGE 687 688 #define CONFIG_UEC_ETH1 /* ETH1 */ 689 #define CONFIG_HAS_ETH0 690 691 #ifdef CONFIG_UEC_ETH1 692 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 693 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 694 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 695 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 696 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 697 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 698 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 699 #endif /* CONFIG_UEC_ETH1 */ 700 701 #define CONFIG_UEC_ETH5 /* ETH5 */ 702 #define CONFIG_HAS_ETH1 703 704 #ifdef CONFIG_UEC_ETH5 705 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 706 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 707 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 708 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 709 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 710 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 711 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 712 #endif /* CONFIG_UEC_ETH5 */ 713 #endif /* CONFIG_TARGET_P1025RDB */ 714 715 /* 716 * Environment 717 */ 718 #ifdef CONFIG_SPIFLASH 719 #define CONFIG_ENV_SPI_BUS 0 720 #define CONFIG_ENV_SPI_CS 0 721 #define CONFIG_ENV_SPI_MAX_HZ 10000000 722 #define CONFIG_ENV_SPI_MODE 0 723 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 724 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 725 #define CONFIG_ENV_SECT_SIZE 0x10000 726 #elif defined(CONFIG_SDCARD) 727 #define CONFIG_FSL_FIXED_MMC_LOCATION 728 #define CONFIG_ENV_SIZE 0x2000 729 #define CONFIG_SYS_MMC_ENV_DEV 0 730 #elif defined(CONFIG_NAND) 731 #ifdef CONFIG_TPL_BUILD 732 #define CONFIG_ENV_SIZE 0x2000 733 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 734 #else 735 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 736 #endif 737 #define CONFIG_ENV_OFFSET (1024 * 1024) 738 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 739 #elif defined(CONFIG_SYS_RAMBOOT) 740 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 741 #define CONFIG_ENV_SIZE 0x2000 742 #else 743 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 744 #define CONFIG_ENV_SIZE 0x2000 745 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 746 #endif 747 748 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 749 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 750 751 /* 752 * USB 753 */ 754 #define CONFIG_HAS_FSL_DR_USB 755 756 #if defined(CONFIG_HAS_FSL_DR_USB) 757 #ifdef CONFIG_USB_EHCI_HCD 758 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 759 #define CONFIG_USB_EHCI_FSL 760 #endif 761 #endif 762 763 #if defined(CONFIG_TARGET_P1020RDB_PD) 764 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 765 #endif 766 767 #ifdef CONFIG_MMC 768 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 769 #endif 770 771 #undef CONFIG_WATCHDOG /* watchdog disabled */ 772 773 /* 774 * Miscellaneous configurable options 775 */ 776 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 777 778 /* 779 * For booting Linux, the board info and command line data 780 * have to be in the first 64 MB of memory, since this is 781 * the maximum mapped by the Linux kernel during initialization. 782 */ 783 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 784 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 785 786 #if defined(CONFIG_CMD_KGDB) 787 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 788 #endif 789 790 /* 791 * Environment Configuration 792 */ 793 #define CONFIG_HOSTNAME "unknown" 794 #define CONFIG_ROOTPATH "/opt/nfsroot" 795 #define CONFIG_BOOTFILE "uImage" 796 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 797 798 /* default location for tftp and bootm */ 799 #define CONFIG_LOADADDR 1000000 800 801 #ifdef __SW_BOOT_NOR 802 #define __NOR_RST_CMD \ 803 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 804 i2c mw 18 3 __SW_BOOT_MASK 1; reset 805 #endif 806 #ifdef __SW_BOOT_SPI 807 #define __SPI_RST_CMD \ 808 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 809 i2c mw 18 3 __SW_BOOT_MASK 1; reset 810 #endif 811 #ifdef __SW_BOOT_SD 812 #define __SD_RST_CMD \ 813 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 814 i2c mw 18 3 __SW_BOOT_MASK 1; reset 815 #endif 816 #ifdef __SW_BOOT_NAND 817 #define __NAND_RST_CMD \ 818 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 819 i2c mw 18 3 __SW_BOOT_MASK 1; reset 820 #endif 821 #ifdef __SW_BOOT_PCIE 822 #define __PCIE_RST_CMD \ 823 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 824 i2c mw 18 3 __SW_BOOT_MASK 1; reset 825 #endif 826 827 #define CONFIG_EXTRA_ENV_SETTINGS \ 828 "netdev=eth0\0" \ 829 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 830 "loadaddr=1000000\0" \ 831 "bootfile=uImage\0" \ 832 "tftpflash=tftpboot $loadaddr $uboot; " \ 833 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 834 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 835 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 836 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 837 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 838 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 839 "consoledev=ttyS0\0" \ 840 "ramdiskaddr=2000000\0" \ 841 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 842 "fdtaddr=1e00000\0" \ 843 "bdev=sda1\0" \ 844 "jffs2nor=mtdblock3\0" \ 845 "norbootaddr=ef080000\0" \ 846 "norfdtaddr=ef040000\0" \ 847 "jffs2nand=mtdblock9\0" \ 848 "nandbootaddr=100000\0" \ 849 "nandfdtaddr=80000\0" \ 850 "ramdisk_size=120000\0" \ 851 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 852 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 853 __stringify(__NOR_RST_CMD)"\0" \ 854 __stringify(__SPI_RST_CMD)"\0" \ 855 __stringify(__SD_RST_CMD)"\0" \ 856 __stringify(__NAND_RST_CMD)"\0" \ 857 __stringify(__PCIE_RST_CMD)"\0" 858 859 #define CONFIG_NFSBOOTCOMMAND \ 860 "setenv bootargs root=/dev/nfs rw " \ 861 "nfsroot=$serverip:$rootpath " \ 862 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 863 "console=$consoledev,$baudrate $othbootargs;" \ 864 "tftp $loadaddr $bootfile;" \ 865 "tftp $fdtaddr $fdtfile;" \ 866 "bootm $loadaddr - $fdtaddr" 867 868 #define CONFIG_HDBOOT \ 869 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 870 "console=$consoledev,$baudrate $othbootargs;" \ 871 "usb start;" \ 872 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 873 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 874 "bootm $loadaddr - $fdtaddr" 875 876 #define CONFIG_USB_FAT_BOOT \ 877 "setenv bootargs root=/dev/ram rw " \ 878 "console=$consoledev,$baudrate $othbootargs " \ 879 "ramdisk_size=$ramdisk_size;" \ 880 "usb start;" \ 881 "fatload usb 0:2 $loadaddr $bootfile;" \ 882 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 883 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 884 "bootm $loadaddr $ramdiskaddr $fdtaddr" 885 886 #define CONFIG_USB_EXT2_BOOT \ 887 "setenv bootargs root=/dev/ram rw " \ 888 "console=$consoledev,$baudrate $othbootargs " \ 889 "ramdisk_size=$ramdisk_size;" \ 890 "usb start;" \ 891 "ext2load usb 0:4 $loadaddr $bootfile;" \ 892 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 893 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 894 "bootm $loadaddr $ramdiskaddr $fdtaddr" 895 896 #define CONFIG_NORBOOT \ 897 "setenv bootargs root=/dev/$jffs2nor rw " \ 898 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 899 "bootm $norbootaddr - $norfdtaddr" 900 901 #define CONFIG_RAMBOOTCOMMAND \ 902 "setenv bootargs root=/dev/ram rw " \ 903 "console=$consoledev,$baudrate $othbootargs " \ 904 "ramdisk_size=$ramdisk_size;" \ 905 "tftp $ramdiskaddr $ramdiskfile;" \ 906 "tftp $loadaddr $bootfile;" \ 907 "tftp $fdtaddr $fdtfile;" \ 908 "bootm $loadaddr $ramdiskaddr $fdtaddr" 909 910 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 911 912 #endif /* __CONFIG_H */ 913