1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TARGET_P1020MBG) 14 #define CONFIG_BOARDNAME "P1020MBG-PC" 15 #define CONFIG_VSC7385_ENET 16 #define CONFIG_SLIC 17 #define __SW_BOOT_MASK 0x03 18 #define __SW_BOOT_NOR 0xe4 19 #define __SW_BOOT_SD 0x54 20 #define CONFIG_SYS_L2_SIZE (256 << 10) 21 #endif 22 23 #if defined(CONFIG_TARGET_P1020UTM) 24 #define CONFIG_BOARDNAME "P1020UTM-PC" 25 #define __SW_BOOT_MASK 0x03 26 #define __SW_BOOT_NOR 0xe0 27 #define __SW_BOOT_SD 0x50 28 #define CONFIG_SYS_L2_SIZE (256 << 10) 29 #endif 30 31 #if defined(CONFIG_TARGET_P1020RDB_PC) 32 #define CONFIG_BOARDNAME "P1020RDB-PC" 33 #define CONFIG_NAND_FSL_ELBC 34 #define CONFIG_VSC7385_ENET 35 #define CONFIG_SLIC 36 #define __SW_BOOT_MASK 0x03 37 #define __SW_BOOT_NOR 0x5c 38 #define __SW_BOOT_SPI 0x1c 39 #define __SW_BOOT_SD 0x9c 40 #define __SW_BOOT_NAND 0xec 41 #define __SW_BOOT_PCIE 0x6c 42 #define CONFIG_SYS_L2_SIZE (256 << 10) 43 #endif 44 45 /* 46 * P1020RDB-PD board has user selectable switches for evaluating different 47 * frequency and boot options for the P1020 device. The table that 48 * follow describe the available options. The front six binary number was in 49 * accordance with SW3[1:6]. 50 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 51 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 52 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 53 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 54 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 55 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 56 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 57 */ 58 #if defined(CONFIG_TARGET_P1020RDB_PD) 59 #define CONFIG_BOARDNAME "P1020RDB-PD" 60 #define CONFIG_NAND_FSL_ELBC 61 #define CONFIG_VSC7385_ENET 62 #define CONFIG_SLIC 63 #define __SW_BOOT_MASK 0x03 64 #define __SW_BOOT_NOR 0x64 65 #define __SW_BOOT_SPI 0x34 66 #define __SW_BOOT_SD 0x24 67 #define __SW_BOOT_NAND 0x44 68 #define __SW_BOOT_PCIE 0x74 69 #define CONFIG_SYS_L2_SIZE (256 << 10) 70 /* 71 * Dynamic MTD Partition support with mtdparts 72 */ 73 #define CONFIG_MTD_DEVICE 74 #define CONFIG_MTD_PARTITIONS 75 #define CONFIG_FLASH_CFI_MTD 76 #endif 77 78 #if defined(CONFIG_TARGET_P1021RDB) 79 #define CONFIG_BOARDNAME "P1021RDB-PC" 80 #define CONFIG_NAND_FSL_ELBC 81 #define CONFIG_QE 82 #define CONFIG_VSC7385_ENET 83 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 84 addresses in the LBC */ 85 #define __SW_BOOT_MASK 0x03 86 #define __SW_BOOT_NOR 0x5c 87 #define __SW_BOOT_SPI 0x1c 88 #define __SW_BOOT_SD 0x9c 89 #define __SW_BOOT_NAND 0xec 90 #define __SW_BOOT_PCIE 0x6c 91 #define CONFIG_SYS_L2_SIZE (256 << 10) 92 /* 93 * Dynamic MTD Partition support with mtdparts 94 */ 95 #define CONFIG_MTD_DEVICE 96 #define CONFIG_MTD_PARTITIONS 97 #define CONFIG_FLASH_CFI_MTD 98 #endif 99 100 #if defined(CONFIG_TARGET_P1024RDB) 101 #define CONFIG_BOARDNAME "P1024RDB" 102 #define CONFIG_NAND_FSL_ELBC 103 #define CONFIG_SLIC 104 #define __SW_BOOT_MASK 0xf3 105 #define __SW_BOOT_NOR 0x00 106 #define __SW_BOOT_SPI 0x08 107 #define __SW_BOOT_SD 0x04 108 #define __SW_BOOT_NAND 0x0c 109 #define CONFIG_SYS_L2_SIZE (256 << 10) 110 #endif 111 112 #if defined(CONFIG_TARGET_P1025RDB) 113 #define CONFIG_BOARDNAME "P1025RDB" 114 #define CONFIG_NAND_FSL_ELBC 115 #define CONFIG_QE 116 #define CONFIG_SLIC 117 118 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 119 addresses in the LBC */ 120 #define __SW_BOOT_MASK 0xf3 121 #define __SW_BOOT_NOR 0x00 122 #define __SW_BOOT_SPI 0x08 123 #define __SW_BOOT_SD 0x04 124 #define __SW_BOOT_NAND 0x0c 125 #define CONFIG_SYS_L2_SIZE (256 << 10) 126 #endif 127 128 #if defined(CONFIG_TARGET_P2020RDB) 129 #define CONFIG_BOARDNAME "P2020RDB-PC" 130 #define CONFIG_NAND_FSL_ELBC 131 #define CONFIG_VSC7385_ENET 132 #define __SW_BOOT_MASK 0x03 133 #define __SW_BOOT_NOR 0xc8 134 #define __SW_BOOT_SPI 0x28 135 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 136 #define __SW_BOOT_NAND 0xe8 137 #define __SW_BOOT_PCIE 0xa8 138 #define CONFIG_SYS_L2_SIZE (512 << 10) 139 /* 140 * Dynamic MTD Partition support with mtdparts 141 */ 142 #define CONFIG_MTD_DEVICE 143 #define CONFIG_MTD_PARTITIONS 144 #define CONFIG_FLASH_CFI_MTD 145 #endif 146 147 #ifdef CONFIG_SDCARD 148 #define CONFIG_SPL_MMC_MINIMAL 149 #define CONFIG_SPL_FLUSH_IMAGE 150 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 151 #define CONFIG_SYS_TEXT_BASE 0x11001000 152 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 153 #define CONFIG_SPL_PAD_TO 0x20000 154 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 155 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 156 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 157 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 158 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 159 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 160 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 161 #define CONFIG_SPL_MMC_BOOT 162 #ifdef CONFIG_SPL_BUILD 163 #define CONFIG_SPL_COMMON_INIT_DDR 164 #endif 165 #endif 166 167 #ifdef CONFIG_SPIFLASH 168 #define CONFIG_SPL_SPI_FLASH_MINIMAL 169 #define CONFIG_SPL_FLUSH_IMAGE 170 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 171 #define CONFIG_SYS_TEXT_BASE 0x11001000 172 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 173 #define CONFIG_SPL_PAD_TO 0x20000 174 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 175 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 176 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 177 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 178 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 179 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 180 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 181 #define CONFIG_SPL_SPI_BOOT 182 #ifdef CONFIG_SPL_BUILD 183 #define CONFIG_SPL_COMMON_INIT_DDR 184 #endif 185 #endif 186 187 #ifdef CONFIG_NAND 188 #ifdef CONFIG_TPL_BUILD 189 #define CONFIG_SPL_NAND_BOOT 190 #define CONFIG_SPL_FLUSH_IMAGE 191 #define CONFIG_SPL_NAND_INIT 192 #define CONFIG_SPL_COMMON_INIT_DDR 193 #define CONFIG_SPL_MAX_SIZE (128 << 10) 194 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 195 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 196 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 197 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 198 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 199 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 200 #elif defined(CONFIG_SPL_BUILD) 201 #define CONFIG_SPL_INIT_MINIMAL 202 #define CONFIG_SPL_FLUSH_IMAGE 203 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 204 #define CONFIG_SPL_TEXT_BASE 0xff800000 205 #define CONFIG_SPL_MAX_SIZE 4096 206 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 207 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 208 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 209 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 210 #endif /* not CONFIG_TPL_BUILD */ 211 212 #define CONFIG_SPL_PAD_TO 0x20000 213 #define CONFIG_TPL_PAD_TO 0x20000 214 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 215 #define CONFIG_SYS_TEXT_BASE 0x11001000 216 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 217 #endif 218 219 #ifndef CONFIG_SYS_TEXT_BASE 220 #define CONFIG_SYS_TEXT_BASE 0xeff40000 221 #endif 222 223 #ifndef CONFIG_RESET_VECTOR_ADDRESS 224 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 225 #endif 226 227 #ifndef CONFIG_SYS_MONITOR_BASE 228 #ifdef CONFIG_SPL_BUILD 229 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 230 #else 231 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 232 #endif 233 #endif 234 235 #define CONFIG_MP 236 237 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 238 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 239 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 240 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 241 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 242 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 243 244 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 245 #define CONFIG_ENV_OVERWRITE 246 247 #define CONFIG_SYS_SATA_MAX_DEVICE 2 248 #define CONFIG_LBA48 249 250 #if defined(CONFIG_TARGET_P2020RDB) 251 #define CONFIG_SYS_CLK_FREQ 100000000 252 #else 253 #define CONFIG_SYS_CLK_FREQ 66666666 254 #endif 255 #define CONFIG_DDR_CLK_FREQ 66666666 256 257 #define CONFIG_HWCONFIG 258 /* 259 * These can be toggled for performance analysis, otherwise use default. 260 */ 261 #define CONFIG_L2_CACHE 262 #define CONFIG_BTB 263 264 #define CONFIG_ENABLE_36BIT_PHYS 265 266 #ifdef CONFIG_PHYS_64BIT 267 #define CONFIG_ADDR_MAP 1 268 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 269 #endif 270 271 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 272 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 273 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 274 275 #define CONFIG_SYS_CCSRBAR 0xffe00000 276 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 277 278 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 279 SPL code*/ 280 #ifdef CONFIG_SPL_BUILD 281 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 282 #endif 283 284 /* DDR Setup */ 285 #define CONFIG_SYS_DDR_RAW_TIMING 286 #define CONFIG_DDR_SPD 287 #define CONFIG_SYS_SPD_BUS_NUM 1 288 #define SPD_EEPROM_ADDRESS 0x52 289 #undef CONFIG_FSL_DDR_INTERACTIVE 290 291 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 292 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 293 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 294 #else 295 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 296 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 297 #endif 298 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 299 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 300 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 301 302 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 303 304 /* Default settings for DDR3 */ 305 #ifndef CONFIG_TARGET_P2020RDB 306 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 307 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 308 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 309 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 310 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 311 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 312 313 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 314 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 315 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 316 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 317 318 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 319 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 320 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 321 #define CONFIG_SYS_DDR_RCW_1 0x00000000 322 #define CONFIG_SYS_DDR_RCW_2 0x00000000 323 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 324 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 325 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 326 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 327 328 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 329 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 330 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 331 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 332 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 333 #define CONFIG_SYS_DDR_MODE_1 0x40461520 334 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 335 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 336 #endif 337 338 #undef CONFIG_CLOCKS_IN_MHZ 339 340 /* 341 * Memory map 342 * 343 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 344 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 345 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 346 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 347 * (early boot only) 348 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 349 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 350 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 351 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 352 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 353 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 354 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 355 */ 356 357 /* 358 * Local Bus Definitions 359 */ 360 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 361 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 362 #define CONFIG_SYS_FLASH_BASE 0xec000000 363 #elif defined(CONFIG_TARGET_P1020UTM) 364 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 365 #define CONFIG_SYS_FLASH_BASE 0xee000000 366 #else 367 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 368 #define CONFIG_SYS_FLASH_BASE 0xef000000 369 #endif 370 371 #ifdef CONFIG_PHYS_64BIT 372 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 373 #else 374 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 375 #endif 376 377 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 378 | BR_PS_16 | BR_V) 379 380 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 381 382 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 383 #define CONFIG_SYS_FLASH_QUIET_TEST 384 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 385 386 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 387 388 #undef CONFIG_SYS_FLASH_CHECKSUM 389 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 390 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 391 392 #define CONFIG_FLASH_CFI_DRIVER 393 #define CONFIG_SYS_FLASH_CFI 394 #define CONFIG_SYS_FLASH_EMPTY_INFO 395 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 396 397 /* Nand Flash */ 398 #ifdef CONFIG_NAND_FSL_ELBC 399 #define CONFIG_SYS_NAND_BASE 0xff800000 400 #ifdef CONFIG_PHYS_64BIT 401 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 402 #else 403 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 404 #endif 405 406 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 407 #define CONFIG_SYS_MAX_NAND_DEVICE 1 408 #if defined(CONFIG_TARGET_P1020RDB_PD) 409 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 410 #else 411 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 412 #endif 413 414 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 415 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 416 | BR_PS_8 /* Port Size = 8 bit */ \ 417 | BR_MS_FCM /* MSEL = FCM */ \ 418 | BR_V) /* valid */ 419 #if defined(CONFIG_TARGET_P1020RDB_PD) 420 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 421 | OR_FCM_PGS /* Large Page*/ \ 422 | OR_FCM_CSCT \ 423 | OR_FCM_CST \ 424 | OR_FCM_CHT \ 425 | OR_FCM_SCY_1 \ 426 | OR_FCM_TRLX \ 427 | OR_FCM_EHTR) 428 #else 429 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 430 | OR_FCM_CSCT \ 431 | OR_FCM_CST \ 432 | OR_FCM_CHT \ 433 | OR_FCM_SCY_1 \ 434 | OR_FCM_TRLX \ 435 | OR_FCM_EHTR) 436 #endif 437 #endif /* CONFIG_NAND_FSL_ELBC */ 438 439 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 440 441 #define CONFIG_SYS_INIT_RAM_LOCK 442 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 443 #ifdef CONFIG_PHYS_64BIT 444 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 445 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 446 /* The assembler doesn't like typecast */ 447 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 448 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 449 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 450 #else 451 /* Initial L1 address */ 452 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 453 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 455 #endif 456 /* Size of used area in RAM */ 457 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 458 459 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 460 GENERATED_GBL_DATA_SIZE) 461 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 462 463 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 464 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 465 466 #define CONFIG_SYS_CPLD_BASE 0xffa00000 467 #ifdef CONFIG_PHYS_64BIT 468 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 469 #else 470 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 471 #endif 472 /* CPLD config size: 1Mb */ 473 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 474 BR_PS_8 | BR_V) 475 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 476 477 #define CONFIG_SYS_PMC_BASE 0xff980000 478 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 479 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 480 BR_PS_8 | BR_V) 481 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 482 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 483 OR_GPCM_EAD) 484 485 #ifdef CONFIG_NAND 486 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 487 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 488 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 489 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 490 #else 491 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 492 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 493 #ifdef CONFIG_NAND_FSL_ELBC 494 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 495 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 496 #endif 497 #endif 498 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 499 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 500 501 /* Vsc7385 switch */ 502 #ifdef CONFIG_VSC7385_ENET 503 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 504 505 #ifdef CONFIG_PHYS_64BIT 506 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 507 #else 508 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 509 #endif 510 511 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 512 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 513 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 514 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 515 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 516 517 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 518 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 519 520 /* The size of the VSC7385 firmware image */ 521 #define CONFIG_VSC7385_IMAGE_SIZE 8192 522 #endif 523 524 /* 525 * Config the L2 Cache as L2 SRAM 526 */ 527 #if defined(CONFIG_SPL_BUILD) 528 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 529 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 530 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 531 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 532 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 533 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 534 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 535 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 536 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 537 #if defined(CONFIG_TARGET_P2020RDB) 538 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 539 #else 540 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 541 #endif 542 #elif defined(CONFIG_NAND) 543 #ifdef CONFIG_TPL_BUILD 544 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 545 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 546 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 547 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 548 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 549 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 550 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 551 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 552 #else 553 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 554 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 555 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 556 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 557 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 558 #endif /* CONFIG_TPL_BUILD */ 559 #endif 560 #endif 561 562 /* Serial Port - controlled on board with jumper J8 563 * open - index 2 564 * shorted - index 1 565 */ 566 #define CONFIG_CONS_INDEX 1 567 #undef CONFIG_SERIAL_SOFTWARE_FIFO 568 #define CONFIG_SYS_NS16550_SERIAL 569 #define CONFIG_SYS_NS16550_REG_SIZE 1 570 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 571 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 572 #define CONFIG_NS16550_MIN_FUNCTIONS 573 #endif 574 575 #define CONFIG_SYS_BAUDRATE_TABLE \ 576 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 577 578 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 579 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 580 581 /* I2C */ 582 #define CONFIG_SYS_I2C 583 #define CONFIG_SYS_I2C_FSL 584 #define CONFIG_SYS_FSL_I2C_SPEED 400000 585 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 586 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 587 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 588 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 589 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 590 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 591 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 592 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 593 594 /* 595 * I2C2 EEPROM 596 */ 597 #undef CONFIG_ID_EEPROM 598 599 #define CONFIG_RTC_PT7C4338 600 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 601 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 602 603 /* enable read and write access to EEPROM */ 604 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 605 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 606 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 607 608 /* 609 * eSPI - Enhanced SPI 610 */ 611 #define CONFIG_HARD_SPI 612 613 #if defined(CONFIG_SPI_FLASH) 614 #define CONFIG_SF_DEFAULT_SPEED 10000000 615 #define CONFIG_SF_DEFAULT_MODE 0 616 #endif 617 618 #if defined(CONFIG_PCI) 619 /* 620 * General PCI 621 * Memory space is mapped 1-1, but I/O space must start from 0. 622 */ 623 624 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 625 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 626 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 627 #ifdef CONFIG_PHYS_64BIT 628 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 629 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 630 #else 631 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 632 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 633 #endif 634 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 635 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 636 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 637 #ifdef CONFIG_PHYS_64BIT 638 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 639 #else 640 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 641 #endif 642 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 643 644 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 645 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 646 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 647 #ifdef CONFIG_PHYS_64BIT 648 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 649 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 650 #else 651 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 652 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 653 #endif 654 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 655 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 656 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 657 #ifdef CONFIG_PHYS_64BIT 658 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 659 #else 660 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 661 #endif 662 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 663 664 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 665 #endif /* CONFIG_PCI */ 666 667 #if defined(CONFIG_TSEC_ENET) 668 #define CONFIG_MII /* MII PHY management */ 669 #define CONFIG_TSEC1 670 #define CONFIG_TSEC1_NAME "eTSEC1" 671 #define CONFIG_TSEC2 672 #define CONFIG_TSEC2_NAME "eTSEC2" 673 #define CONFIG_TSEC3 674 #define CONFIG_TSEC3_NAME "eTSEC3" 675 676 #define TSEC1_PHY_ADDR 2 677 #define TSEC2_PHY_ADDR 0 678 #define TSEC3_PHY_ADDR 1 679 680 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 681 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 682 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 683 684 #define TSEC1_PHYIDX 0 685 #define TSEC2_PHYIDX 0 686 #define TSEC3_PHYIDX 0 687 688 #define CONFIG_ETHPRIME "eTSEC1" 689 690 #define CONFIG_HAS_ETH0 691 #define CONFIG_HAS_ETH1 692 #define CONFIG_HAS_ETH2 693 #endif /* CONFIG_TSEC_ENET */ 694 695 #ifdef CONFIG_QE 696 /* QE microcode/firmware address */ 697 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 698 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 699 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 700 #endif /* CONFIG_QE */ 701 702 #ifdef CONFIG_TARGET_P1025RDB 703 /* 704 * QE UEC ethernet configuration 705 */ 706 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 707 708 #undef CONFIG_UEC_ETH 709 #define CONFIG_PHY_MODE_NEED_CHANGE 710 711 #define CONFIG_UEC_ETH1 /* ETH1 */ 712 #define CONFIG_HAS_ETH0 713 714 #ifdef CONFIG_UEC_ETH1 715 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 716 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 717 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 718 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 719 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 720 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 721 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 722 #endif /* CONFIG_UEC_ETH1 */ 723 724 #define CONFIG_UEC_ETH5 /* ETH5 */ 725 #define CONFIG_HAS_ETH1 726 727 #ifdef CONFIG_UEC_ETH5 728 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 729 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 730 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 731 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 732 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 733 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 734 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 735 #endif /* CONFIG_UEC_ETH5 */ 736 #endif /* CONFIG_TARGET_P1025RDB */ 737 738 /* 739 * Environment 740 */ 741 #ifdef CONFIG_SPIFLASH 742 #define CONFIG_ENV_SPI_BUS 0 743 #define CONFIG_ENV_SPI_CS 0 744 #define CONFIG_ENV_SPI_MAX_HZ 10000000 745 #define CONFIG_ENV_SPI_MODE 0 746 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 747 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 748 #define CONFIG_ENV_SECT_SIZE 0x10000 749 #elif defined(CONFIG_SDCARD) 750 #define CONFIG_FSL_FIXED_MMC_LOCATION 751 #define CONFIG_ENV_SIZE 0x2000 752 #define CONFIG_SYS_MMC_ENV_DEV 0 753 #elif defined(CONFIG_NAND) 754 #ifdef CONFIG_TPL_BUILD 755 #define CONFIG_ENV_SIZE 0x2000 756 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 757 #else 758 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 759 #endif 760 #define CONFIG_ENV_OFFSET (1024 * 1024) 761 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 762 #elif defined(CONFIG_SYS_RAMBOOT) 763 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 764 #define CONFIG_ENV_SIZE 0x2000 765 #else 766 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 767 #define CONFIG_ENV_SIZE 0x2000 768 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 769 #endif 770 771 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 772 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 773 774 /* 775 * USB 776 */ 777 #define CONFIG_HAS_FSL_DR_USB 778 779 #if defined(CONFIG_HAS_FSL_DR_USB) 780 #ifdef CONFIG_USB_EHCI_HCD 781 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 782 #define CONFIG_USB_EHCI_FSL 783 #define CONFIG_EHCI_DESC_BIG_ENDIAN 784 #endif 785 #endif 786 787 #if defined(CONFIG_TARGET_P1020RDB_PD) 788 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 789 #endif 790 791 #ifdef CONFIG_MMC 792 #define CONFIG_FSL_ESDHC 793 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 794 #endif 795 796 #undef CONFIG_WATCHDOG /* watchdog disabled */ 797 798 /* 799 * Miscellaneous configurable options 800 */ 801 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 802 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 803 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 804 805 /* 806 * For booting Linux, the board info and command line data 807 * have to be in the first 64 MB of memory, since this is 808 * the maximum mapped by the Linux kernel during initialization. 809 */ 810 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 811 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 812 813 #if defined(CONFIG_CMD_KGDB) 814 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 815 #endif 816 817 /* 818 * Environment Configuration 819 */ 820 #define CONFIG_HOSTNAME unknown 821 #define CONFIG_ROOTPATH "/opt/nfsroot" 822 #define CONFIG_BOOTFILE "uImage" 823 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 824 825 /* default location for tftp and bootm */ 826 #define CONFIG_LOADADDR 1000000 827 828 #ifdef __SW_BOOT_NOR 829 #define __NOR_RST_CMD \ 830 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 831 i2c mw 18 3 __SW_BOOT_MASK 1; reset 832 #endif 833 #ifdef __SW_BOOT_SPI 834 #define __SPI_RST_CMD \ 835 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 836 i2c mw 18 3 __SW_BOOT_MASK 1; reset 837 #endif 838 #ifdef __SW_BOOT_SD 839 #define __SD_RST_CMD \ 840 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 841 i2c mw 18 3 __SW_BOOT_MASK 1; reset 842 #endif 843 #ifdef __SW_BOOT_NAND 844 #define __NAND_RST_CMD \ 845 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 846 i2c mw 18 3 __SW_BOOT_MASK 1; reset 847 #endif 848 #ifdef __SW_BOOT_PCIE 849 #define __PCIE_RST_CMD \ 850 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 851 i2c mw 18 3 __SW_BOOT_MASK 1; reset 852 #endif 853 854 #define CONFIG_EXTRA_ENV_SETTINGS \ 855 "netdev=eth0\0" \ 856 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 857 "loadaddr=1000000\0" \ 858 "bootfile=uImage\0" \ 859 "tftpflash=tftpboot $loadaddr $uboot; " \ 860 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 861 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 862 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 863 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 864 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 865 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 866 "consoledev=ttyS0\0" \ 867 "ramdiskaddr=2000000\0" \ 868 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 869 "fdtaddr=1e00000\0" \ 870 "bdev=sda1\0" \ 871 "jffs2nor=mtdblock3\0" \ 872 "norbootaddr=ef080000\0" \ 873 "norfdtaddr=ef040000\0" \ 874 "jffs2nand=mtdblock9\0" \ 875 "nandbootaddr=100000\0" \ 876 "nandfdtaddr=80000\0" \ 877 "ramdisk_size=120000\0" \ 878 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 879 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 880 __stringify(__NOR_RST_CMD)"\0" \ 881 __stringify(__SPI_RST_CMD)"\0" \ 882 __stringify(__SD_RST_CMD)"\0" \ 883 __stringify(__NAND_RST_CMD)"\0" \ 884 __stringify(__PCIE_RST_CMD)"\0" 885 886 #define CONFIG_NFSBOOTCOMMAND \ 887 "setenv bootargs root=/dev/nfs rw " \ 888 "nfsroot=$serverip:$rootpath " \ 889 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 890 "console=$consoledev,$baudrate $othbootargs;" \ 891 "tftp $loadaddr $bootfile;" \ 892 "tftp $fdtaddr $fdtfile;" \ 893 "bootm $loadaddr - $fdtaddr" 894 895 #define CONFIG_HDBOOT \ 896 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 897 "console=$consoledev,$baudrate $othbootargs;" \ 898 "usb start;" \ 899 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 900 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 901 "bootm $loadaddr - $fdtaddr" 902 903 #define CONFIG_USB_FAT_BOOT \ 904 "setenv bootargs root=/dev/ram rw " \ 905 "console=$consoledev,$baudrate $othbootargs " \ 906 "ramdisk_size=$ramdisk_size;" \ 907 "usb start;" \ 908 "fatload usb 0:2 $loadaddr $bootfile;" \ 909 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 910 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 911 "bootm $loadaddr $ramdiskaddr $fdtaddr" 912 913 #define CONFIG_USB_EXT2_BOOT \ 914 "setenv bootargs root=/dev/ram rw " \ 915 "console=$consoledev,$baudrate $othbootargs " \ 916 "ramdisk_size=$ramdisk_size;" \ 917 "usb start;" \ 918 "ext2load usb 0:4 $loadaddr $bootfile;" \ 919 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 920 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 921 "bootm $loadaddr $ramdiskaddr $fdtaddr" 922 923 #define CONFIG_NORBOOT \ 924 "setenv bootargs root=/dev/$jffs2nor rw " \ 925 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 926 "bootm $norbootaddr - $norfdtaddr" 927 928 #define CONFIG_RAMBOOTCOMMAND \ 929 "setenv bootargs root=/dev/ram rw " \ 930 "console=$consoledev,$baudrate $othbootargs " \ 931 "ramdisk_size=$ramdisk_size;" \ 932 "tftp $ramdiskaddr $ramdiskfile;" \ 933 "tftp $loadaddr $bootfile;" \ 934 "tftp $fdtaddr $fdtfile;" \ 935 "bootm $loadaddr $ramdiskaddr $fdtaddr" 936 937 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 938 939 #endif /* __CONFIG_H */ 940