1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 #if defined(CONFIG_P1020MBG) 16 #define CONFIG_BOARDNAME "P1020MBG-PC" 17 #define CONFIG_P1020 18 #define CONFIG_VSC7385_ENET 19 #define CONFIG_SLIC 20 #define __SW_BOOT_MASK 0x03 21 #define __SW_BOOT_NOR 0xe4 22 #define __SW_BOOT_SD 0x54 23 #define CONFIG_SYS_L2_SIZE (256 << 10) 24 #endif 25 26 #if defined(CONFIG_P1020UTM) 27 #define CONFIG_BOARDNAME "P1020UTM-PC" 28 #define CONFIG_P1020 29 #define __SW_BOOT_MASK 0x03 30 #define __SW_BOOT_NOR 0xe0 31 #define __SW_BOOT_SD 0x50 32 #define CONFIG_SYS_L2_SIZE (256 << 10) 33 #endif 34 35 #if defined(CONFIG_P1020RDB_PC) 36 #define CONFIG_BOARDNAME "P1020RDB-PC" 37 #define CONFIG_NAND_FSL_ELBC 38 #define CONFIG_P1020 39 #define CONFIG_VSC7385_ENET 40 #define CONFIG_SLIC 41 #define __SW_BOOT_MASK 0x03 42 #define __SW_BOOT_NOR 0x5c 43 #define __SW_BOOT_SPI 0x1c 44 #define __SW_BOOT_SD 0x9c 45 #define __SW_BOOT_NAND 0xec 46 #define __SW_BOOT_PCIE 0x6c 47 #define CONFIG_SYS_L2_SIZE (256 << 10) 48 #endif 49 50 /* 51 * P1020RDB-PD board has user selectable switches for evaluating different 52 * frequency and boot options for the P1020 device. The table that 53 * follow describe the available options. The front six binary number was in 54 * accordance with SW3[1:6]. 55 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 56 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 57 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 58 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 59 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 60 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 61 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 62 */ 63 #if defined(CONFIG_P1020RDB_PD) 64 #define CONFIG_BOARDNAME "P1020RDB-PD" 65 #define CONFIG_NAND_FSL_ELBC 66 #define CONFIG_P1020 67 #define CONFIG_VSC7385_ENET 68 #define CONFIG_SLIC 69 #define __SW_BOOT_MASK 0x03 70 #define __SW_BOOT_NOR 0x64 71 #define __SW_BOOT_SPI 0x34 72 #define __SW_BOOT_SD 0x24 73 #define __SW_BOOT_NAND 0x44 74 #define __SW_BOOT_PCIE 0x74 75 #define CONFIG_SYS_L2_SIZE (256 << 10) 76 /* 77 * Dynamic MTD Partition support with mtdparts 78 */ 79 #define CONFIG_MTD_DEVICE 80 #define CONFIG_MTD_PARTITIONS 81 #define CONFIG_CMD_MTDPARTS 82 #define CONFIG_FLASH_CFI_MTD 83 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 84 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ 85 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" 86 #endif 87 88 #if defined(CONFIG_P1021RDB) 89 #define CONFIG_BOARDNAME "P1021RDB-PC" 90 #define CONFIG_NAND_FSL_ELBC 91 #define CONFIG_P1021 92 #define CONFIG_QE 93 #define CONFIG_VSC7385_ENET 94 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 95 addresses in the LBC */ 96 #define __SW_BOOT_MASK 0x03 97 #define __SW_BOOT_NOR 0x5c 98 #define __SW_BOOT_SPI 0x1c 99 #define __SW_BOOT_SD 0x9c 100 #define __SW_BOOT_NAND 0xec 101 #define __SW_BOOT_PCIE 0x6c 102 #define CONFIG_SYS_L2_SIZE (256 << 10) 103 /* 104 * Dynamic MTD Partition support with mtdparts 105 */ 106 #define CONFIG_MTD_DEVICE 107 #define CONFIG_MTD_PARTITIONS 108 #define CONFIG_CMD_MTDPARTS 109 #define CONFIG_FLASH_CFI_MTD 110 #ifdef CONFIG_PHYS_64BIT 111 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 112 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 113 "256k(dtb),4608k(kernel),9728k(fs)," \ 114 "256k(qe-ucode-firmware),1280k(u-boot)" 115 #else 116 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 117 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 118 "256k(dtb),4608k(kernel),9728k(fs)," \ 119 "256k(qe-ucode-firmware),1280k(u-boot)" 120 #endif 121 #endif 122 123 #if defined(CONFIG_P1024RDB) 124 #define CONFIG_BOARDNAME "P1024RDB" 125 #define CONFIG_NAND_FSL_ELBC 126 #define CONFIG_P1024 127 #define CONFIG_SLIC 128 #define __SW_BOOT_MASK 0xf3 129 #define __SW_BOOT_NOR 0x00 130 #define __SW_BOOT_SPI 0x08 131 #define __SW_BOOT_SD 0x04 132 #define __SW_BOOT_NAND 0x0c 133 #define CONFIG_SYS_L2_SIZE (256 << 10) 134 #endif 135 136 #if defined(CONFIG_P1025RDB) 137 #define CONFIG_BOARDNAME "P1025RDB" 138 #define CONFIG_NAND_FSL_ELBC 139 #define CONFIG_P1025 140 #define CONFIG_QE 141 #define CONFIG_SLIC 142 143 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 144 addresses in the LBC */ 145 #define __SW_BOOT_MASK 0xf3 146 #define __SW_BOOT_NOR 0x00 147 #define __SW_BOOT_SPI 0x08 148 #define __SW_BOOT_SD 0x04 149 #define __SW_BOOT_NAND 0x0c 150 #define CONFIG_SYS_L2_SIZE (256 << 10) 151 #endif 152 153 #if defined(CONFIG_P2020RDB) 154 #define CONFIG_BOARDNAME "P2020RDB-PCA" 155 #define CONFIG_NAND_FSL_ELBC 156 #define CONFIG_P2020 157 #define CONFIG_VSC7385_ENET 158 #define __SW_BOOT_MASK 0x03 159 #define __SW_BOOT_NOR 0xc8 160 #define __SW_BOOT_SPI 0x28 161 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 162 #define __SW_BOOT_NAND 0xe8 163 #define __SW_BOOT_PCIE 0xa8 164 #define CONFIG_SYS_L2_SIZE (512 << 10) 165 /* 166 * Dynamic MTD Partition support with mtdparts 167 */ 168 #define CONFIG_MTD_DEVICE 169 #define CONFIG_MTD_PARTITIONS 170 #define CONFIG_CMD_MTDPARTS 171 #define CONFIG_FLASH_CFI_MTD 172 #ifdef CONFIG_PHYS_64BIT 173 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 174 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 175 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 176 #else 177 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 178 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 179 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 180 #endif 181 #endif 182 183 #ifdef CONFIG_SDCARD 184 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 185 #define CONFIG_SPL_SERIAL_SUPPORT 186 #define CONFIG_SPL_MMC_SUPPORT 187 #define CONFIG_SPL_MMC_MINIMAL 188 #define CONFIG_SPL_FLUSH_IMAGE 189 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 190 #define CONFIG_SPL_LIBGENERIC_SUPPORT 191 #define CONFIG_FSL_LAW /* Use common FSL init code */ 192 #define CONFIG_SYS_TEXT_BASE 0x11001000 193 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 194 #define CONFIG_SPL_PAD_TO 0x20000 195 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 196 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 197 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 198 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 199 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 200 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 201 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 202 #define CONFIG_SPL_MMC_BOOT 203 #ifdef CONFIG_SPL_BUILD 204 #define CONFIG_SPL_COMMON_INIT_DDR 205 #endif 206 #endif 207 208 #ifdef CONFIG_SPIFLASH 209 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 210 #define CONFIG_SPL_SERIAL_SUPPORT 211 #define CONFIG_SPL_SPI_SUPPORT 212 #define CONFIG_SPL_SPI_FLASH_SUPPORT 213 #define CONFIG_SPL_SPI_FLASH_MINIMAL 214 #define CONFIG_SPL_FLUSH_IMAGE 215 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 216 #define CONFIG_SPL_LIBGENERIC_SUPPORT 217 #define CONFIG_FSL_LAW /* Use common FSL init code */ 218 #define CONFIG_SYS_TEXT_BASE 0x11001000 219 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 220 #define CONFIG_SPL_PAD_TO 0x20000 221 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 222 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 223 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 224 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 225 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 226 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 227 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 228 #define CONFIG_SPL_SPI_BOOT 229 #ifdef CONFIG_SPL_BUILD 230 #define CONFIG_SPL_COMMON_INIT_DDR 231 #endif 232 #endif 233 234 #ifdef CONFIG_NAND 235 #ifdef CONFIG_TPL_BUILD 236 #define CONFIG_SPL_NAND_BOOT 237 #define CONFIG_SPL_FLUSH_IMAGE 238 #define CONFIG_SPL_NAND_INIT 239 #define CONFIG_TPL_SERIAL_SUPPORT 240 #define CONFIG_TPL_LIBGENERIC_SUPPORT 241 #define CONFIG_TPL_NAND_SUPPORT 242 #define CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT 243 #define CONFIG_SPL_COMMON_INIT_DDR 244 #define CONFIG_SPL_MAX_SIZE (128 << 10) 245 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 246 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 247 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 248 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 249 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 250 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 251 #elif defined(CONFIG_SPL_BUILD) 252 #define CONFIG_SPL_INIT_MINIMAL 253 #define CONFIG_SPL_SERIAL_SUPPORT 254 #define CONFIG_SPL_NAND_SUPPORT 255 #define CONFIG_SPL_FLUSH_IMAGE 256 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 257 #define CONFIG_SPL_TEXT_BASE 0xff800000 258 #define CONFIG_SPL_MAX_SIZE 4096 259 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 260 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 261 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 262 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 263 #endif /* not CONFIG_TPL_BUILD */ 264 265 #define CONFIG_SPL_PAD_TO 0x20000 266 #define CONFIG_TPL_PAD_TO 0x20000 267 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 268 #define CONFIG_SYS_TEXT_BASE 0x11001000 269 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 270 #endif 271 272 #ifndef CONFIG_SYS_TEXT_BASE 273 #define CONFIG_SYS_TEXT_BASE 0xeff40000 274 #endif 275 276 #ifndef CONFIG_RESET_VECTOR_ADDRESS 277 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 278 #endif 279 280 #ifndef CONFIG_SYS_MONITOR_BASE 281 #ifdef CONFIG_SPL_BUILD 282 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 283 #else 284 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 285 #endif 286 #endif 287 288 /* High Level Configuration Options */ 289 #define CONFIG_BOOKE 290 #define CONFIG_E500 291 292 #define CONFIG_MP 293 294 #define CONFIG_FSL_ELBC 295 #define CONFIG_PCI 296 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 297 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 298 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 299 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 300 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 301 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 302 303 #define CONFIG_FSL_LAW 304 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 305 #define CONFIG_ENV_OVERWRITE 306 307 #define CONFIG_CMD_SATA 308 #define CONFIG_SATA_SIL 309 #define CONFIG_SYS_SATA_MAX_DEVICE 2 310 #define CONFIG_LIBATA 311 #define CONFIG_LBA48 312 313 #if defined(CONFIG_P2020RDB) 314 #define CONFIG_SYS_CLK_FREQ 100000000 315 #else 316 #define CONFIG_SYS_CLK_FREQ 66666666 317 #endif 318 #define CONFIG_DDR_CLK_FREQ 66666666 319 320 #define CONFIG_HWCONFIG 321 /* 322 * These can be toggled for performance analysis, otherwise use default. 323 */ 324 #define CONFIG_L2_CACHE 325 #define CONFIG_BTB 326 327 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 328 329 #define CONFIG_ENABLE_36BIT_PHYS 330 331 #ifdef CONFIG_PHYS_64BIT 332 #define CONFIG_ADDR_MAP 1 333 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 334 #endif 335 336 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 337 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 338 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 339 340 #define CONFIG_SYS_CCSRBAR 0xffe00000 341 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 342 343 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 344 SPL code*/ 345 #ifdef CONFIG_SPL_BUILD 346 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 347 #endif 348 349 /* DDR Setup */ 350 #define CONFIG_SYS_FSL_DDR3 351 #define CONFIG_SYS_DDR_RAW_TIMING 352 #define CONFIG_DDR_SPD 353 #define CONFIG_SYS_SPD_BUS_NUM 1 354 #define SPD_EEPROM_ADDRESS 0x52 355 #undef CONFIG_FSL_DDR_INTERACTIVE 356 357 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 358 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 359 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 360 #else 361 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 362 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 363 #endif 364 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 365 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 366 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 367 368 #define CONFIG_NUM_DDR_CONTROLLERS 1 369 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 370 371 /* Default settings for DDR3 */ 372 #ifndef CONFIG_P2020RDB 373 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 374 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 375 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 376 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 377 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 378 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 379 380 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 381 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 382 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 383 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 384 385 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 386 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 387 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 388 #define CONFIG_SYS_DDR_RCW_1 0x00000000 389 #define CONFIG_SYS_DDR_RCW_2 0x00000000 390 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 391 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 392 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 393 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 394 395 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 396 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 397 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 398 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 399 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 400 #define CONFIG_SYS_DDR_MODE_1 0x40461520 401 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 402 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 403 #endif 404 405 #undef CONFIG_CLOCKS_IN_MHZ 406 407 /* 408 * Memory map 409 * 410 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 411 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 412 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 413 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 414 * (early boot only) 415 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 416 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 417 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 418 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 419 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 420 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 421 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 422 */ 423 424 /* 425 * Local Bus Definitions 426 */ 427 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 428 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 429 #define CONFIG_SYS_FLASH_BASE 0xec000000 430 #elif defined(CONFIG_P1020UTM) 431 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 432 #define CONFIG_SYS_FLASH_BASE 0xee000000 433 #else 434 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 435 #define CONFIG_SYS_FLASH_BASE 0xef000000 436 #endif 437 438 #ifdef CONFIG_PHYS_64BIT 439 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 440 #else 441 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 442 #endif 443 444 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 445 | BR_PS_16 | BR_V) 446 447 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 448 449 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 450 #define CONFIG_SYS_FLASH_QUIET_TEST 451 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 452 453 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 454 455 #undef CONFIG_SYS_FLASH_CHECKSUM 456 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 457 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 458 459 #define CONFIG_FLASH_CFI_DRIVER 460 #define CONFIG_SYS_FLASH_CFI 461 #define CONFIG_SYS_FLASH_EMPTY_INFO 462 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 463 464 /* Nand Flash */ 465 #ifdef CONFIG_NAND_FSL_ELBC 466 #define CONFIG_SYS_NAND_BASE 0xff800000 467 #ifdef CONFIG_PHYS_64BIT 468 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 469 #else 470 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 471 #endif 472 473 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 474 #define CONFIG_SYS_MAX_NAND_DEVICE 1 475 #define CONFIG_CMD_NAND 476 #if defined(CONFIG_P1020RDB_PD) 477 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 478 #else 479 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 480 #endif 481 482 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 483 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 484 | BR_PS_8 /* Port Size = 8 bit */ \ 485 | BR_MS_FCM /* MSEL = FCM */ \ 486 | BR_V) /* valid */ 487 #if defined(CONFIG_P1020RDB_PD) 488 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 489 | OR_FCM_PGS /* Large Page*/ \ 490 | OR_FCM_CSCT \ 491 | OR_FCM_CST \ 492 | OR_FCM_CHT \ 493 | OR_FCM_SCY_1 \ 494 | OR_FCM_TRLX \ 495 | OR_FCM_EHTR) 496 #else 497 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 498 | OR_FCM_CSCT \ 499 | OR_FCM_CST \ 500 | OR_FCM_CHT \ 501 | OR_FCM_SCY_1 \ 502 | OR_FCM_TRLX \ 503 | OR_FCM_EHTR) 504 #endif 505 #endif /* CONFIG_NAND_FSL_ELBC */ 506 507 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 508 509 #define CONFIG_SYS_INIT_RAM_LOCK 510 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 511 #ifdef CONFIG_PHYS_64BIT 512 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 513 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 514 /* The assembler doesn't like typecast */ 515 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 516 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 517 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 518 #else 519 /* Initial L1 address */ 520 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 521 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 522 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 523 #endif 524 /* Size of used area in RAM */ 525 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 526 527 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 528 GENERATED_GBL_DATA_SIZE) 529 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 530 531 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 532 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 533 534 #define CONFIG_SYS_CPLD_BASE 0xffa00000 535 #ifdef CONFIG_PHYS_64BIT 536 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 537 #else 538 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 539 #endif 540 /* CPLD config size: 1Mb */ 541 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 542 BR_PS_8 | BR_V) 543 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 544 545 #define CONFIG_SYS_PMC_BASE 0xff980000 546 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 547 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 548 BR_PS_8 | BR_V) 549 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 550 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 551 OR_GPCM_EAD) 552 553 #ifdef CONFIG_NAND 554 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 555 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 556 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 557 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 558 #else 559 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 560 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 561 #ifdef CONFIG_NAND_FSL_ELBC 562 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 563 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 564 #endif 565 #endif 566 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 567 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 568 569 /* Vsc7385 switch */ 570 #ifdef CONFIG_VSC7385_ENET 571 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 572 573 #ifdef CONFIG_PHYS_64BIT 574 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 575 #else 576 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 577 #endif 578 579 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 580 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 581 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 582 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 583 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 584 585 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 586 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 587 588 /* The size of the VSC7385 firmware image */ 589 #define CONFIG_VSC7385_IMAGE_SIZE 8192 590 #endif 591 592 /* 593 * Config the L2 Cache as L2 SRAM 594 */ 595 #if defined(CONFIG_SPL_BUILD) 596 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 597 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 598 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 599 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 600 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 601 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 602 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 603 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 604 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 605 #if defined(CONFIG_P2020RDB) 606 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 607 #else 608 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 609 #endif 610 #elif defined(CONFIG_NAND) 611 #ifdef CONFIG_TPL_BUILD 612 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 613 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 614 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 615 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 616 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 617 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 618 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 619 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 620 #else 621 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 622 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 623 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 624 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 625 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 626 #endif /* CONFIG_TPL_BUILD */ 627 #endif 628 #endif 629 630 /* Serial Port - controlled on board with jumper J8 631 * open - index 2 632 * shorted - index 1 633 */ 634 #define CONFIG_CONS_INDEX 1 635 #undef CONFIG_SERIAL_SOFTWARE_FIFO 636 #define CONFIG_SYS_NS16550_SERIAL 637 #define CONFIG_SYS_NS16550_REG_SIZE 1 638 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 639 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 640 #define CONFIG_NS16550_MIN_FUNCTIONS 641 #endif 642 643 #define CONFIG_SYS_BAUDRATE_TABLE \ 644 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 645 646 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 647 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 648 649 /* I2C */ 650 #define CONFIG_SYS_I2C 651 #define CONFIG_SYS_I2C_FSL 652 #define CONFIG_SYS_FSL_I2C_SPEED 400000 653 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 654 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 655 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 656 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 657 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 658 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 659 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 660 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 661 662 /* 663 * I2C2 EEPROM 664 */ 665 #undef CONFIG_ID_EEPROM 666 667 #define CONFIG_RTC_PT7C4338 668 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 669 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 670 671 /* enable read and write access to EEPROM */ 672 #define CONFIG_CMD_EEPROM 673 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 674 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 675 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 676 677 /* 678 * eSPI - Enhanced SPI 679 */ 680 #define CONFIG_HARD_SPI 681 682 #if defined(CONFIG_SPI_FLASH) 683 #define CONFIG_SF_DEFAULT_SPEED 10000000 684 #define CONFIG_SF_DEFAULT_MODE 0 685 #endif 686 687 #if defined(CONFIG_PCI) 688 /* 689 * General PCI 690 * Memory space is mapped 1-1, but I/O space must start from 0. 691 */ 692 693 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 694 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 695 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 696 #ifdef CONFIG_PHYS_64BIT 697 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 698 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 699 #else 700 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 701 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 702 #endif 703 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 704 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 705 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 706 #ifdef CONFIG_PHYS_64BIT 707 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 708 #else 709 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 710 #endif 711 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 712 713 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 714 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 715 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 716 #ifdef CONFIG_PHYS_64BIT 717 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 718 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 719 #else 720 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 721 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 722 #endif 723 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 724 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 725 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 726 #ifdef CONFIG_PHYS_64BIT 727 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 728 #else 729 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 730 #endif 731 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 732 733 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 734 #define CONFIG_CMD_PCI 735 736 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 737 #define CONFIG_DOS_PARTITION 738 #endif /* CONFIG_PCI */ 739 740 #if defined(CONFIG_TSEC_ENET) 741 #define CONFIG_MII /* MII PHY management */ 742 #define CONFIG_TSEC1 743 #define CONFIG_TSEC1_NAME "eTSEC1" 744 #define CONFIG_TSEC2 745 #define CONFIG_TSEC2_NAME "eTSEC2" 746 #define CONFIG_TSEC3 747 #define CONFIG_TSEC3_NAME "eTSEC3" 748 749 #define TSEC1_PHY_ADDR 2 750 #define TSEC2_PHY_ADDR 0 751 #define TSEC3_PHY_ADDR 1 752 753 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 754 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 755 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 756 757 #define TSEC1_PHYIDX 0 758 #define TSEC2_PHYIDX 0 759 #define TSEC3_PHYIDX 0 760 761 #define CONFIG_ETHPRIME "eTSEC1" 762 763 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 764 765 #define CONFIG_HAS_ETH0 766 #define CONFIG_HAS_ETH1 767 #define CONFIG_HAS_ETH2 768 #endif /* CONFIG_TSEC_ENET */ 769 770 #ifdef CONFIG_QE 771 /* QE microcode/firmware address */ 772 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 773 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 774 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 775 #endif /* CONFIG_QE */ 776 777 #ifdef CONFIG_P1025RDB 778 /* 779 * QE UEC ethernet configuration 780 */ 781 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 782 783 #undef CONFIG_UEC_ETH 784 #define CONFIG_PHY_MODE_NEED_CHANGE 785 786 #define CONFIG_UEC_ETH1 /* ETH1 */ 787 #define CONFIG_HAS_ETH0 788 789 #ifdef CONFIG_UEC_ETH1 790 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 791 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 792 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 793 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 794 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 795 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 796 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 797 #endif /* CONFIG_UEC_ETH1 */ 798 799 #define CONFIG_UEC_ETH5 /* ETH5 */ 800 #define CONFIG_HAS_ETH1 801 802 #ifdef CONFIG_UEC_ETH5 803 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 804 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 805 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 806 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 807 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 808 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 809 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 810 #endif /* CONFIG_UEC_ETH5 */ 811 #endif /* CONFIG_P1025RDB */ 812 813 /* 814 * Environment 815 */ 816 #ifdef CONFIG_SPIFLASH 817 #define CONFIG_ENV_IS_IN_SPI_FLASH 818 #define CONFIG_ENV_SPI_BUS 0 819 #define CONFIG_ENV_SPI_CS 0 820 #define CONFIG_ENV_SPI_MAX_HZ 10000000 821 #define CONFIG_ENV_SPI_MODE 0 822 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 823 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 824 #define CONFIG_ENV_SECT_SIZE 0x10000 825 #elif defined(CONFIG_SDCARD) 826 #define CONFIG_ENV_IS_IN_MMC 827 #define CONFIG_FSL_FIXED_MMC_LOCATION 828 #define CONFIG_ENV_SIZE 0x2000 829 #define CONFIG_SYS_MMC_ENV_DEV 0 830 #elif defined(CONFIG_NAND) 831 #ifdef CONFIG_TPL_BUILD 832 #define CONFIG_ENV_SIZE 0x2000 833 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 834 #else 835 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 836 #endif 837 #define CONFIG_ENV_IS_IN_NAND 838 #define CONFIG_ENV_OFFSET (1024 * 1024) 839 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 840 #elif defined(CONFIG_SYS_RAMBOOT) 841 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 842 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 843 #define CONFIG_ENV_SIZE 0x2000 844 #else 845 #define CONFIG_ENV_IS_IN_FLASH 846 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 847 #define CONFIG_ENV_SIZE 0x2000 848 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 849 #endif 850 851 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 852 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 853 854 /* 855 * Command line configuration. 856 */ 857 #define CONFIG_CMD_IRQ 858 #define CONFIG_CMD_DATE 859 #define CONFIG_CMD_REGINFO 860 861 /* 862 * USB 863 */ 864 #define CONFIG_HAS_FSL_DR_USB 865 866 #if defined(CONFIG_HAS_FSL_DR_USB) 867 #define CONFIG_USB_EHCI 868 869 #ifdef CONFIG_USB_EHCI 870 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 871 #define CONFIG_USB_EHCI_FSL 872 #endif 873 #endif 874 875 #if defined(CONFIG_P1020RDB_PD) 876 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 877 #endif 878 879 #define CONFIG_MMC 880 881 #ifdef CONFIG_MMC 882 #define CONFIG_FSL_ESDHC 883 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 884 #define CONFIG_GENERIC_MMC 885 #endif 886 887 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 888 || defined(CONFIG_FSL_SATA) 889 #define CONFIG_DOS_PARTITION 890 #endif 891 892 #undef CONFIG_WATCHDOG /* watchdog disabled */ 893 894 /* 895 * Miscellaneous configurable options 896 */ 897 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 898 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 899 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 900 #if defined(CONFIG_CMD_KGDB) 901 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 902 #else 903 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 904 #endif 905 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 906 /* Print Buffer Size */ 907 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 908 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 909 910 /* 911 * For booting Linux, the board info and command line data 912 * have to be in the first 64 MB of memory, since this is 913 * the maximum mapped by the Linux kernel during initialization. 914 */ 915 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 916 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 917 918 #if defined(CONFIG_CMD_KGDB) 919 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 920 #endif 921 922 /* 923 * Environment Configuration 924 */ 925 #define CONFIG_HOSTNAME unknown 926 #define CONFIG_ROOTPATH "/opt/nfsroot" 927 #define CONFIG_BOOTFILE "uImage" 928 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 929 930 /* default location for tftp and bootm */ 931 #define CONFIG_LOADADDR 1000000 932 933 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 934 935 #define CONFIG_BAUDRATE 115200 936 937 #ifdef __SW_BOOT_NOR 938 #define __NOR_RST_CMD \ 939 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 940 i2c mw 18 3 __SW_BOOT_MASK 1; reset 941 #endif 942 #ifdef __SW_BOOT_SPI 943 #define __SPI_RST_CMD \ 944 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 945 i2c mw 18 3 __SW_BOOT_MASK 1; reset 946 #endif 947 #ifdef __SW_BOOT_SD 948 #define __SD_RST_CMD \ 949 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 950 i2c mw 18 3 __SW_BOOT_MASK 1; reset 951 #endif 952 #ifdef __SW_BOOT_NAND 953 #define __NAND_RST_CMD \ 954 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 955 i2c mw 18 3 __SW_BOOT_MASK 1; reset 956 #endif 957 #ifdef __SW_BOOT_PCIE 958 #define __PCIE_RST_CMD \ 959 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 960 i2c mw 18 3 __SW_BOOT_MASK 1; reset 961 #endif 962 963 #define CONFIG_EXTRA_ENV_SETTINGS \ 964 "netdev=eth0\0" \ 965 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 966 "loadaddr=1000000\0" \ 967 "bootfile=uImage\0" \ 968 "tftpflash=tftpboot $loadaddr $uboot; " \ 969 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 970 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 971 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 972 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 973 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 974 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 975 "consoledev=ttyS0\0" \ 976 "ramdiskaddr=2000000\0" \ 977 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 978 "fdtaddr=1e00000\0" \ 979 "bdev=sda1\0" \ 980 "jffs2nor=mtdblock3\0" \ 981 "norbootaddr=ef080000\0" \ 982 "norfdtaddr=ef040000\0" \ 983 "jffs2nand=mtdblock9\0" \ 984 "nandbootaddr=100000\0" \ 985 "nandfdtaddr=80000\0" \ 986 "ramdisk_size=120000\0" \ 987 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 988 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 989 __stringify(__NOR_RST_CMD)"\0" \ 990 __stringify(__SPI_RST_CMD)"\0" \ 991 __stringify(__SD_RST_CMD)"\0" \ 992 __stringify(__NAND_RST_CMD)"\0" \ 993 __stringify(__PCIE_RST_CMD)"\0" 994 995 #define CONFIG_NFSBOOTCOMMAND \ 996 "setenv bootargs root=/dev/nfs rw " \ 997 "nfsroot=$serverip:$rootpath " \ 998 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 999 "console=$consoledev,$baudrate $othbootargs;" \ 1000 "tftp $loadaddr $bootfile;" \ 1001 "tftp $fdtaddr $fdtfile;" \ 1002 "bootm $loadaddr - $fdtaddr" 1003 1004 #define CONFIG_HDBOOT \ 1005 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 1006 "console=$consoledev,$baudrate $othbootargs;" \ 1007 "usb start;" \ 1008 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 1009 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 1010 "bootm $loadaddr - $fdtaddr" 1011 1012 #define CONFIG_USB_FAT_BOOT \ 1013 "setenv bootargs root=/dev/ram rw " \ 1014 "console=$consoledev,$baudrate $othbootargs " \ 1015 "ramdisk_size=$ramdisk_size;" \ 1016 "usb start;" \ 1017 "fatload usb 0:2 $loadaddr $bootfile;" \ 1018 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 1019 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 1020 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1021 1022 #define CONFIG_USB_EXT2_BOOT \ 1023 "setenv bootargs root=/dev/ram rw " \ 1024 "console=$consoledev,$baudrate $othbootargs " \ 1025 "ramdisk_size=$ramdisk_size;" \ 1026 "usb start;" \ 1027 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1028 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1029 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1030 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1031 1032 #define CONFIG_NORBOOT \ 1033 "setenv bootargs root=/dev/$jffs2nor rw " \ 1034 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1035 "bootm $norbootaddr - $norfdtaddr" 1036 1037 #define CONFIG_RAMBOOTCOMMAND \ 1038 "setenv bootargs root=/dev/ram rw " \ 1039 "console=$consoledev,$baudrate $othbootargs " \ 1040 "ramdisk_size=$ramdisk_size;" \ 1041 "tftp $ramdiskaddr $ramdiskfile;" \ 1042 "tftp $loadaddr $bootfile;" \ 1043 "tftp $fdtaddr $fdtfile;" \ 1044 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1045 1046 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1047 1048 #endif /* __CONFIG_H */ 1049