1 /*
2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 /*
8  * QorIQ RDB boards configuration file
9  */
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 #if defined(CONFIG_TARGET_P1020MBG)
14 #define CONFIG_BOARDNAME "P1020MBG-PC"
15 #define CONFIG_VSC7385_ENET
16 #define CONFIG_SLIC
17 #define __SW_BOOT_MASK		0x03
18 #define __SW_BOOT_NOR		0xe4
19 #define __SW_BOOT_SD		0x54
20 #define CONFIG_SYS_L2_SIZE	(256 << 10)
21 #endif
22 
23 #if defined(CONFIG_TARGET_P1020UTM)
24 #define CONFIG_BOARDNAME "P1020UTM-PC"
25 #define __SW_BOOT_MASK		0x03
26 #define __SW_BOOT_NOR		0xe0
27 #define __SW_BOOT_SD		0x50
28 #define CONFIG_SYS_L2_SIZE	(256 << 10)
29 #endif
30 
31 #if defined(CONFIG_TARGET_P1020RDB_PC)
32 #define CONFIG_BOARDNAME "P1020RDB-PC"
33 #define CONFIG_NAND_FSL_ELBC
34 #define CONFIG_VSC7385_ENET
35 #define CONFIG_SLIC
36 #define __SW_BOOT_MASK		0x03
37 #define __SW_BOOT_NOR		0x5c
38 #define __SW_BOOT_SPI		0x1c
39 #define __SW_BOOT_SD		0x9c
40 #define __SW_BOOT_NAND		0xec
41 #define __SW_BOOT_PCIE		0x6c
42 #define CONFIG_SYS_L2_SIZE	(256 << 10)
43 #endif
44 
45 /*
46  * P1020RDB-PD board has user selectable switches for evaluating different
47  * frequency and boot options for the P1020 device. The table that
48  * follow describe the available options. The front six binary number was in
49  * accordance with SW3[1:6].
50  * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
51  * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
52  * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
53  * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
54  * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
55  * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
56  * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
57  */
58 #if defined(CONFIG_TARGET_P1020RDB_PD)
59 #define CONFIG_BOARDNAME "P1020RDB-PD"
60 #define CONFIG_NAND_FSL_ELBC
61 #define CONFIG_VSC7385_ENET
62 #define CONFIG_SLIC
63 #define __SW_BOOT_MASK		0x03
64 #define __SW_BOOT_NOR		0x64
65 #define __SW_BOOT_SPI		0x34
66 #define __SW_BOOT_SD		0x24
67 #define __SW_BOOT_NAND		0x44
68 #define __SW_BOOT_PCIE		0x74
69 #define CONFIG_SYS_L2_SIZE	(256 << 10)
70 /*
71  * Dynamic MTD Partition support with mtdparts
72  */
73 #define CONFIG_MTD_DEVICE
74 #define CONFIG_MTD_PARTITIONS
75 #define CONFIG_FLASH_CFI_MTD
76 #endif
77 
78 #if defined(CONFIG_TARGET_P1021RDB)
79 #define CONFIG_BOARDNAME "P1021RDB-PC"
80 #define CONFIG_NAND_FSL_ELBC
81 #define CONFIG_QE
82 #define CONFIG_VSC7385_ENET
83 #define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
84 						addresses in the LBC */
85 #define __SW_BOOT_MASK		0x03
86 #define __SW_BOOT_NOR		0x5c
87 #define __SW_BOOT_SPI		0x1c
88 #define __SW_BOOT_SD		0x9c
89 #define __SW_BOOT_NAND		0xec
90 #define __SW_BOOT_PCIE		0x6c
91 #define CONFIG_SYS_L2_SIZE	(256 << 10)
92 /*
93  * Dynamic MTD Partition support with mtdparts
94  */
95 #define CONFIG_MTD_DEVICE
96 #define CONFIG_MTD_PARTITIONS
97 #define CONFIG_FLASH_CFI_MTD
98 #endif
99 
100 #if defined(CONFIG_TARGET_P1024RDB)
101 #define CONFIG_BOARDNAME "P1024RDB"
102 #define CONFIG_NAND_FSL_ELBC
103 #define CONFIG_SLIC
104 #define __SW_BOOT_MASK		0xf3
105 #define __SW_BOOT_NOR		0x00
106 #define __SW_BOOT_SPI		0x08
107 #define __SW_BOOT_SD		0x04
108 #define __SW_BOOT_NAND		0x0c
109 #define CONFIG_SYS_L2_SIZE	(256 << 10)
110 #endif
111 
112 #if defined(CONFIG_TARGET_P1025RDB)
113 #define CONFIG_BOARDNAME "P1025RDB"
114 #define CONFIG_NAND_FSL_ELBC
115 #define CONFIG_QE
116 #define CONFIG_SLIC
117 
118 #define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
119 						addresses in the LBC */
120 #define __SW_BOOT_MASK		0xf3
121 #define __SW_BOOT_NOR		0x00
122 #define __SW_BOOT_SPI		0x08
123 #define __SW_BOOT_SD		0x04
124 #define __SW_BOOT_NAND		0x0c
125 #define CONFIG_SYS_L2_SIZE	(256 << 10)
126 #endif
127 
128 #if defined(CONFIG_TARGET_P2020RDB)
129 #define CONFIG_BOARDNAME "P2020RDB-PC"
130 #define CONFIG_NAND_FSL_ELBC
131 #define CONFIG_VSC7385_ENET
132 #define __SW_BOOT_MASK		0x03
133 #define __SW_BOOT_NOR		0xc8
134 #define __SW_BOOT_SPI		0x28
135 #define __SW_BOOT_SD		0x68 /* or 0x18 */
136 #define __SW_BOOT_NAND		0xe8
137 #define __SW_BOOT_PCIE		0xa8
138 #define CONFIG_SYS_L2_SIZE	(512 << 10)
139 /*
140  * Dynamic MTD Partition support with mtdparts
141  */
142 #define CONFIG_MTD_DEVICE
143 #define CONFIG_MTD_PARTITIONS
144 #define CONFIG_FLASH_CFI_MTD
145 #endif
146 
147 #ifdef CONFIG_SDCARD
148 #define CONFIG_SPL_FLUSH_IMAGE
149 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
150 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
151 #define CONFIG_SPL_PAD_TO		0x20000
152 #define CONFIG_SPL_MAX_SIZE		(128 * 1024)
153 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
154 #define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
155 #define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
156 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(128 << 10)
157 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
158 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
159 #define CONFIG_SPL_MMC_BOOT
160 #ifdef CONFIG_SPL_BUILD
161 #define CONFIG_SPL_COMMON_INIT_DDR
162 #endif
163 #endif
164 
165 #ifdef CONFIG_SPIFLASH
166 #define CONFIG_SPL_SPI_FLASH_MINIMAL
167 #define CONFIG_SPL_FLUSH_IMAGE
168 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
169 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
170 #define CONFIG_SPL_PAD_TO		0x20000
171 #define CONFIG_SPL_MAX_SIZE		(128 * 1024)
172 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
173 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
174 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
175 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(128 << 10)
176 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
177 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
178 #define CONFIG_SPL_SPI_BOOT
179 #ifdef CONFIG_SPL_BUILD
180 #define CONFIG_SPL_COMMON_INIT_DDR
181 #endif
182 #endif
183 
184 #ifdef CONFIG_NAND
185 #ifdef CONFIG_TPL_BUILD
186 #define CONFIG_SPL_NAND_BOOT
187 #define CONFIG_SPL_FLUSH_IMAGE
188 #define CONFIG_SPL_NAND_INIT
189 #define CONFIG_SPL_COMMON_INIT_DDR
190 #define CONFIG_SPL_MAX_SIZE		(128 << 10)
191 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
192 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
193 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
194 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
195 #define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
196 #define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
197 #elif defined(CONFIG_SPL_BUILD)
198 #define CONFIG_SPL_INIT_MINIMAL
199 #define CONFIG_SPL_FLUSH_IMAGE
200 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
201 #define CONFIG_SPL_TEXT_BASE		0xff800000
202 #define CONFIG_SPL_MAX_SIZE		4096
203 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
204 #define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
205 #define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
206 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
207 #endif /* not CONFIG_TPL_BUILD */
208 
209 #define CONFIG_SPL_PAD_TO		0x20000
210 #define CONFIG_TPL_PAD_TO		0x20000
211 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
212 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
213 #endif
214 
215 #ifndef CONFIG_RESET_VECTOR_ADDRESS
216 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
217 #endif
218 
219 #ifndef CONFIG_SYS_MONITOR_BASE
220 #ifdef CONFIG_SPL_BUILD
221 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
222 #else
223 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
224 #endif
225 #endif
226 
227 #define CONFIG_MP
228 
229 #define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
230 #define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
231 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
232 #define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
233 #define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
234 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
235 
236 #define CONFIG_TSEC_ENET	/* tsec ethernet support */
237 #define CONFIG_ENV_OVERWRITE
238 
239 #define CONFIG_SYS_SATA_MAX_DEVICE	2
240 #define CONFIG_LBA48
241 
242 #if defined(CONFIG_TARGET_P2020RDB)
243 #define CONFIG_SYS_CLK_FREQ	100000000
244 #else
245 #define CONFIG_SYS_CLK_FREQ	66666666
246 #endif
247 #define CONFIG_DDR_CLK_FREQ	66666666
248 
249 #define CONFIG_HWCONFIG
250 /*
251  * These can be toggled for performance analysis, otherwise use default.
252  */
253 #define CONFIG_L2_CACHE
254 #define CONFIG_BTB
255 
256 #define CONFIG_ENABLE_36BIT_PHYS
257 
258 #ifdef CONFIG_PHYS_64BIT
259 #define CONFIG_ADDR_MAP			1
260 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
261 #endif
262 
263 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
264 #define CONFIG_SYS_MEMTEST_END		0x1fffffff
265 
266 #define CONFIG_SYS_CCSRBAR		0xffe00000
267 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
268 
269 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
270        SPL code*/
271 #ifdef CONFIG_SPL_BUILD
272 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
273 #endif
274 
275 /* DDR Setup */
276 #define CONFIG_SYS_DDR_RAW_TIMING
277 #define CONFIG_DDR_SPD
278 #define CONFIG_SYS_SPD_BUS_NUM 1
279 #define SPD_EEPROM_ADDRESS 0x52
280 #undef CONFIG_FSL_DDR_INTERACTIVE
281 
282 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
283 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
284 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
285 #else
286 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_1G
287 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
288 #endif
289 #define CONFIG_SYS_SDRAM_SIZE		(1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
290 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
291 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
292 
293 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
294 
295 /* Default settings for DDR3 */
296 #ifndef CONFIG_TARGET_P2020RDB
297 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
298 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
299 #define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
300 #define CONFIG_SYS_DDR_CS1_BNDS		0x0040007f
301 #define CONFIG_SYS_DDR_CS1_CONFIG	0x80014302
302 #define CONFIG_SYS_DDR_CS1_CONFIG_2	0x00000000
303 
304 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
305 #define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
306 #define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
307 #define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
308 
309 #define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
310 #define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8655A608
311 #define CONFIG_SYS_DDR_SR_CNTR		0x00000000
312 #define CONFIG_SYS_DDR_RCW_1		0x00000000
313 #define CONFIG_SYS_DDR_RCW_2		0x00000000
314 #define CONFIG_SYS_DDR_CONTROL		0xC70C0000	/* Type = DDR3	*/
315 #define CONFIG_SYS_DDR_CONTROL_2	0x04401050
316 #define CONFIG_SYS_DDR_TIMING_4		0x00220001
317 #define CONFIG_SYS_DDR_TIMING_5		0x03402400
318 
319 #define CONFIG_SYS_DDR_TIMING_3		0x00020000
320 #define CONFIG_SYS_DDR_TIMING_0		0x00330004
321 #define CONFIG_SYS_DDR_TIMING_1		0x6f6B4846
322 #define CONFIG_SYS_DDR_TIMING_2		0x0FA8C8CF
323 #define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
324 #define CONFIG_SYS_DDR_MODE_1		0x40461520
325 #define CONFIG_SYS_DDR_MODE_2		0x8000c000
326 #define CONFIG_SYS_DDR_INTERVAL		0x0C300000
327 #endif
328 
329 #undef CONFIG_CLOCKS_IN_MHZ
330 
331 /*
332  * Memory map
333  *
334  * 0x0000_0000 0x7fff_ffff	DDR		Up to 2GB cacheable
335  * 0x8000_0000 0xdfff_ffff	PCI Express Mem	1.5G non-cacheable(PCIe * 3)
336  * 0xec00_0000 0xefff_ffff	NOR flash	Up to 64M non-cacheable	CS0/1
337  * 0xf8f8_0000 0xf8ff_ffff	L2 SRAM		Up to 512K cacheable
338  *   (early boot only)
339  * 0xff80_0000 0xff80_7fff	NAND flash	32K non-cacheable	CS1/0
340  * 0xff98_0000 0xff98_ffff	PMC		64K non-cacheable	CS2
341  * 0xffa0_0000 0xffaf_ffff	CPLD		1M non-cacheable	CS3
342  * 0xffb0_0000 0xffbf_ffff	VSC7385 switch  1M non-cacheable	CS2
343  * 0xffc0_0000 0xffc3_ffff	PCI IO range	256k non-cacheable
344  * 0xffd0_0000 0xffd0_3fff	L1 for stack	16K cacheable
345  * 0xffe0_0000 0xffef_ffff	CCSR		1M non-cacheable
346  */
347 
348 /*
349  * Local Bus Definitions
350  */
351 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
352 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
353 #define CONFIG_SYS_FLASH_BASE		0xec000000
354 #elif defined(CONFIG_TARGET_P1020UTM)
355 #define CONFIG_SYS_MAX_FLASH_SECT	256	/* 32M */
356 #define CONFIG_SYS_FLASH_BASE		0xee000000
357 #else
358 #define CONFIG_SYS_MAX_FLASH_SECT	128	/* 16M */
359 #define CONFIG_SYS_FLASH_BASE		0xef000000
360 #endif
361 
362 #ifdef CONFIG_PHYS_64BIT
363 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
364 #else
365 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
366 #endif
367 
368 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
369 	| BR_PS_16 | BR_V)
370 
371 #define CONFIG_FLASH_OR_PRELIM	0xfc000ff7
372 
373 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
374 #define CONFIG_SYS_FLASH_QUIET_TEST
375 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
376 
377 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
378 
379 #undef CONFIG_SYS_FLASH_CHECKSUM
380 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
381 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
382 
383 #define CONFIG_FLASH_CFI_DRIVER
384 #define CONFIG_SYS_FLASH_CFI
385 #define CONFIG_SYS_FLASH_EMPTY_INFO
386 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
387 
388 /* Nand Flash */
389 #ifdef CONFIG_NAND_FSL_ELBC
390 #define CONFIG_SYS_NAND_BASE		0xff800000
391 #ifdef CONFIG_PHYS_64BIT
392 #define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
393 #else
394 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
395 #endif
396 
397 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
398 #define CONFIG_SYS_MAX_NAND_DEVICE	1
399 #if defined(CONFIG_TARGET_P1020RDB_PD)
400 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
401 #else
402 #define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
403 #endif
404 
405 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
406 	| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
407 	| BR_PS_8	/* Port Size = 8 bit */ \
408 	| BR_MS_FCM	/* MSEL = FCM */ \
409 	| BR_V)	/* valid */
410 #if defined(CONFIG_TARGET_P1020RDB_PD)
411 #define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB \
412 	| OR_FCM_PGS	/* Large Page*/ \
413 	| OR_FCM_CSCT \
414 	| OR_FCM_CST \
415 	| OR_FCM_CHT \
416 	| OR_FCM_SCY_1 \
417 	| OR_FCM_TRLX \
418 	| OR_FCM_EHTR)
419 #else
420 #define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB	/* small page */ \
421 	| OR_FCM_CSCT \
422 	| OR_FCM_CST \
423 	| OR_FCM_CHT \
424 	| OR_FCM_SCY_1 \
425 	| OR_FCM_TRLX \
426 	| OR_FCM_EHTR)
427 #endif
428 #endif /* CONFIG_NAND_FSL_ELBC */
429 
430 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
431 
432 #define CONFIG_SYS_INIT_RAM_LOCK
433 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* stack in RAM */
434 #ifdef CONFIG_PHYS_64BIT
435 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
436 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
437 /* The assembler doesn't like typecast */
438 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
439 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
440 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
441 #else
442 /* Initial L1 address */
443 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
444 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
445 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
446 #endif
447 /* Size of used area in RAM */
448 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
449 
450 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
451 					GENERATED_GBL_DATA_SIZE)
452 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
453 
454 #define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
455 #define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)/* Reserved for malloc */
456 
457 #define CONFIG_SYS_CPLD_BASE	0xffa00000
458 #ifdef CONFIG_PHYS_64BIT
459 #define CONFIG_SYS_CPLD_BASE_PHYS	0xfffa00000ull
460 #else
461 #define CONFIG_SYS_CPLD_BASE_PHYS	CONFIG_SYS_CPLD_BASE
462 #endif
463 /* CPLD config size: 1Mb */
464 #define CONFIG_CPLD_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
465 					BR_PS_8 | BR_V)
466 #define CONFIG_CPLD_OR_PRELIM	(0xfff009f7)
467 
468 #define CONFIG_SYS_PMC_BASE	0xff980000
469 #define CONFIG_SYS_PMC_BASE_PHYS	CONFIG_SYS_PMC_BASE
470 #define CONFIG_PMC_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
471 					BR_PS_8 | BR_V)
472 #define CONFIG_PMC_OR_PRELIM	(OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
473 				 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
474 				 OR_GPCM_EAD)
475 
476 #ifdef CONFIG_NAND
477 #define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
478 #define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
479 #define CONFIG_SYS_BR1_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
480 #define CONFIG_SYS_OR1_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
481 #else
482 #define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
483 #define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
484 #ifdef CONFIG_NAND_FSL_ELBC
485 #define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
486 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
487 #endif
488 #endif
489 #define CONFIG_SYS_BR3_PRELIM	CONFIG_CPLD_BR_PRELIM	/* CPLD Base Address */
490 #define CONFIG_SYS_OR3_PRELIM	CONFIG_CPLD_OR_PRELIM	/* CPLD Options */
491 
492 /* Vsc7385 switch */
493 #ifdef CONFIG_VSC7385_ENET
494 #define CONFIG_SYS_VSC7385_BASE		0xffb00000
495 
496 #ifdef CONFIG_PHYS_64BIT
497 #define CONFIG_SYS_VSC7385_BASE_PHYS	0xfffb00000ull
498 #else
499 #define CONFIG_SYS_VSC7385_BASE_PHYS	CONFIG_SYS_VSC7385_BASE
500 #endif
501 
502 #define CONFIG_SYS_VSC7385_BR_PRELIM	\
503 	(BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
504 #define CONFIG_SYS_VSC7385_OR_PRELIM	(OR_AM_128KB | OR_GPCM_CSNT | \
505 			OR_GPCM_XACS |  OR_GPCM_SCY_15 | OR_GPCM_SETA | \
506 			OR_GPCM_TRLX |  OR_GPCM_EHTR | OR_GPCM_EAD)
507 
508 #define CONFIG_SYS_BR2_PRELIM	CONFIG_SYS_VSC7385_BR_PRELIM
509 #define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_VSC7385_OR_PRELIM
510 
511 /* The size of the VSC7385 firmware image */
512 #define CONFIG_VSC7385_IMAGE_SIZE	8192
513 #endif
514 
515 /*
516  * Config the L2 Cache as L2 SRAM
517 */
518 #if defined(CONFIG_SPL_BUILD)
519 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
520 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
521 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
522 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
523 #define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
524 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
525 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
526 #define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
527 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
528 #if defined(CONFIG_TARGET_P2020RDB)
529 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(364 << 10)
530 #else
531 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(108 << 10)
532 #endif
533 #elif defined(CONFIG_NAND)
534 #ifdef CONFIG_TPL_BUILD
535 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
536 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
537 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
538 #define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
539 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
540 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
541 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
542 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
543 #else
544 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
545 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
546 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
547 #define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x2000)
548 #define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
549 #endif /* CONFIG_TPL_BUILD */
550 #endif
551 #endif
552 
553 /* Serial Port - controlled on board with jumper J8
554  * open - index 2
555  * shorted - index 1
556  */
557 #define CONFIG_CONS_INDEX		1
558 #undef CONFIG_SERIAL_SOFTWARE_FIFO
559 #define CONFIG_SYS_NS16550_SERIAL
560 #define CONFIG_SYS_NS16550_REG_SIZE	1
561 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
562 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
563 #define CONFIG_NS16550_MIN_FUNCTIONS
564 #endif
565 
566 #define CONFIG_SYS_BAUDRATE_TABLE	\
567 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
568 
569 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
570 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
571 
572 /* I2C */
573 #define CONFIG_SYS_I2C
574 #define CONFIG_SYS_I2C_FSL
575 #define CONFIG_SYS_FSL_I2C_SPEED	400000
576 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
577 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
578 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
579 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
580 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
581 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
582 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
583 #define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash bank */
584 
585 /*
586  * I2C2 EEPROM
587  */
588 #undef CONFIG_ID_EEPROM
589 
590 #define CONFIG_RTC_PT7C4338
591 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
592 #define CONFIG_SYS_I2C_PCA9557_ADDR	0x18
593 
594 /* enable read and write access to EEPROM */
595 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
596 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
597 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
598 
599 /*
600  * eSPI - Enhanced SPI
601  */
602 #define CONFIG_HARD_SPI
603 
604 #if defined(CONFIG_SPI_FLASH)
605 #define CONFIG_SF_DEFAULT_SPEED	10000000
606 #define CONFIG_SF_DEFAULT_MODE	0
607 #endif
608 
609 #if defined(CONFIG_PCI)
610 /*
611  * General PCI
612  * Memory space is mapped 1-1, but I/O space must start from 0.
613  */
614 
615 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
616 #define CONFIG_SYS_PCIE2_NAME		"PCIe SLOT"
617 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
618 #ifdef CONFIG_PHYS_64BIT
619 #define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
620 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
621 #else
622 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
623 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
624 #endif
625 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
626 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
627 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
628 #ifdef CONFIG_PHYS_64BIT
629 #define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
630 #else
631 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
632 #endif
633 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
634 
635 /* controller 1, Slot 2, tgtid 1, Base address a000 */
636 #define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
637 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
638 #ifdef CONFIG_PHYS_64BIT
639 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
640 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
641 #else
642 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
643 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
644 #endif
645 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
646 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
647 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
648 #ifdef CONFIG_PHYS_64BIT
649 #define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
650 #else
651 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
652 #endif
653 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
654 
655 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
656 #endif /* CONFIG_PCI */
657 
658 #if defined(CONFIG_TSEC_ENET)
659 #define CONFIG_MII		/* MII PHY management */
660 #define CONFIG_TSEC1
661 #define CONFIG_TSEC1_NAME	"eTSEC1"
662 #define CONFIG_TSEC2
663 #define CONFIG_TSEC2_NAME	"eTSEC2"
664 #define CONFIG_TSEC3
665 #define CONFIG_TSEC3_NAME	"eTSEC3"
666 
667 #define TSEC1_PHY_ADDR	2
668 #define TSEC2_PHY_ADDR	0
669 #define TSEC3_PHY_ADDR	1
670 
671 #define TSEC1_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
672 #define TSEC2_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
673 #define TSEC3_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
674 
675 #define TSEC1_PHYIDX	0
676 #define TSEC2_PHYIDX	0
677 #define TSEC3_PHYIDX	0
678 
679 #define CONFIG_ETHPRIME	"eTSEC1"
680 
681 #define CONFIG_HAS_ETH0
682 #define CONFIG_HAS_ETH1
683 #define CONFIG_HAS_ETH2
684 #endif /* CONFIG_TSEC_ENET */
685 
686 #ifdef CONFIG_QE
687 /* QE microcode/firmware address */
688 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
689 #define CONFIG_SYS_QE_FW_ADDR	0xefec0000
690 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
691 #endif /* CONFIG_QE */
692 
693 #ifdef CONFIG_TARGET_P1025RDB
694 /*
695  * QE UEC ethernet configuration
696  */
697 #define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
698 
699 #undef CONFIG_UEC_ETH
700 #define CONFIG_PHY_MODE_NEED_CHANGE
701 
702 #define CONFIG_UEC_ETH1	/* ETH1 */
703 #define CONFIG_HAS_ETH0
704 
705 #ifdef CONFIG_UEC_ETH1
706 #define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
707 #define CONFIG_SYS_UEC1_RX_CLK	QE_CLK12 /* CLK12 for MII */
708 #define CONFIG_SYS_UEC1_TX_CLK	QE_CLK9 /* CLK9 for MII */
709 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
710 #define CONFIG_SYS_UEC1_PHY_ADDR	0x0	/* 0x0 for MII */
711 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
712 #define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
713 #endif /* CONFIG_UEC_ETH1 */
714 
715 #define CONFIG_UEC_ETH5	/* ETH5 */
716 #define CONFIG_HAS_ETH1
717 
718 #ifdef CONFIG_UEC_ETH5
719 #define CONFIG_SYS_UEC5_UCC_NUM	4	/* UCC5 */
720 #define CONFIG_SYS_UEC5_RX_CLK	QE_CLK_NONE
721 #define CONFIG_SYS_UEC5_TX_CLK	QE_CLK13 /* CLK 13 for RMII */
722 #define CONFIG_SYS_UEC5_ETH_TYPE	FAST_ETH
723 #define CONFIG_SYS_UEC5_PHY_ADDR	0x3	/* 0x3 for RMII */
724 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
725 #define CONFIG_SYS_UEC5_INTERFACE_SPEED	100
726 #endif /* CONFIG_UEC_ETH5 */
727 #endif /* CONFIG_TARGET_P1025RDB */
728 
729 /*
730  * Environment
731  */
732 #ifdef CONFIG_SPIFLASH
733 #define CONFIG_ENV_SPI_BUS	0
734 #define CONFIG_ENV_SPI_CS	0
735 #define CONFIG_ENV_SPI_MAX_HZ	10000000
736 #define CONFIG_ENV_SPI_MODE	0
737 #define CONFIG_ENV_SIZE		0x2000	/* 8KB */
738 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
739 #define CONFIG_ENV_SECT_SIZE	0x10000
740 #elif defined(CONFIG_SDCARD)
741 #define CONFIG_FSL_FIXED_MMC_LOCATION
742 #define CONFIG_ENV_SIZE		0x2000
743 #define CONFIG_SYS_MMC_ENV_DEV	0
744 #elif defined(CONFIG_NAND)
745 #ifdef CONFIG_TPL_BUILD
746 #define CONFIG_ENV_SIZE		0x2000
747 #define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
748 #else
749 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
750 #endif
751 #define CONFIG_ENV_OFFSET	(1024 * 1024)
752 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
753 #elif defined(CONFIG_SYS_RAMBOOT)
754 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
755 #define CONFIG_ENV_SIZE		0x2000
756 #else
757 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
758 #define CONFIG_ENV_SIZE		0x2000
759 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
760 #endif
761 
762 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
763 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
764 
765 /*
766  * USB
767  */
768 #define CONFIG_HAS_FSL_DR_USB
769 
770 #if defined(CONFIG_HAS_FSL_DR_USB)
771 #ifdef CONFIG_USB_EHCI_HCD
772 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
773 #define CONFIG_USB_EHCI_FSL
774 #define CONFIG_EHCI_DESC_BIG_ENDIAN
775 #endif
776 #endif
777 
778 #if defined(CONFIG_TARGET_P1020RDB_PD)
779 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
780 #endif
781 
782 #ifdef CONFIG_MMC
783 #define CONFIG_FSL_ESDHC
784 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
785 #endif
786 
787 #undef CONFIG_WATCHDOG	/* watchdog disabled */
788 
789 /*
790  * Miscellaneous configurable options
791  */
792 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
793 
794 /*
795  * For booting Linux, the board info and command line data
796  * have to be in the first 64 MB of memory, since this is
797  * the maximum mapped by the Linux kernel during initialization.
798  */
799 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
800 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
801 
802 #if defined(CONFIG_CMD_KGDB)
803 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
804 #endif
805 
806 /*
807  * Environment Configuration
808  */
809 #define CONFIG_HOSTNAME		unknown
810 #define CONFIG_ROOTPATH		"/opt/nfsroot"
811 #define CONFIG_BOOTFILE		"uImage"
812 #define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
813 
814 /* default location for tftp and bootm */
815 #define CONFIG_LOADADDR	1000000
816 
817 #ifdef __SW_BOOT_NOR
818 #define __NOR_RST_CMD	\
819 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
820 i2c mw 18 3 __SW_BOOT_MASK 1; reset
821 #endif
822 #ifdef __SW_BOOT_SPI
823 #define __SPI_RST_CMD	\
824 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
825 i2c mw 18 3 __SW_BOOT_MASK 1; reset
826 #endif
827 #ifdef __SW_BOOT_SD
828 #define __SD_RST_CMD	\
829 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
830 i2c mw 18 3 __SW_BOOT_MASK 1; reset
831 #endif
832 #ifdef __SW_BOOT_NAND
833 #define __NAND_RST_CMD	\
834 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
835 i2c mw 18 3 __SW_BOOT_MASK 1; reset
836 #endif
837 #ifdef __SW_BOOT_PCIE
838 #define __PCIE_RST_CMD	\
839 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
840 i2c mw 18 3 __SW_BOOT_MASK 1; reset
841 #endif
842 
843 #define	CONFIG_EXTRA_ENV_SETTINGS	\
844 "netdev=eth0\0"	\
845 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
846 "loadaddr=1000000\0"	\
847 "bootfile=uImage\0"	\
848 "tftpflash=tftpboot $loadaddr $uboot; "	\
849 	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
850 	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
851 	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
852 	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
853 	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
854 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
855 "consoledev=ttyS0\0"	\
856 "ramdiskaddr=2000000\0"	\
857 "ramdiskfile=rootfs.ext2.gz.uboot\0"	\
858 "fdtaddr=1e00000\0"	\
859 "bdev=sda1\0" \
860 "jffs2nor=mtdblock3\0"	\
861 "norbootaddr=ef080000\0"	\
862 "norfdtaddr=ef040000\0"	\
863 "jffs2nand=mtdblock9\0"	\
864 "nandbootaddr=100000\0"	\
865 "nandfdtaddr=80000\0"		\
866 "ramdisk_size=120000\0"	\
867 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
868 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
869 __stringify(__NOR_RST_CMD)"\0" \
870 __stringify(__SPI_RST_CMD)"\0" \
871 __stringify(__SD_RST_CMD)"\0" \
872 __stringify(__NAND_RST_CMD)"\0" \
873 __stringify(__PCIE_RST_CMD)"\0"
874 
875 #define CONFIG_NFSBOOTCOMMAND	\
876 "setenv bootargs root=/dev/nfs rw "	\
877 "nfsroot=$serverip:$rootpath "	\
878 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
879 "console=$consoledev,$baudrate $othbootargs;" \
880 "tftp $loadaddr $bootfile;"	\
881 "tftp $fdtaddr $fdtfile;"	\
882 "bootm $loadaddr - $fdtaddr"
883 
884 #define CONFIG_HDBOOT	\
885 "setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
886 "console=$consoledev,$baudrate $othbootargs;" \
887 "usb start;"	\
888 "ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
889 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
890 "bootm $loadaddr - $fdtaddr"
891 
892 #define CONFIG_USB_FAT_BOOT	\
893 "setenv bootargs root=/dev/ram rw "	\
894 "console=$consoledev,$baudrate $othbootargs " \
895 "ramdisk_size=$ramdisk_size;"	\
896 "usb start;"	\
897 "fatload usb 0:2 $loadaddr $bootfile;"	\
898 "fatload usb 0:2 $fdtaddr $fdtfile;"	\
899 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
900 "bootm $loadaddr $ramdiskaddr $fdtaddr"
901 
902 #define CONFIG_USB_EXT2_BOOT	\
903 "setenv bootargs root=/dev/ram rw "	\
904 "console=$consoledev,$baudrate $othbootargs " \
905 "ramdisk_size=$ramdisk_size;"	\
906 "usb start;"	\
907 "ext2load usb 0:4 $loadaddr $bootfile;"	\
908 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
909 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
910 "bootm $loadaddr $ramdiskaddr $fdtaddr"
911 
912 #define CONFIG_NORBOOT	\
913 "setenv bootargs root=/dev/$jffs2nor rw "	\
914 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
915 "bootm $norbootaddr - $norfdtaddr"
916 
917 #define CONFIG_RAMBOOTCOMMAND	\
918 "setenv bootargs root=/dev/ram rw "	\
919 "console=$consoledev,$baudrate $othbootargs " \
920 "ramdisk_size=$ramdisk_size;"	\
921 "tftp $ramdiskaddr $ramdiskfile;"	\
922 "tftp $loadaddr $bootfile;"	\
923 "tftp $fdtaddr $fdtfile;"	\
924 "bootm $loadaddr $ramdiskaddr $fdtaddr"
925 
926 #define CONFIG_BOOTCOMMAND	CONFIG_HDBOOT
927 
928 #endif /* __CONFIG_H */
929