1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #ifdef CONFIG_36BIT 14 #define CONFIG_PHYS_64BIT 15 #endif 16 17 #if defined(CONFIG_P1020MBG) 18 #define CONFIG_BOARDNAME "P1020MBG-PC" 19 #define CONFIG_P1020 20 #define CONFIG_VSC7385_ENET 21 #define CONFIG_SLIC 22 #define __SW_BOOT_MASK 0x03 23 #define __SW_BOOT_NOR 0xe4 24 #define __SW_BOOT_SD 0x54 25 #define CONFIG_SYS_L2_SIZE (256 << 10) 26 #endif 27 28 #if defined(CONFIG_P1020UTM) 29 #define CONFIG_BOARDNAME "P1020UTM-PC" 30 #define CONFIG_P1020 31 #define __SW_BOOT_MASK 0x03 32 #define __SW_BOOT_NOR 0xe0 33 #define __SW_BOOT_SD 0x50 34 #define CONFIG_SYS_L2_SIZE (256 << 10) 35 #endif 36 37 #if defined(CONFIG_P1020RDB_PC) 38 #define CONFIG_BOARDNAME "P1020RDB-PC" 39 #define CONFIG_NAND_FSL_ELBC 40 #define CONFIG_P1020 41 #define CONFIG_SPI_FLASH 42 #define CONFIG_VSC7385_ENET 43 #define CONFIG_SLIC 44 #define __SW_BOOT_MASK 0x03 45 #define __SW_BOOT_NOR 0x5c 46 #define __SW_BOOT_SPI 0x1c 47 #define __SW_BOOT_SD 0x9c 48 #define __SW_BOOT_NAND 0xec 49 #define __SW_BOOT_PCIE 0x6c 50 #define CONFIG_SYS_L2_SIZE (256 << 10) 51 #endif 52 53 /* 54 * P1020RDB-PD board has user selectable switches for evaluating different 55 * frequency and boot options for the P1020 device. The table that 56 * follow describe the available options. The front six binary number was in 57 * accordance with SW3[1:6]. 58 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 59 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 60 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 61 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 62 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 63 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 64 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 65 */ 66 #if defined(CONFIG_P1020RDB_PD) 67 #define CONFIG_BOARDNAME "P1020RDB-PD" 68 #define CONFIG_NAND_FSL_ELBC 69 #define CONFIG_P1020 70 #define CONFIG_SPI_FLASH 71 #define CONFIG_VSC7385_ENET 72 #define CONFIG_SLIC 73 #define __SW_BOOT_MASK 0x03 74 #define __SW_BOOT_NOR 0x64 75 #define __SW_BOOT_SPI 0x34 76 #define __SW_BOOT_SD 0x24 77 #define __SW_BOOT_NAND 0x44 78 #define __SW_BOOT_PCIE 0x74 79 #define CONFIG_SYS_L2_SIZE (256 << 10) 80 #endif 81 82 #if defined(CONFIG_P1021RDB) 83 #define CONFIG_BOARDNAME "P1021RDB-PC" 84 #define CONFIG_NAND_FSL_ELBC 85 #define CONFIG_P1021 86 #define CONFIG_QE 87 #define CONFIG_SPI_FLASH 88 #define CONFIG_VSC7385_ENET 89 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 90 addresses in the LBC */ 91 #define __SW_BOOT_MASK 0x03 92 #define __SW_BOOT_NOR 0x5c 93 #define __SW_BOOT_SPI 0x1c 94 #define __SW_BOOT_SD 0x9c 95 #define __SW_BOOT_NAND 0xec 96 #define __SW_BOOT_PCIE 0x6c 97 #define CONFIG_SYS_L2_SIZE (256 << 10) 98 #endif 99 100 #if defined(CONFIG_P1024RDB) 101 #define CONFIG_BOARDNAME "P1024RDB" 102 #define CONFIG_NAND_FSL_ELBC 103 #define CONFIG_P1024 104 #define CONFIG_SLIC 105 #define CONFIG_SPI_FLASH 106 #define __SW_BOOT_MASK 0xf3 107 #define __SW_BOOT_NOR 0x00 108 #define __SW_BOOT_SPI 0x08 109 #define __SW_BOOT_SD 0x04 110 #define __SW_BOOT_NAND 0x0c 111 #define CONFIG_SYS_L2_SIZE (256 << 10) 112 #endif 113 114 #if defined(CONFIG_P1025RDB) 115 #define CONFIG_BOARDNAME "P1025RDB" 116 #define CONFIG_NAND_FSL_ELBC 117 #define CONFIG_P1025 118 #define CONFIG_QE 119 #define CONFIG_SLIC 120 #define CONFIG_SPI_FLASH 121 122 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 123 addresses in the LBC */ 124 #define __SW_BOOT_MASK 0xf3 125 #define __SW_BOOT_NOR 0x00 126 #define __SW_BOOT_SPI 0x08 127 #define __SW_BOOT_SD 0x04 128 #define __SW_BOOT_NAND 0x0c 129 #define CONFIG_SYS_L2_SIZE (256 << 10) 130 #endif 131 132 #if defined(CONFIG_P2020RDB) 133 #define CONFIG_BOARDNAME "P2020RDB-PCA" 134 #define CONFIG_NAND_FSL_ELBC 135 #define CONFIG_P2020 136 #define CONFIG_SPI_FLASH 137 #define CONFIG_VSC7385_ENET 138 #define __SW_BOOT_MASK 0x03 139 #define __SW_BOOT_NOR 0xc8 140 #define __SW_BOOT_SPI 0x28 141 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 142 #define __SW_BOOT_NAND 0xe8 143 #define __SW_BOOT_PCIE 0xa8 144 #define CONFIG_SYS_L2_SIZE (512 << 10) 145 #endif 146 147 #ifdef CONFIG_SDCARD 148 #define CONFIG_SPL 149 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 150 #define CONFIG_SPL_ENV_SUPPORT 151 #define CONFIG_SPL_SERIAL_SUPPORT 152 #define CONFIG_SPL_MMC_SUPPORT 153 #define CONFIG_SPL_MMC_MINIMAL 154 #define CONFIG_SPL_FLUSH_IMAGE 155 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 156 #define CONFIG_SPL_LIBGENERIC_SUPPORT 157 #define CONFIG_SPL_LIBCOMMON_SUPPORT 158 #define CONFIG_SPL_I2C_SUPPORT 159 #define CONFIG_FSL_LAW /* Use common FSL init code */ 160 #define CONFIG_SYS_TEXT_BASE 0x11001000 161 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 162 #define CONFIG_SPL_PAD_TO 0x20000 163 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 164 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 165 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 166 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 167 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 168 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 169 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 170 #define CONFIG_SPL_MMC_BOOT 171 #ifdef CONFIG_SPL_BUILD 172 #define CONFIG_SPL_COMMON_INIT_DDR 173 #endif 174 #endif 175 176 #ifdef CONFIG_SPIFLASH 177 #define CONFIG_SPL 178 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 179 #define CONFIG_SPL_ENV_SUPPORT 180 #define CONFIG_SPL_SERIAL_SUPPORT 181 #define CONFIG_SPL_SPI_SUPPORT 182 #define CONFIG_SPL_SPI_FLASH_SUPPORT 183 #define CONFIG_SPL_SPI_FLASH_MINIMAL 184 #define CONFIG_SPL_FLUSH_IMAGE 185 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 186 #define CONFIG_SPL_LIBGENERIC_SUPPORT 187 #define CONFIG_SPL_LIBCOMMON_SUPPORT 188 #define CONFIG_SPL_I2C_SUPPORT 189 #define CONFIG_FSL_LAW /* Use common FSL init code */ 190 #define CONFIG_SYS_TEXT_BASE 0x11001000 191 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 192 #define CONFIG_SPL_PAD_TO 0x20000 193 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 194 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 195 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 196 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 197 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 198 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 199 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 200 #define CONFIG_SPL_SPI_BOOT 201 #ifdef CONFIG_SPL_BUILD 202 #define CONFIG_SPL_COMMON_INIT_DDR 203 #endif 204 #endif 205 206 #ifdef CONFIG_NAND 207 #define CONFIG_SPL 208 #define CONFIG_TPL 209 #ifdef CONFIG_TPL_BUILD 210 #define CONFIG_SPL_NAND_BOOT 211 #define CONFIG_SPL_FLUSH_IMAGE 212 #define CONFIG_SPL_ENV_SUPPORT 213 #define CONFIG_SPL_NAND_INIT 214 #define CONFIG_SPL_SERIAL_SUPPORT 215 #define CONFIG_SPL_LIBGENERIC_SUPPORT 216 #define CONFIG_SPL_LIBCOMMON_SUPPORT 217 #define CONFIG_SPL_I2C_SUPPORT 218 #define CONFIG_SPL_NAND_SUPPORT 219 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 220 #define CONFIG_SPL_COMMON_INIT_DDR 221 #define CONFIG_SPL_MAX_SIZE (128 << 10) 222 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 223 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 224 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 225 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 226 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 227 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 228 #elif defined(CONFIG_SPL_BUILD) 229 #define CONFIG_SPL_INIT_MINIMAL 230 #define CONFIG_SPL_SERIAL_SUPPORT 231 #define CONFIG_SPL_NAND_SUPPORT 232 #define CONFIG_SPL_FLUSH_IMAGE 233 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 234 #define CONFIG_SPL_TEXT_BASE 0xff800000 235 #define CONFIG_SPL_MAX_SIZE 4096 236 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 237 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 238 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 239 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 240 #endif /* not CONFIG_TPL_BUILD */ 241 242 #define CONFIG_SPL_PAD_TO 0x20000 243 #define CONFIG_TPL_PAD_TO 0x20000 244 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 245 #define CONFIG_SYS_TEXT_BASE 0x11001000 246 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 247 #endif 248 249 #ifndef CONFIG_SYS_TEXT_BASE 250 #define CONFIG_SYS_TEXT_BASE 0xeff40000 251 #endif 252 253 #ifndef CONFIG_RESET_VECTOR_ADDRESS 254 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 255 #endif 256 257 #ifndef CONFIG_SYS_MONITOR_BASE 258 #ifdef CONFIG_SPL_BUILD 259 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 260 #else 261 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 262 #endif 263 #endif 264 265 /* High Level Configuration Options */ 266 #define CONFIG_BOOKE 267 #define CONFIG_E500 268 269 #define CONFIG_MP 270 271 #define CONFIG_FSL_ELBC 272 #define CONFIG_PCI 273 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 274 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 275 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 276 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 277 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 278 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 279 280 #define CONFIG_FSL_LAW 281 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 282 #define CONFIG_ENV_OVERWRITE 283 284 #define CONFIG_CMD_SATA 285 #define CONFIG_SATA_SIL 286 #define CONFIG_SYS_SATA_MAX_DEVICE 2 287 #define CONFIG_LIBATA 288 #define CONFIG_LBA48 289 290 #if defined(CONFIG_P2020RDB) 291 #define CONFIG_SYS_CLK_FREQ 100000000 292 #else 293 #define CONFIG_SYS_CLK_FREQ 66666666 294 #endif 295 #define CONFIG_DDR_CLK_FREQ 66666666 296 297 #define CONFIG_HWCONFIG 298 /* 299 * These can be toggled for performance analysis, otherwise use default. 300 */ 301 #define CONFIG_L2_CACHE 302 #define CONFIG_BTB 303 304 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 305 306 #define CONFIG_ENABLE_36BIT_PHYS 307 308 #ifdef CONFIG_PHYS_64BIT 309 #define CONFIG_ADDR_MAP 1 310 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 311 #endif 312 313 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 314 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 315 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 316 317 #define CONFIG_SYS_CCSRBAR 0xffe00000 318 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 319 320 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 321 SPL code*/ 322 #ifdef CONFIG_SPL_BUILD 323 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 324 #endif 325 326 /* DDR Setup */ 327 #define CONFIG_SYS_FSL_DDR3 328 #define CONFIG_SYS_DDR_RAW_TIMING 329 #define CONFIG_DDR_SPD 330 #define CONFIG_SYS_SPD_BUS_NUM 1 331 #define SPD_EEPROM_ADDRESS 0x52 332 #undef CONFIG_FSL_DDR_INTERACTIVE 333 334 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 335 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 336 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 337 #else 338 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 339 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 340 #endif 341 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 342 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 343 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 344 345 #define CONFIG_NUM_DDR_CONTROLLERS 1 346 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 347 348 /* Default settings for DDR3 */ 349 #ifndef CONFIG_P2020RDB 350 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 351 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 352 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 353 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 354 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 355 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 356 357 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 358 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 359 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 360 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 361 362 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 363 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 364 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 365 #define CONFIG_SYS_DDR_RCW_1 0x00000000 366 #define CONFIG_SYS_DDR_RCW_2 0x00000000 367 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 368 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 369 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 370 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 371 372 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 373 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 374 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 375 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 376 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 377 #define CONFIG_SYS_DDR_MODE_1 0x40461520 378 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 379 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 380 #endif 381 382 #undef CONFIG_CLOCKS_IN_MHZ 383 384 /* 385 * Memory map 386 * 387 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 388 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 389 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 390 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 391 * (early boot only) 392 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 393 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 394 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 395 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 396 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 397 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 398 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 399 */ 400 401 402 /* 403 * Local Bus Definitions 404 */ 405 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 406 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 407 #define CONFIG_SYS_FLASH_BASE 0xec000000 408 #elif defined(CONFIG_P1020UTM) 409 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 410 #define CONFIG_SYS_FLASH_BASE 0xee000000 411 #else 412 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 413 #define CONFIG_SYS_FLASH_BASE 0xef000000 414 #endif 415 416 417 #ifdef CONFIG_PHYS_64BIT 418 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 419 #else 420 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 421 #endif 422 423 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 424 | BR_PS_16 | BR_V) 425 426 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 427 428 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 429 #define CONFIG_SYS_FLASH_QUIET_TEST 430 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 431 432 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 433 434 #undef CONFIG_SYS_FLASH_CHECKSUM 435 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 436 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 437 438 #define CONFIG_FLASH_CFI_DRIVER 439 #define CONFIG_SYS_FLASH_CFI 440 #define CONFIG_SYS_FLASH_EMPTY_INFO 441 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 442 443 /* Nand Flash */ 444 #ifdef CONFIG_NAND_FSL_ELBC 445 #define CONFIG_SYS_NAND_BASE 0xff800000 446 #ifdef CONFIG_PHYS_64BIT 447 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 448 #else 449 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 450 #endif 451 452 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 453 #define CONFIG_SYS_MAX_NAND_DEVICE 1 454 #define CONFIG_MTD_NAND_VERIFY_WRITE 455 #define CONFIG_CMD_NAND 456 #if defined(CONFIG_P1020RDB_PD) 457 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 458 #else 459 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 460 #endif 461 462 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 463 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 464 | BR_PS_8 /* Port Size = 8 bit */ \ 465 | BR_MS_FCM /* MSEL = FCM */ \ 466 | BR_V) /* valid */ 467 #if defined(CONFIG_P1020RDB_PD) 468 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 469 | OR_FCM_PGS /* Large Page*/ \ 470 | OR_FCM_CSCT \ 471 | OR_FCM_CST \ 472 | OR_FCM_CHT \ 473 | OR_FCM_SCY_1 \ 474 | OR_FCM_TRLX \ 475 | OR_FCM_EHTR) 476 #else 477 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 478 | OR_FCM_CSCT \ 479 | OR_FCM_CST \ 480 | OR_FCM_CHT \ 481 | OR_FCM_SCY_1 \ 482 | OR_FCM_TRLX \ 483 | OR_FCM_EHTR) 484 #endif 485 #endif /* CONFIG_NAND_FSL_ELBC */ 486 487 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 488 489 #define CONFIG_SYS_INIT_RAM_LOCK 490 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 491 #ifdef CONFIG_PHYS_64BIT 492 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 493 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 494 /* The assembler doesn't like typecast */ 495 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 496 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 497 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 498 #else 499 /* Initial L1 address */ 500 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 501 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 502 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 503 #endif 504 /* Size of used area in RAM */ 505 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 506 507 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 508 GENERATED_GBL_DATA_SIZE) 509 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 510 511 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ 512 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 513 514 #define CONFIG_SYS_CPLD_BASE 0xffa00000 515 #ifdef CONFIG_PHYS_64BIT 516 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 517 #else 518 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 519 #endif 520 /* CPLD config size: 1Mb */ 521 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 522 BR_PS_8 | BR_V) 523 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 524 525 #define CONFIG_SYS_PMC_BASE 0xff980000 526 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 527 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 528 BR_PS_8 | BR_V) 529 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 530 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 531 OR_GPCM_EAD) 532 533 #ifdef CONFIG_NAND 534 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 535 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 536 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 537 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 538 #else 539 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 540 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 541 #ifdef CONFIG_NAND_FSL_ELBC 542 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 543 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 544 #endif 545 #endif 546 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 547 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 548 549 550 /* Vsc7385 switch */ 551 #ifdef CONFIG_VSC7385_ENET 552 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 553 554 #ifdef CONFIG_PHYS_64BIT 555 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 556 #else 557 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 558 #endif 559 560 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 561 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 562 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 563 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 564 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 565 566 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 567 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 568 569 /* The size of the VSC7385 firmware image */ 570 #define CONFIG_VSC7385_IMAGE_SIZE 8192 571 #endif 572 573 /* 574 * Config the L2 Cache as L2 SRAM 575 */ 576 #if defined(CONFIG_SPL_BUILD) 577 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 578 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 579 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 580 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 581 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 582 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 583 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 584 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 585 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 586 #if defined(CONFIG_P2020RDB) 587 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 588 #else 589 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 590 #endif 591 #elif defined(CONFIG_NAND) 592 #ifdef CONFIG_TPL_BUILD 593 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 594 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 595 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 596 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 597 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 598 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 599 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 600 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 601 #else 602 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 603 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 604 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 605 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 606 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 607 #endif /* CONFIG_TPL_BUILD */ 608 #endif 609 #endif 610 611 /* Serial Port - controlled on board with jumper J8 612 * open - index 2 613 * shorted - index 1 614 */ 615 #define CONFIG_CONS_INDEX 1 616 #undef CONFIG_SERIAL_SOFTWARE_FIFO 617 #define CONFIG_SYS_NS16550 618 #define CONFIG_SYS_NS16550_SERIAL 619 #define CONFIG_SYS_NS16550_REG_SIZE 1 620 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 621 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 622 #define CONFIG_NS16550_MIN_FUNCTIONS 623 #endif 624 625 #define CONFIG_SYS_BAUDRATE_TABLE \ 626 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 627 628 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 629 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 630 631 /* Use the HUSH parser */ 632 #define CONFIG_SYS_HUSH_PARSER 633 634 /* 635 * Pass open firmware flat tree 636 */ 637 #define CONFIG_OF_LIBFDT 638 #define CONFIG_OF_BOARD_SETUP 639 #define CONFIG_OF_STDOUT_VIA_ALIAS 640 641 /* new uImage format support */ 642 #define CONFIG_FIT 643 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 644 645 /* I2C */ 646 #define CONFIG_SYS_I2C 647 #define CONFIG_SYS_I2C_FSL 648 #define CONFIG_SYS_FSL_I2C_SPEED 400000 649 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 650 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 651 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 652 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 653 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 654 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 655 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 656 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 657 658 /* 659 * I2C2 EEPROM 660 */ 661 #undef CONFIG_ID_EEPROM 662 663 #define CONFIG_RTC_PT7C4338 664 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 665 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 666 667 /* enable read and write access to EEPROM */ 668 #define CONFIG_CMD_EEPROM 669 #define CONFIG_SYS_I2C_MULTI_EEPROMS 670 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 671 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 672 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 673 674 /* 675 * eSPI - Enhanced SPI 676 */ 677 #define CONFIG_HARD_SPI 678 #define CONFIG_FSL_ESPI 679 680 #if defined(CONFIG_SPI_FLASH) 681 #define CONFIG_SPI_FLASH_SPANSION 682 #define CONFIG_CMD_SF 683 #define CONFIG_SF_DEFAULT_SPEED 10000000 684 #define CONFIG_SF_DEFAULT_MODE 0 685 #endif 686 687 #if defined(CONFIG_PCI) 688 /* 689 * General PCI 690 * Memory space is mapped 1-1, but I/O space must start from 0. 691 */ 692 693 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 694 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 695 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 696 #ifdef CONFIG_PHYS_64BIT 697 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 698 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 699 #else 700 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 701 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 702 #endif 703 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 704 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 705 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 706 #ifdef CONFIG_PHYS_64BIT 707 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 708 #else 709 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 710 #endif 711 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 712 713 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 714 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 715 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 716 #ifdef CONFIG_PHYS_64BIT 717 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 718 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 719 #else 720 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 721 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 722 #endif 723 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 724 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 725 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 726 #ifdef CONFIG_PHYS_64BIT 727 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 728 #else 729 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 730 #endif 731 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 732 733 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 734 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ 735 #define CONFIG_CMD_PCI 736 #define CONFIG_CMD_NET 737 738 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 739 #define CONFIG_DOS_PARTITION 740 #endif /* CONFIG_PCI */ 741 742 #if defined(CONFIG_TSEC_ENET) 743 #define CONFIG_MII /* MII PHY management */ 744 #define CONFIG_TSEC1 745 #define CONFIG_TSEC1_NAME "eTSEC1" 746 #define CONFIG_TSEC2 747 #define CONFIG_TSEC2_NAME "eTSEC2" 748 #define CONFIG_TSEC3 749 #define CONFIG_TSEC3_NAME "eTSEC3" 750 751 #define TSEC1_PHY_ADDR 2 752 #define TSEC2_PHY_ADDR 0 753 #define TSEC3_PHY_ADDR 1 754 755 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 756 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 757 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 758 759 #define TSEC1_PHYIDX 0 760 #define TSEC2_PHYIDX 0 761 #define TSEC3_PHYIDX 0 762 763 #define CONFIG_ETHPRIME "eTSEC1" 764 765 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 766 767 #define CONFIG_HAS_ETH0 768 #define CONFIG_HAS_ETH1 769 #define CONFIG_HAS_ETH2 770 #endif /* CONFIG_TSEC_ENET */ 771 772 #ifdef CONFIG_QE 773 /* QE microcode/firmware address */ 774 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 775 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000 776 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 777 #endif /* CONFIG_QE */ 778 779 #ifdef CONFIG_P1025RDB 780 /* 781 * QE UEC ethernet configuration 782 */ 783 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 784 785 #undef CONFIG_UEC_ETH 786 #define CONFIG_PHY_MODE_NEED_CHANGE 787 788 #define CONFIG_UEC_ETH1 /* ETH1 */ 789 #define CONFIG_HAS_ETH0 790 791 #ifdef CONFIG_UEC_ETH1 792 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 793 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 794 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 795 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 796 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 797 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 798 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 799 #endif /* CONFIG_UEC_ETH1 */ 800 801 #define CONFIG_UEC_ETH5 /* ETH5 */ 802 #define CONFIG_HAS_ETH1 803 804 #ifdef CONFIG_UEC_ETH5 805 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 806 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 807 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 808 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 809 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 810 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 811 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 812 #endif /* CONFIG_UEC_ETH5 */ 813 #endif /* CONFIG_P1025RDB */ 814 815 /* 816 * Environment 817 */ 818 #ifdef CONFIG_SPIFLASH 819 #define CONFIG_ENV_IS_IN_SPI_FLASH 820 #define CONFIG_ENV_SPI_BUS 0 821 #define CONFIG_ENV_SPI_CS 0 822 #define CONFIG_ENV_SPI_MAX_HZ 10000000 823 #define CONFIG_ENV_SPI_MODE 0 824 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 825 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 826 #define CONFIG_ENV_SECT_SIZE 0x10000 827 #elif defined(CONFIG_SDCARD) 828 #define CONFIG_ENV_IS_IN_MMC 829 #define CONFIG_FSL_FIXED_MMC_LOCATION 830 #define CONFIG_ENV_SIZE 0x2000 831 #define CONFIG_SYS_MMC_ENV_DEV 0 832 #elif defined(CONFIG_NAND) 833 #ifdef CONFIG_TPL_BUILD 834 #define CONFIG_ENV_SIZE 0x2000 835 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 836 #else 837 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 838 #endif 839 #define CONFIG_ENV_IS_IN_NAND 840 #define CONFIG_ENV_OFFSET (1024 * 1024) 841 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 842 #elif defined(CONFIG_SYS_RAMBOOT) 843 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 844 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 845 #define CONFIG_ENV_SIZE 0x2000 846 #else 847 #define CONFIG_ENV_IS_IN_FLASH 848 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 849 #define CONFIG_ENV_SIZE 0x2000 850 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 851 #endif 852 853 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 854 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 855 856 /* 857 * Command line configuration. 858 */ 859 #include <config_cmd_default.h> 860 861 #define CONFIG_CMD_IRQ 862 #define CONFIG_CMD_PING 863 #define CONFIG_CMD_I2C 864 #define CONFIG_CMD_MII 865 #define CONFIG_CMD_DATE 866 #define CONFIG_CMD_ELF 867 #define CONFIG_CMD_SETEXPR 868 #define CONFIG_CMD_REGINFO 869 870 /* 871 * USB 872 */ 873 #define CONFIG_HAS_FSL_DR_USB 874 875 #if defined(CONFIG_HAS_FSL_DR_USB) 876 #define CONFIG_USB_EHCI 877 878 #ifdef CONFIG_USB_EHCI 879 #define CONFIG_CMD_USB 880 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 881 #define CONFIG_USB_EHCI_FSL 882 #define CONFIG_USB_STORAGE 883 #endif 884 #endif 885 886 #define CONFIG_MMC 887 888 #ifdef CONFIG_MMC 889 #define CONFIG_FSL_ESDHC 890 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 891 #define CONFIG_CMD_MMC 892 #define CONFIG_GENERIC_MMC 893 #endif 894 895 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 896 || defined(CONFIG_FSL_SATA) 897 #define CONFIG_CMD_EXT2 898 #define CONFIG_CMD_FAT 899 #define CONFIG_DOS_PARTITION 900 #endif 901 902 #undef CONFIG_WATCHDOG /* watchdog disabled */ 903 904 /* 905 * Miscellaneous configurable options 906 */ 907 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 908 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 909 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 910 #if defined(CONFIG_CMD_KGDB) 911 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 912 #else 913 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 914 #endif 915 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 916 /* Print Buffer Size */ 917 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 918 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 919 920 /* 921 * For booting Linux, the board info and command line data 922 * have to be in the first 64 MB of memory, since this is 923 * the maximum mapped by the Linux kernel during initialization. 924 */ 925 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 926 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 927 928 #if defined(CONFIG_CMD_KGDB) 929 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 930 #endif 931 932 /* 933 * Environment Configuration 934 */ 935 #define CONFIG_HOSTNAME unknown 936 #define CONFIG_ROOTPATH "/opt/nfsroot" 937 #define CONFIG_BOOTFILE "uImage" 938 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 939 940 /* default location for tftp and bootm */ 941 #define CONFIG_LOADADDR 1000000 942 943 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 944 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 945 946 #define CONFIG_BAUDRATE 115200 947 948 #ifdef __SW_BOOT_NOR 949 #define __NOR_RST_CMD \ 950 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 951 i2c mw 18 3 __SW_BOOT_MASK 1; reset 952 #endif 953 #ifdef __SW_BOOT_SPI 954 #define __SPI_RST_CMD \ 955 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 956 i2c mw 18 3 __SW_BOOT_MASK 1; reset 957 #endif 958 #ifdef __SW_BOOT_SD 959 #define __SD_RST_CMD \ 960 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 961 i2c mw 18 3 __SW_BOOT_MASK 1; reset 962 #endif 963 #ifdef __SW_BOOT_NAND 964 #define __NAND_RST_CMD \ 965 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 966 i2c mw 18 3 __SW_BOOT_MASK 1; reset 967 #endif 968 #ifdef __SW_BOOT_PCIE 969 #define __PCIE_RST_CMD \ 970 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 971 i2c mw 18 3 __SW_BOOT_MASK 1; reset 972 #endif 973 974 #define CONFIG_EXTRA_ENV_SETTINGS \ 975 "netdev=eth0\0" \ 976 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 977 "loadaddr=1000000\0" \ 978 "bootfile=uImage\0" \ 979 "tftpflash=tftpboot $loadaddr $uboot; " \ 980 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 981 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 982 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 983 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 984 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 985 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 986 "consoledev=ttyS0\0" \ 987 "ramdiskaddr=2000000\0" \ 988 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 989 "fdtaddr=c00000\0" \ 990 "bdev=sda1\0" \ 991 "jffs2nor=mtdblock3\0" \ 992 "norbootaddr=ef080000\0" \ 993 "norfdtaddr=ef040000\0" \ 994 "jffs2nand=mtdblock9\0" \ 995 "nandbootaddr=100000\0" \ 996 "nandfdtaddr=80000\0" \ 997 "ramdisk_size=120000\0" \ 998 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 999 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 1000 __stringify(__NOR_RST_CMD)"\0" \ 1001 __stringify(__SPI_RST_CMD)"\0" \ 1002 __stringify(__SD_RST_CMD)"\0" \ 1003 __stringify(__NAND_RST_CMD)"\0" \ 1004 __stringify(__PCIE_RST_CMD)"\0" 1005 1006 #define CONFIG_NFSBOOTCOMMAND \ 1007 "setenv bootargs root=/dev/nfs rw " \ 1008 "nfsroot=$serverip:$rootpath " \ 1009 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 1010 "console=$consoledev,$baudrate $othbootargs;" \ 1011 "tftp $loadaddr $bootfile;" \ 1012 "tftp $fdtaddr $fdtfile;" \ 1013 "bootm $loadaddr - $fdtaddr" 1014 1015 #define CONFIG_HDBOOT \ 1016 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 1017 "console=$consoledev,$baudrate $othbootargs;" \ 1018 "usb start;" \ 1019 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 1020 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 1021 "bootm $loadaddr - $fdtaddr" 1022 1023 #define CONFIG_USB_FAT_BOOT \ 1024 "setenv bootargs root=/dev/ram rw " \ 1025 "console=$consoledev,$baudrate $othbootargs " \ 1026 "ramdisk_size=$ramdisk_size;" \ 1027 "usb start;" \ 1028 "fatload usb 0:2 $loadaddr $bootfile;" \ 1029 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 1030 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 1031 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1032 1033 #define CONFIG_USB_EXT2_BOOT \ 1034 "setenv bootargs root=/dev/ram rw " \ 1035 "console=$consoledev,$baudrate $othbootargs " \ 1036 "ramdisk_size=$ramdisk_size;" \ 1037 "usb start;" \ 1038 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1039 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1040 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1041 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1042 1043 #define CONFIG_NORBOOT \ 1044 "setenv bootargs root=/dev/$jffs2nor rw " \ 1045 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1046 "bootm $norbootaddr - $norfdtaddr" 1047 1048 #define CONFIG_RAMBOOTCOMMAND \ 1049 "setenv bootargs root=/dev/ram rw " \ 1050 "console=$consoledev,$baudrate $othbootargs " \ 1051 "ramdisk_size=$ramdisk_size;" \ 1052 "tftp $ramdiskaddr $ramdiskfile;" \ 1053 "tftp $loadaddr $bootfile;" \ 1054 "tftp $fdtaddr $fdtfile;" \ 1055 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1056 1057 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1058 1059 #endif /* __CONFIG_H */ 1060