1 /*
2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 /*
8  * QorIQ RDB boards configuration file
9  */
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 #ifdef CONFIG_36BIT
14 #define CONFIG_PHYS_64BIT
15 #endif
16 
17 #if defined(CONFIG_P1020MBG)
18 #define CONFIG_BOARDNAME "P1020MBG-PC"
19 #define CONFIG_P1020
20 #define CONFIG_VSC7385_ENET
21 #define CONFIG_SLIC
22 #define __SW_BOOT_MASK		0x03
23 #define __SW_BOOT_NOR		0xe4
24 #define __SW_BOOT_SD		0x54
25 #define CONFIG_SYS_L2_SIZE	(256 << 10)
26 #endif
27 
28 #if defined(CONFIG_P1020UTM)
29 #define CONFIG_BOARDNAME "P1020UTM-PC"
30 #define CONFIG_P1020
31 #define __SW_BOOT_MASK		0x03
32 #define __SW_BOOT_NOR		0xe0
33 #define __SW_BOOT_SD		0x50
34 #define CONFIG_SYS_L2_SIZE	(256 << 10)
35 #endif
36 
37 #if defined(CONFIG_P1020RDB_PC)
38 #define CONFIG_BOARDNAME "P1020RDB-PC"
39 #define CONFIG_NAND_FSL_ELBC
40 #define CONFIG_P1020
41 #define CONFIG_SPI_FLASH
42 #define CONFIG_VSC7385_ENET
43 #define CONFIG_SLIC
44 #define __SW_BOOT_MASK		0x03
45 #define __SW_BOOT_NOR		0x5c
46 #define __SW_BOOT_SPI		0x1c
47 #define __SW_BOOT_SD		0x9c
48 #define __SW_BOOT_NAND		0xec
49 #define __SW_BOOT_PCIE		0x6c
50 #define CONFIG_SYS_L2_SIZE	(256 << 10)
51 #endif
52 
53 /*
54  * P1020RDB-PD board has user selectable switches for evaluating different
55  * frequency and boot options for the P1020 device. The table that
56  * follow describe the available options. The front six binary number was in
57  * accordance with SW3[1:6].
58  * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
59  * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
60  * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
61  * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
62  * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
63  * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
64  * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
65  */
66 #if defined(CONFIG_P1020RDB_PD)
67 #define CONFIG_BOARDNAME "P1020RDB-PD"
68 #define CONFIG_NAND_FSL_ELBC
69 #define CONFIG_P1020
70 #define CONFIG_SPI_FLASH
71 #define CONFIG_VSC7385_ENET
72 #define CONFIG_SLIC
73 #define __SW_BOOT_MASK		0x03
74 #define __SW_BOOT_NOR		0x64
75 #define __SW_BOOT_SPI		0x34
76 #define __SW_BOOT_SD		0x24
77 #define __SW_BOOT_NAND		0x44
78 #define __SW_BOOT_PCIE		0x74
79 #define CONFIG_SYS_L2_SIZE	(256 << 10)
80 #endif
81 
82 #if defined(CONFIG_P1021RDB)
83 #define CONFIG_BOARDNAME "P1021RDB-PC"
84 #define CONFIG_NAND_FSL_ELBC
85 #define CONFIG_P1021
86 #define CONFIG_QE
87 #define CONFIG_SPI_FLASH
88 #define CONFIG_VSC7385_ENET
89 #define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
90 						addresses in the LBC */
91 #define __SW_BOOT_MASK		0x03
92 #define __SW_BOOT_NOR		0x5c
93 #define __SW_BOOT_SPI		0x1c
94 #define __SW_BOOT_SD		0x9c
95 #define __SW_BOOT_NAND		0xec
96 #define __SW_BOOT_PCIE		0x6c
97 #define CONFIG_SYS_L2_SIZE	(256 << 10)
98 #endif
99 
100 #if defined(CONFIG_P1024RDB)
101 #define CONFIG_BOARDNAME "P1024RDB"
102 #define CONFIG_NAND_FSL_ELBC
103 #define CONFIG_P1024
104 #define CONFIG_SLIC
105 #define CONFIG_SPI_FLASH
106 #define __SW_BOOT_MASK		0xf3
107 #define __SW_BOOT_NOR		0x00
108 #define __SW_BOOT_SPI		0x08
109 #define __SW_BOOT_SD		0x04
110 #define __SW_BOOT_NAND		0x0c
111 #define CONFIG_SYS_L2_SIZE	(256 << 10)
112 #endif
113 
114 #if defined(CONFIG_P1025RDB)
115 #define CONFIG_BOARDNAME "P1025RDB"
116 #define CONFIG_NAND_FSL_ELBC
117 #define CONFIG_P1025
118 #define CONFIG_QE
119 #define CONFIG_SLIC
120 #define CONFIG_SPI_FLASH
121 
122 #define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
123 						addresses in the LBC */
124 #define __SW_BOOT_MASK		0xf3
125 #define __SW_BOOT_NOR		0x00
126 #define __SW_BOOT_SPI		0x08
127 #define __SW_BOOT_SD		0x04
128 #define __SW_BOOT_NAND		0x0c
129 #define CONFIG_SYS_L2_SIZE	(256 << 10)
130 #endif
131 
132 #if defined(CONFIG_P2020RDB)
133 #define CONFIG_BOARDNAME "P2020RDB-PCA"
134 #define CONFIG_NAND_FSL_ELBC
135 #define CONFIG_P2020
136 #define CONFIG_SPI_FLASH
137 #define CONFIG_VSC7385_ENET
138 #define __SW_BOOT_MASK		0x03
139 #define __SW_BOOT_NOR		0xc8
140 #define __SW_BOOT_SPI		0x28
141 #define __SW_BOOT_SD		0x68 /* or 0x18 */
142 #define __SW_BOOT_NAND		0xe8
143 #define __SW_BOOT_PCIE		0xa8
144 #define CONFIG_SYS_L2_SIZE	(512 << 10)
145 #endif
146 
147 #ifdef CONFIG_SDCARD
148 #define CONFIG_SPL
149 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
150 #define CONFIG_SPL_ENV_SUPPORT
151 #define CONFIG_SPL_SERIAL_SUPPORT
152 #define CONFIG_SPL_MMC_SUPPORT
153 #define CONFIG_SPL_MMC_MINIMAL
154 #define CONFIG_SPL_FLUSH_IMAGE
155 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
156 #define CONFIG_SPL_LIBGENERIC_SUPPORT
157 #define CONFIG_SPL_LIBCOMMON_SUPPORT
158 #define CONFIG_SPL_I2C_SUPPORT
159 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
160 #define CONFIG_SYS_TEXT_BASE		0x11001000
161 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
162 #define CONFIG_SPL_PAD_TO		0x18000
163 #define CONFIG_SPL_MAX_SIZE		(96 * 1024)
164 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(512 << 10)
165 #define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
166 #define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
167 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(96 << 10)
168 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
169 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
170 #define CONFIG_SPL_MMC_BOOT
171 #ifdef CONFIG_SPL_BUILD
172 #define CONFIG_SPL_COMMON_INIT_DDR
173 #endif
174 #endif
175 
176 #ifdef CONFIG_SPIFLASH
177 #define CONFIG_SPL
178 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
179 #define CONFIG_SPL_ENV_SUPPORT
180 #define CONFIG_SPL_SERIAL_SUPPORT
181 #define CONFIG_SPL_SPI_SUPPORT
182 #define CONFIG_SPL_SPI_FLASH_SUPPORT
183 #define CONFIG_SPL_SPI_FLASH_MINIMAL
184 #define CONFIG_SPL_FLUSH_IMAGE
185 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
186 #define CONFIG_SPL_LIBGENERIC_SUPPORT
187 #define CONFIG_SPL_LIBCOMMON_SUPPORT
188 #define CONFIG_SPL_I2C_SUPPORT
189 #define CONFIG_FSL_LAW         /* Use common FSL init code */
190 #define CONFIG_SYS_TEXT_BASE		0x11001000
191 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
192 #define CONFIG_SPL_PAD_TO		0x18000
193 #define CONFIG_SPL_MAX_SIZE		(96 * 1024)
194 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(512 << 10)
195 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
196 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
197 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(96 << 10)
198 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
199 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
200 #define CONFIG_SPL_SPI_BOOT
201 #ifdef CONFIG_SPL_BUILD
202 #define CONFIG_SPL_COMMON_INIT_DDR
203 #endif
204 #endif
205 
206 #ifdef CONFIG_NAND
207 #define CONFIG_SPL
208 #define CONFIG_TPL
209 #ifdef CONFIG_TPL_BUILD
210 #define CONFIG_SPL_NAND_BOOT
211 #define CONFIG_SPL_FLUSH_IMAGE
212 #define CONFIG_SPL_ENV_SUPPORT
213 #define CONFIG_SPL_NAND_INIT
214 #define CONFIG_SPL_SERIAL_SUPPORT
215 #define CONFIG_SPL_LIBGENERIC_SUPPORT
216 #define CONFIG_SPL_LIBCOMMON_SUPPORT
217 #define CONFIG_SPL_I2C_SUPPORT
218 #define CONFIG_SPL_NAND_SUPPORT
219 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
220 #define CONFIG_SPL_COMMON_INIT_DDR
221 #define CONFIG_SPL_MAX_SIZE		(128 << 10)
222 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
223 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
224 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(576 << 10)
225 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
226 #define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
227 #define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
228 #elif defined(CONFIG_SPL_BUILD)
229 #define CONFIG_SPL_INIT_MINIMAL
230 #define CONFIG_SPL_SERIAL_SUPPORT
231 #define CONFIG_SPL_NAND_SUPPORT
232 #define CONFIG_SPL_FLUSH_IMAGE
233 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
234 #define CONFIG_SPL_TEXT_BASE		0xff800000
235 #define CONFIG_SPL_MAX_SIZE		4096
236 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
237 #define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
238 #define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
239 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
240 #endif /* not CONFIG_TPL_BUILD */
241 
242 #define CONFIG_SPL_PAD_TO		0x20000
243 #define CONFIG_TPL_PAD_TO		0x20000
244 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
245 #define CONFIG_SYS_TEXT_BASE		0x11001000
246 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
247 #endif
248 
249 #ifndef CONFIG_SYS_TEXT_BASE
250 #define CONFIG_SYS_TEXT_BASE		0xeff80000
251 #endif
252 
253 #ifndef CONFIG_RESET_VECTOR_ADDRESS
254 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
255 #endif
256 
257 #ifndef CONFIG_SYS_MONITOR_BASE
258 #ifdef CONFIG_SPL_BUILD
259 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
260 #else
261 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
262 #endif
263 #endif
264 
265 /* High Level Configuration Options */
266 #define CONFIG_BOOKE
267 #define CONFIG_E500
268 #define CONFIG_MPC85xx
269 
270 #define CONFIG_MP
271 
272 #define CONFIG_FSL_ELBC
273 #define CONFIG_PCI
274 #define CONFIG_PCIE1	/* PCIE controler 1 (slot 1) */
275 #define CONFIG_PCIE2	/* PCIE controler 2 (slot 2) */
276 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
277 #define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
278 #define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
279 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
280 
281 #define CONFIG_FSL_LAW
282 #define CONFIG_TSEC_ENET	/* tsec ethernet support */
283 #define CONFIG_ENV_OVERWRITE
284 
285 #define CONFIG_CMD_SATA
286 #define CONFIG_SATA_SIL
287 #define CONFIG_SYS_SATA_MAX_DEVICE	2
288 #define CONFIG_LIBATA
289 #define CONFIG_LBA48
290 
291 #if defined(CONFIG_P2020RDB)
292 #define CONFIG_SYS_CLK_FREQ	100000000
293 #else
294 #define CONFIG_SYS_CLK_FREQ	66666666
295 #endif
296 #define CONFIG_DDR_CLK_FREQ	66666666
297 
298 #define CONFIG_HWCONFIG
299 /*
300  * These can be toggled for performance analysis, otherwise use default.
301  */
302 #define CONFIG_L2_CACHE
303 #define CONFIG_BTB
304 
305 #define CONFIG_BOARD_EARLY_INIT_F	/* Call board_pre_init */
306 
307 #define CONFIG_ENABLE_36BIT_PHYS
308 
309 #ifdef CONFIG_PHYS_64BIT
310 #define CONFIG_ADDR_MAP			1
311 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
312 #endif
313 
314 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
315 #define CONFIG_SYS_MEMTEST_END		0x1fffffff
316 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
317 
318 #define CONFIG_SYS_CCSRBAR		0xffe00000
319 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
320 
321 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
322        SPL code*/
323 #ifdef CONFIG_SPL_BUILD
324 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
325 #endif
326 
327 /* DDR Setup */
328 #define CONFIG_FSL_DDR3
329 #define CONFIG_SYS_DDR_RAW_TIMING
330 #define CONFIG_DDR_SPD
331 #define CONFIG_SYS_SPD_BUS_NUM 1
332 #define SPD_EEPROM_ADDRESS 0x52
333 #undef CONFIG_FSL_DDR_INTERACTIVE
334 
335 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
336 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
337 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
338 #else
339 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_1G
340 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
341 #endif
342 #define CONFIG_SYS_SDRAM_SIZE		(1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
343 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
344 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
345 
346 #define CONFIG_NUM_DDR_CONTROLLERS	1
347 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
348 
349 /* Default settings for DDR3 */
350 #ifndef CONFIG_P2020RDB
351 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
352 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
353 #define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
354 #define CONFIG_SYS_DDR_CS1_BNDS		0x0040007f
355 #define CONFIG_SYS_DDR_CS1_CONFIG	0x80014302
356 #define CONFIG_SYS_DDR_CS1_CONFIG_2	0x00000000
357 
358 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
359 #define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
360 #define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
361 #define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
362 
363 #define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
364 #define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8655A608
365 #define CONFIG_SYS_DDR_SR_CNTR		0x00000000
366 #define CONFIG_SYS_DDR_RCW_1		0x00000000
367 #define CONFIG_SYS_DDR_RCW_2		0x00000000
368 #define CONFIG_SYS_DDR_CONTROL		0xC70C0000	/* Type = DDR3	*/
369 #define CONFIG_SYS_DDR_CONTROL_2	0x04401050
370 #define CONFIG_SYS_DDR_TIMING_4		0x00220001
371 #define CONFIG_SYS_DDR_TIMING_5		0x03402400
372 
373 #define CONFIG_SYS_DDR_TIMING_3		0x00020000
374 #define CONFIG_SYS_DDR_TIMING_0		0x00330004
375 #define CONFIG_SYS_DDR_TIMING_1		0x6f6B4846
376 #define CONFIG_SYS_DDR_TIMING_2		0x0FA8C8CF
377 #define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
378 #define CONFIG_SYS_DDR_MODE_1		0x40461520
379 #define CONFIG_SYS_DDR_MODE_2		0x8000c000
380 #define CONFIG_SYS_DDR_INTERVAL		0x0C300000
381 #endif
382 
383 #undef CONFIG_CLOCKS_IN_MHZ
384 
385 /*
386  * Memory map
387  *
388  * 0x0000_0000 0x7fff_ffff	DDR		Up to 2GB cacheable
389  * 0x8000_0000 0xdfff_ffff	PCI Express Mem	1.5G non-cacheable(PCIe * 3)
390  * 0xec00_0000 0xefff_ffff	NOR flash	Up to 64M non-cacheable	CS0/1
391  * 0xf8f8_0000 0xf8ff_ffff	L2 SRAM		Up to 512K cacheable
392  *   (early boot only)
393  * 0xff80_0000 0xff80_7fff	NAND flash	32K non-cacheable	CS1/0
394  * 0xff98_0000 0xff98_ffff	PMC		64K non-cacheable	CS2
395  * 0xffa0_0000 0xffaf_ffff	CPLD		1M non-cacheable	CS3
396  * 0xffb0_0000 0xffbf_ffff	VSC7385 switch  1M non-cacheable	CS2
397  * 0xffc0_0000 0xffc3_ffff	PCI IO range	256k non-cacheable
398  * 0xffd0_0000 0xffd0_3fff	L1 for stack	16K cacheable
399  * 0xffe0_0000 0xffef_ffff	CCSR		1M non-cacheable
400  */
401 
402 
403 /*
404  * Local Bus Definitions
405  */
406 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
407 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
408 #define CONFIG_SYS_FLASH_BASE		0xec000000
409 #elif defined(CONFIG_P1020UTM)
410 #define CONFIG_SYS_MAX_FLASH_SECT	256	/* 32M */
411 #define CONFIG_SYS_FLASH_BASE		0xee000000
412 #else
413 #define CONFIG_SYS_MAX_FLASH_SECT	128	/* 16M */
414 #define CONFIG_SYS_FLASH_BASE		0xef000000
415 #endif
416 
417 
418 #ifdef CONFIG_PHYS_64BIT
419 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
420 #else
421 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
422 #endif
423 
424 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
425 	| BR_PS_16 | BR_V)
426 
427 #define CONFIG_FLASH_OR_PRELIM	0xfc000ff7
428 
429 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
430 #define CONFIG_SYS_FLASH_QUIET_TEST
431 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
432 
433 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
434 
435 #undef CONFIG_SYS_FLASH_CHECKSUM
436 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
437 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
438 
439 #define CONFIG_FLASH_CFI_DRIVER
440 #define CONFIG_SYS_FLASH_CFI
441 #define CONFIG_SYS_FLASH_EMPTY_INFO
442 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
443 
444 /* Nand Flash */
445 #ifdef CONFIG_NAND_FSL_ELBC
446 #define CONFIG_SYS_NAND_BASE		0xff800000
447 #ifdef CONFIG_PHYS_64BIT
448 #define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
449 #else
450 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
451 #endif
452 
453 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
454 #define CONFIG_SYS_MAX_NAND_DEVICE	1
455 #define CONFIG_MTD_NAND_VERIFY_WRITE
456 #define CONFIG_CMD_NAND
457 #if defined(CONFIG_P1020RDB_PD)
458 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
459 #else
460 #define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
461 #endif
462 
463 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
464 	| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
465 	| BR_PS_8	/* Port Size = 8 bit */ \
466 	| BR_MS_FCM	/* MSEL = FCM */ \
467 	| BR_V)	/* valid */
468 #if defined(CONFIG_P1020RDB_PD)
469 #define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB \
470 	| OR_FCM_PGS	/* Large Page*/ \
471 	| OR_FCM_CSCT \
472 	| OR_FCM_CST \
473 	| OR_FCM_CHT \
474 	| OR_FCM_SCY_1 \
475 	| OR_FCM_TRLX \
476 	| OR_FCM_EHTR)
477 #else
478 #define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB	/* small page */ \
479 	| OR_FCM_CSCT \
480 	| OR_FCM_CST \
481 	| OR_FCM_CHT \
482 	| OR_FCM_SCY_1 \
483 	| OR_FCM_TRLX \
484 	| OR_FCM_EHTR)
485 #endif
486 #endif /* CONFIG_NAND_FSL_ELBC */
487 
488 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
489 
490 #define CONFIG_SYS_INIT_RAM_LOCK
491 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* stack in RAM */
492 #ifdef CONFIG_PHYS_64BIT
493 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
494 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
495 /* The assembler doesn't like typecast */
496 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
497 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
498 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
499 #else
500 /* Initial L1 address */
501 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
502 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
503 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
504 #endif
505 /* Size of used area in RAM */
506 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
507 
508 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
509 					GENERATED_GBL_DATA_SIZE)
510 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
511 
512 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)/* Reserve 256 kB for Mon */
513 #define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)/* Reserved for malloc */
514 
515 #define CONFIG_SYS_CPLD_BASE	0xffa00000
516 #ifdef CONFIG_PHYS_64BIT
517 #define CONFIG_SYS_CPLD_BASE_PHYS	0xfffa00000ull
518 #else
519 #define CONFIG_SYS_CPLD_BASE_PHYS	CONFIG_SYS_CPLD_BASE
520 #endif
521 /* CPLD config size: 1Mb */
522 #define CONFIG_CPLD_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
523 					BR_PS_8 | BR_V)
524 #define CONFIG_CPLD_OR_PRELIM	(0xfff009f7)
525 
526 #define CONFIG_SYS_PMC_BASE	0xff980000
527 #define CONFIG_SYS_PMC_BASE_PHYS	CONFIG_SYS_PMC_BASE
528 #define CONFIG_PMC_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
529 					BR_PS_8 | BR_V)
530 #define CONFIG_PMC_OR_PRELIM	(OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
531 				 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
532 				 OR_GPCM_EAD)
533 
534 #ifdef CONFIG_NAND
535 #define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
536 #define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
537 #define CONFIG_SYS_BR1_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
538 #define CONFIG_SYS_OR1_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
539 #else
540 #define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
541 #define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
542 #ifdef CONFIG_NAND_FSL_ELBC
543 #define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
544 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
545 #endif
546 #endif
547 #define CONFIG_SYS_BR3_PRELIM	CONFIG_CPLD_BR_PRELIM	/* CPLD Base Address */
548 #define CONFIG_SYS_OR3_PRELIM	CONFIG_CPLD_OR_PRELIM	/* CPLD Options */
549 
550 
551 /* Vsc7385 switch */
552 #ifdef CONFIG_VSC7385_ENET
553 #define CONFIG_SYS_VSC7385_BASE		0xffb00000
554 
555 #ifdef CONFIG_PHYS_64BIT
556 #define CONFIG_SYS_VSC7385_BASE_PHYS	0xfffb00000ull
557 #else
558 #define CONFIG_SYS_VSC7385_BASE_PHYS	CONFIG_SYS_VSC7385_BASE
559 #endif
560 
561 #define CONFIG_SYS_VSC7385_BR_PRELIM	\
562 	(BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
563 #define CONFIG_SYS_VSC7385_OR_PRELIM	(OR_AM_128KB | OR_GPCM_CSNT | \
564 			OR_GPCM_XACS |  OR_GPCM_SCY_15 | OR_GPCM_SETA | \
565 			OR_GPCM_TRLX |  OR_GPCM_EHTR | OR_GPCM_EAD)
566 
567 #define CONFIG_SYS_BR2_PRELIM	CONFIG_SYS_VSC7385_BR_PRELIM
568 #define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_VSC7385_OR_PRELIM
569 
570 /* The size of the VSC7385 firmware image */
571 #define CONFIG_VSC7385_IMAGE_SIZE	8192
572 #endif
573 
574 /*
575  * Config the L2 Cache as L2 SRAM
576 */
577 #if defined(CONFIG_SPL_BUILD)
578 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
579 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
580 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
581 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
582 #define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
583 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
584 #define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
585 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
586 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(96 << 10)
587 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
588 #elif defined(CONFIG_NAND)
589 #ifdef CONFIG_TPL_BUILD
590 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
591 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
592 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
593 #define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
594 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
595 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
596 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
597 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
598 #else
599 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
600 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
601 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
602 #define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x2000)
603 #define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
604 #endif /* CONFIG_TPL_BUILD */
605 #endif
606 #endif
607 
608 /* Serial Port - controlled on board with jumper J8
609  * open - index 2
610  * shorted - index 1
611  */
612 #define CONFIG_CONS_INDEX		1
613 #undef CONFIG_SERIAL_SOFTWARE_FIFO
614 #define CONFIG_SYS_NS16550
615 #define CONFIG_SYS_NS16550_SERIAL
616 #define CONFIG_SYS_NS16550_REG_SIZE	1
617 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
618 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
619 #define CONFIG_NS16550_MIN_FUNCTIONS
620 #endif
621 
622 #define CONFIG_SYS_BAUDRATE_TABLE	\
623 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
624 
625 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
626 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
627 
628 /* Use the HUSH parser */
629 #define CONFIG_SYS_HUSH_PARSER
630 
631 /*
632  * Pass open firmware flat tree
633  */
634 #define CONFIG_OF_LIBFDT
635 #define CONFIG_OF_BOARD_SETUP
636 #define CONFIG_OF_STDOUT_VIA_ALIAS
637 
638 /* new uImage format support */
639 #define CONFIG_FIT
640 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
641 
642 /* I2C */
643 #define CONFIG_SYS_I2C
644 #define CONFIG_SYS_I2C_FSL
645 #define CONFIG_SYS_FSL_I2C_SPEED	400000
646 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
647 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
648 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
649 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
650 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
651 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
652 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
653 #define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash bank */
654 
655 /*
656  * I2C2 EEPROM
657  */
658 #undef CONFIG_ID_EEPROM
659 
660 #define CONFIG_RTC_PT7C4338
661 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
662 #define CONFIG_SYS_I2C_PCA9557_ADDR	0x18
663 
664 /* enable read and write access to EEPROM */
665 #define CONFIG_CMD_EEPROM
666 #define CONFIG_SYS_I2C_MULTI_EEPROMS
667 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
668 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
669 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
670 
671 /*
672  * eSPI - Enhanced SPI
673  */
674 #define CONFIG_HARD_SPI
675 #define CONFIG_FSL_ESPI
676 
677 #if defined(CONFIG_SPI_FLASH)
678 #define CONFIG_SPI_FLASH_SPANSION
679 #define CONFIG_CMD_SF
680 #define CONFIG_SF_DEFAULT_SPEED	10000000
681 #define CONFIG_SF_DEFAULT_MODE	0
682 #endif
683 
684 #if defined(CONFIG_PCI)
685 /*
686  * General PCI
687  * Memory space is mapped 1-1, but I/O space must start from 0.
688  */
689 
690 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
691 #define CONFIG_SYS_PCIE2_NAME		"PCIe SLOT"
692 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
693 #ifdef CONFIG_PHYS_64BIT
694 #define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
695 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
696 #else
697 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
698 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
699 #endif
700 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
701 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
702 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
703 #ifdef CONFIG_PHYS_64BIT
704 #define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
705 #else
706 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
707 #endif
708 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
709 
710 /* controller 1, Slot 2, tgtid 1, Base address a000 */
711 #define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
712 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
713 #ifdef CONFIG_PHYS_64BIT
714 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
715 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
716 #else
717 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
718 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
719 #endif
720 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
721 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
722 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
723 #ifdef CONFIG_PHYS_64BIT
724 #define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
725 #else
726 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
727 #endif
728 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
729 
730 #define CONFIG_PCI_PNP	/* do pci plug-and-play */
731 #define CONFIG_E1000	/* Defind e1000 pci Ethernet card*/
732 #define CONFIG_CMD_PCI
733 #define CONFIG_CMD_NET
734 
735 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
736 #define CONFIG_DOS_PARTITION
737 #endif /* CONFIG_PCI */
738 
739 #if defined(CONFIG_TSEC_ENET)
740 #define CONFIG_MII		/* MII PHY management */
741 #define CONFIG_TSEC1
742 #define CONFIG_TSEC1_NAME	"eTSEC1"
743 #define CONFIG_TSEC2
744 #define CONFIG_TSEC2_NAME	"eTSEC2"
745 #define CONFIG_TSEC3
746 #define CONFIG_TSEC3_NAME	"eTSEC3"
747 
748 #define TSEC1_PHY_ADDR	2
749 #define TSEC2_PHY_ADDR	0
750 #define TSEC3_PHY_ADDR	1
751 
752 #define TSEC1_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
753 #define TSEC2_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
754 #define TSEC3_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
755 
756 #define TSEC1_PHYIDX	0
757 #define TSEC2_PHYIDX	0
758 #define TSEC3_PHYIDX	0
759 
760 #define CONFIG_ETHPRIME	"eTSEC1"
761 
762 #define CONFIG_PHY_GIGE	1	/* Include GbE speed/duplex detection */
763 
764 #define CONFIG_HAS_ETH0
765 #define CONFIG_HAS_ETH1
766 #define CONFIG_HAS_ETH2
767 #endif /* CONFIG_TSEC_ENET */
768 
769 #ifdef CONFIG_QE
770 /* QE microcode/firmware address */
771 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
772 #define CONFIG_SYS_QE_FMAN_FW_ADDR	0xefec0000
773 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
774 #endif /* CONFIG_QE */
775 
776 #ifdef CONFIG_P1025RDB
777 /*
778  * QE UEC ethernet configuration
779  */
780 #define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
781 
782 #undef CONFIG_UEC_ETH
783 #define CONFIG_PHY_MODE_NEED_CHANGE
784 
785 #define CONFIG_UEC_ETH1	/* ETH1 */
786 #define CONFIG_HAS_ETH0
787 
788 #ifdef CONFIG_UEC_ETH1
789 #define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
790 #define CONFIG_SYS_UEC1_RX_CLK	QE_CLK12 /* CLK12 for MII */
791 #define CONFIG_SYS_UEC1_TX_CLK	QE_CLK9 /* CLK9 for MII */
792 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
793 #define CONFIG_SYS_UEC1_PHY_ADDR	0x0	/* 0x0 for MII */
794 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
795 #define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
796 #endif /* CONFIG_UEC_ETH1 */
797 
798 #define CONFIG_UEC_ETH5	/* ETH5 */
799 #define CONFIG_HAS_ETH1
800 
801 #ifdef CONFIG_UEC_ETH5
802 #define CONFIG_SYS_UEC5_UCC_NUM	4	/* UCC5 */
803 #define CONFIG_SYS_UEC5_RX_CLK	QE_CLK_NONE
804 #define CONFIG_SYS_UEC5_TX_CLK	QE_CLK13 /* CLK 13 for RMII */
805 #define CONFIG_SYS_UEC5_ETH_TYPE	FAST_ETH
806 #define CONFIG_SYS_UEC5_PHY_ADDR	0x3	/* 0x3 for RMII */
807 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
808 #define CONFIG_SYS_UEC5_INTERFACE_SPEED	100
809 #endif /* CONFIG_UEC_ETH5 */
810 #endif /* CONFIG_P1025RDB */
811 
812 /*
813  * Environment
814  */
815 #ifdef CONFIG_SPIFLASH
816 #define CONFIG_ENV_IS_IN_SPI_FLASH
817 #define CONFIG_ENV_SPI_BUS	0
818 #define CONFIG_ENV_SPI_CS	0
819 #define CONFIG_ENV_SPI_MAX_HZ	10000000
820 #define CONFIG_ENV_SPI_MODE	0
821 #define CONFIG_ENV_SIZE		0x2000	/* 8KB */
822 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
823 #define CONFIG_ENV_SECT_SIZE	0x10000
824 #elif defined(CONFIG_SDCARD)
825 #define CONFIG_ENV_IS_IN_MMC
826 #define CONFIG_FSL_FIXED_MMC_LOCATION
827 #define CONFIG_ENV_SIZE		0x2000
828 #define CONFIG_SYS_MMC_ENV_DEV	0
829 #elif defined(CONFIG_NAND)
830 #ifdef CONFIG_TPL_BUILD
831 #define CONFIG_ENV_SIZE		0x2000
832 #define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
833 #else
834 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
835 #endif
836 #define CONFIG_ENV_IS_IN_NAND
837 #define CONFIG_ENV_OFFSET	(1024 * 1024)
838 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
839 #elif defined(CONFIG_SYS_RAMBOOT)
840 #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
841 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
842 #define CONFIG_ENV_SIZE		0x2000
843 #else
844 #define CONFIG_ENV_IS_IN_FLASH
845 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
846 #define CONFIG_ENV_ADDR	0xfff80000
847 #else
848 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
849 #endif
850 #define CONFIG_ENV_SIZE		0x2000
851 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
852 #endif
853 
854 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
855 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
856 
857 /*
858  * Command line configuration.
859  */
860 #include <config_cmd_default.h>
861 
862 #define CONFIG_CMD_IRQ
863 #define CONFIG_CMD_PING
864 #define CONFIG_CMD_I2C
865 #define CONFIG_CMD_MII
866 #define CONFIG_CMD_DATE
867 #define CONFIG_CMD_ELF
868 #define CONFIG_CMD_SETEXPR
869 #define CONFIG_CMD_REGINFO
870 
871 /*
872  * USB
873  */
874 #define CONFIG_HAS_FSL_DR_USB
875 
876 #if defined(CONFIG_HAS_FSL_DR_USB)
877 #define CONFIG_USB_EHCI
878 
879 #ifdef CONFIG_USB_EHCI
880 #define CONFIG_CMD_USB
881 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
882 #define CONFIG_USB_EHCI_FSL
883 #define CONFIG_USB_STORAGE
884 #endif
885 #endif
886 
887 #define CONFIG_MMC
888 
889 #ifdef CONFIG_MMC
890 #define CONFIG_FSL_ESDHC
891 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
892 #define CONFIG_CMD_MMC
893 #define CONFIG_GENERIC_MMC
894 #endif
895 
896 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
897 		 || defined(CONFIG_FSL_SATA)
898 #define CONFIG_CMD_EXT2
899 #define CONFIG_CMD_FAT
900 #define CONFIG_DOS_PARTITION
901 #endif
902 
903 #undef CONFIG_WATCHDOG	/* watchdog disabled */
904 
905 /*
906  * Miscellaneous configurable options
907  */
908 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
909 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
910 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
911 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
912 #if defined(CONFIG_CMD_KGDB)
913 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
914 #else
915 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
916 #endif
917 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
918 	/* Print Buffer Size */
919 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
920 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
921 #define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms tick */
922 
923 /*
924  * For booting Linux, the board info and command line data
925  * have to be in the first 64 MB of memory, since this is
926  * the maximum mapped by the Linux kernel during initialization.
927  */
928 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
929 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
930 
931 #if defined(CONFIG_CMD_KGDB)
932 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
933 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
934 #endif
935 
936 /*
937  * Environment Configuration
938  */
939 #define CONFIG_HOSTNAME		unknown
940 #define CONFIG_ROOTPATH		"/opt/nfsroot"
941 #define CONFIG_BOOTFILE		"uImage"
942 #define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
943 
944 /* default location for tftp and bootm */
945 #define CONFIG_LOADADDR	1000000
946 
947 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
948 #define CONFIG_BOOTARGS	/* the boot command will set bootargs */
949 
950 #define CONFIG_BAUDRATE	115200
951 
952 #ifdef __SW_BOOT_NOR
953 #define __NOR_RST_CMD	\
954 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
955 i2c mw 18 3 __SW_BOOT_MASK 1; reset
956 #endif
957 #ifdef __SW_BOOT_SPI
958 #define __SPI_RST_CMD	\
959 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
960 i2c mw 18 3 __SW_BOOT_MASK 1; reset
961 #endif
962 #ifdef __SW_BOOT_SD
963 #define __SD_RST_CMD	\
964 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
965 i2c mw 18 3 __SW_BOOT_MASK 1; reset
966 #endif
967 #ifdef __SW_BOOT_NAND
968 #define __NAND_RST_CMD	\
969 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
970 i2c mw 18 3 __SW_BOOT_MASK 1; reset
971 #endif
972 #ifdef __SW_BOOT_PCIE
973 #define __PCIE_RST_CMD	\
974 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
975 i2c mw 18 3 __SW_BOOT_MASK 1; reset
976 #endif
977 
978 #define	CONFIG_EXTRA_ENV_SETTINGS	\
979 "netdev=eth0\0"	\
980 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
981 "loadaddr=1000000\0"	\
982 "bootfile=uImage\0"	\
983 "tftpflash=tftpboot $loadaddr $uboot; "	\
984 	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
985 	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
986 	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
987 	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
988 	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
989 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
990 "consoledev=ttyS0\0"	\
991 "ramdiskaddr=2000000\0"	\
992 "ramdiskfile=rootfs.ext2.gz.uboot\0"	\
993 "fdtaddr=c00000\0"	\
994 "bdev=sda1\0" \
995 "jffs2nor=mtdblock3\0"	\
996 "norbootaddr=ef080000\0"	\
997 "norfdtaddr=ef040000\0"	\
998 "jffs2nand=mtdblock9\0"	\
999 "nandbootaddr=100000\0"	\
1000 "nandfdtaddr=80000\0"		\
1001 "ramdisk_size=120000\0"	\
1002 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
1003 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
1004 __stringify(__NOR_RST_CMD)"\0" \
1005 __stringify(__SPI_RST_CMD)"\0" \
1006 __stringify(__SD_RST_CMD)"\0" \
1007 __stringify(__NAND_RST_CMD)"\0" \
1008 __stringify(__PCIE_RST_CMD)"\0"
1009 
1010 #define CONFIG_NFSBOOTCOMMAND	\
1011 "setenv bootargs root=/dev/nfs rw "	\
1012 "nfsroot=$serverip:$rootpath "	\
1013 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
1014 "console=$consoledev,$baudrate $othbootargs;" \
1015 "tftp $loadaddr $bootfile;"	\
1016 "tftp $fdtaddr $fdtfile;"	\
1017 "bootm $loadaddr - $fdtaddr"
1018 
1019 #define CONFIG_HDBOOT	\
1020 "setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
1021 "console=$consoledev,$baudrate $othbootargs;" \
1022 "usb start;"	\
1023 "ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
1024 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
1025 "bootm $loadaddr - $fdtaddr"
1026 
1027 #define CONFIG_USB_FAT_BOOT	\
1028 "setenv bootargs root=/dev/ram rw "	\
1029 "console=$consoledev,$baudrate $othbootargs " \
1030 "ramdisk_size=$ramdisk_size;"	\
1031 "usb start;"	\
1032 "fatload usb 0:2 $loadaddr $bootfile;"	\
1033 "fatload usb 0:2 $fdtaddr $fdtfile;"	\
1034 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
1035 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1036 
1037 #define CONFIG_USB_EXT2_BOOT	\
1038 "setenv bootargs root=/dev/ram rw "	\
1039 "console=$consoledev,$baudrate $othbootargs " \
1040 "ramdisk_size=$ramdisk_size;"	\
1041 "usb start;"	\
1042 "ext2load usb 0:4 $loadaddr $bootfile;"	\
1043 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
1044 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
1045 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1046 
1047 #define CONFIG_NORBOOT	\
1048 "setenv bootargs root=/dev/$jffs2nor rw "	\
1049 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
1050 "bootm $norbootaddr - $norfdtaddr"
1051 
1052 #define CONFIG_RAMBOOTCOMMAND	\
1053 "setenv bootargs root=/dev/ram rw "	\
1054 "console=$consoledev,$baudrate $othbootargs " \
1055 "ramdisk_size=$ramdisk_size;"	\
1056 "tftp $ramdiskaddr $ramdiskfile;"	\
1057 "tftp $loadaddr $bootfile;"	\
1058 "tftp $fdtaddr $fdtfile;"	\
1059 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1060 
1061 #define CONFIG_BOOTCOMMAND	CONFIG_HDBOOT
1062 
1063 #endif /* __CONFIG_H */
1064