1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TARGET_P1020MBG) 14 #define CONFIG_BOARDNAME "P1020MBG-PC" 15 #define CONFIG_VSC7385_ENET 16 #define CONFIG_SLIC 17 #define __SW_BOOT_MASK 0x03 18 #define __SW_BOOT_NOR 0xe4 19 #define __SW_BOOT_SD 0x54 20 #define CONFIG_SYS_L2_SIZE (256 << 10) 21 #endif 22 23 #if defined(CONFIG_TARGET_P1020UTM) 24 #define CONFIG_BOARDNAME "P1020UTM-PC" 25 #define __SW_BOOT_MASK 0x03 26 #define __SW_BOOT_NOR 0xe0 27 #define __SW_BOOT_SD 0x50 28 #define CONFIG_SYS_L2_SIZE (256 << 10) 29 #endif 30 31 #if defined(CONFIG_TARGET_P1020RDB_PC) 32 #define CONFIG_BOARDNAME "P1020RDB-PC" 33 #define CONFIG_NAND_FSL_ELBC 34 #define CONFIG_VSC7385_ENET 35 #define CONFIG_SLIC 36 #define __SW_BOOT_MASK 0x03 37 #define __SW_BOOT_NOR 0x5c 38 #define __SW_BOOT_SPI 0x1c 39 #define __SW_BOOT_SD 0x9c 40 #define __SW_BOOT_NAND 0xec 41 #define __SW_BOOT_PCIE 0x6c 42 #define CONFIG_SYS_L2_SIZE (256 << 10) 43 #endif 44 45 /* 46 * P1020RDB-PD board has user selectable switches for evaluating different 47 * frequency and boot options for the P1020 device. The table that 48 * follow describe the available options. The front six binary number was in 49 * accordance with SW3[1:6]. 50 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 51 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 52 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 53 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 54 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 55 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 56 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 57 */ 58 #if defined(CONFIG_TARGET_P1020RDB_PD) 59 #define CONFIG_BOARDNAME "P1020RDB-PD" 60 #define CONFIG_NAND_FSL_ELBC 61 #define CONFIG_VSC7385_ENET 62 #define CONFIG_SLIC 63 #define __SW_BOOT_MASK 0x03 64 #define __SW_BOOT_NOR 0x64 65 #define __SW_BOOT_SPI 0x34 66 #define __SW_BOOT_SD 0x24 67 #define __SW_BOOT_NAND 0x44 68 #define __SW_BOOT_PCIE 0x74 69 #define CONFIG_SYS_L2_SIZE (256 << 10) 70 /* 71 * Dynamic MTD Partition support with mtdparts 72 */ 73 #define CONFIG_MTD_DEVICE 74 #define CONFIG_MTD_PARTITIONS 75 #define CONFIG_FLASH_CFI_MTD 76 #endif 77 78 #if defined(CONFIG_TARGET_P1021RDB) 79 #define CONFIG_BOARDNAME "P1021RDB-PC" 80 #define CONFIG_NAND_FSL_ELBC 81 #define CONFIG_QE 82 #define CONFIG_VSC7385_ENET 83 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 84 addresses in the LBC */ 85 #define __SW_BOOT_MASK 0x03 86 #define __SW_BOOT_NOR 0x5c 87 #define __SW_BOOT_SPI 0x1c 88 #define __SW_BOOT_SD 0x9c 89 #define __SW_BOOT_NAND 0xec 90 #define __SW_BOOT_PCIE 0x6c 91 #define CONFIG_SYS_L2_SIZE (256 << 10) 92 /* 93 * Dynamic MTD Partition support with mtdparts 94 */ 95 #define CONFIG_MTD_DEVICE 96 #define CONFIG_MTD_PARTITIONS 97 #define CONFIG_FLASH_CFI_MTD 98 #endif 99 100 #if defined(CONFIG_TARGET_P1024RDB) 101 #define CONFIG_BOARDNAME "P1024RDB" 102 #define CONFIG_NAND_FSL_ELBC 103 #define CONFIG_SLIC 104 #define __SW_BOOT_MASK 0xf3 105 #define __SW_BOOT_NOR 0x00 106 #define __SW_BOOT_SPI 0x08 107 #define __SW_BOOT_SD 0x04 108 #define __SW_BOOT_NAND 0x0c 109 #define CONFIG_SYS_L2_SIZE (256 << 10) 110 #endif 111 112 #if defined(CONFIG_TARGET_P1025RDB) 113 #define CONFIG_BOARDNAME "P1025RDB" 114 #define CONFIG_NAND_FSL_ELBC 115 #define CONFIG_QE 116 #define CONFIG_SLIC 117 118 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 119 addresses in the LBC */ 120 #define __SW_BOOT_MASK 0xf3 121 #define __SW_BOOT_NOR 0x00 122 #define __SW_BOOT_SPI 0x08 123 #define __SW_BOOT_SD 0x04 124 #define __SW_BOOT_NAND 0x0c 125 #define CONFIG_SYS_L2_SIZE (256 << 10) 126 #endif 127 128 #if defined(CONFIG_TARGET_P2020RDB) 129 #define CONFIG_BOARDNAME "P2020RDB-PC" 130 #define CONFIG_NAND_FSL_ELBC 131 #define CONFIG_VSC7385_ENET 132 #define __SW_BOOT_MASK 0x03 133 #define __SW_BOOT_NOR 0xc8 134 #define __SW_BOOT_SPI 0x28 135 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 136 #define __SW_BOOT_NAND 0xe8 137 #define __SW_BOOT_PCIE 0xa8 138 #define CONFIG_SYS_L2_SIZE (512 << 10) 139 /* 140 * Dynamic MTD Partition support with mtdparts 141 */ 142 #define CONFIG_MTD_DEVICE 143 #define CONFIG_MTD_PARTITIONS 144 #define CONFIG_FLASH_CFI_MTD 145 #endif 146 147 #ifdef CONFIG_SDCARD 148 #define CONFIG_SPL_MMC_MINIMAL 149 #define CONFIG_SPL_FLUSH_IMAGE 150 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 151 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 152 #define CONFIG_SPL_PAD_TO 0x20000 153 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 154 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 155 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 156 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 157 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 158 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 159 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 160 #define CONFIG_SPL_MMC_BOOT 161 #ifdef CONFIG_SPL_BUILD 162 #define CONFIG_SPL_COMMON_INIT_DDR 163 #endif 164 #endif 165 166 #ifdef CONFIG_SPIFLASH 167 #define CONFIG_SPL_SPI_FLASH_MINIMAL 168 #define CONFIG_SPL_FLUSH_IMAGE 169 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 170 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 171 #define CONFIG_SPL_PAD_TO 0x20000 172 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 173 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 174 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 175 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 176 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 177 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 178 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 179 #define CONFIG_SPL_SPI_BOOT 180 #ifdef CONFIG_SPL_BUILD 181 #define CONFIG_SPL_COMMON_INIT_DDR 182 #endif 183 #endif 184 185 #ifdef CONFIG_NAND 186 #ifdef CONFIG_TPL_BUILD 187 #define CONFIG_SPL_NAND_BOOT 188 #define CONFIG_SPL_FLUSH_IMAGE 189 #define CONFIG_SPL_NAND_INIT 190 #define CONFIG_SPL_COMMON_INIT_DDR 191 #define CONFIG_SPL_MAX_SIZE (128 << 10) 192 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 193 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 194 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 195 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 196 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 197 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 198 #elif defined(CONFIG_SPL_BUILD) 199 #define CONFIG_SPL_INIT_MINIMAL 200 #define CONFIG_SPL_FLUSH_IMAGE 201 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 202 #define CONFIG_SPL_TEXT_BASE 0xff800000 203 #define CONFIG_SPL_MAX_SIZE 4096 204 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 205 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 206 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 207 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 208 #endif /* not CONFIG_TPL_BUILD */ 209 210 #define CONFIG_SPL_PAD_TO 0x20000 211 #define CONFIG_TPL_PAD_TO 0x20000 212 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 213 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 214 #endif 215 216 #ifndef CONFIG_RESET_VECTOR_ADDRESS 217 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 218 #endif 219 220 #ifndef CONFIG_SYS_MONITOR_BASE 221 #ifdef CONFIG_SPL_BUILD 222 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 223 #else 224 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 225 #endif 226 #endif 227 228 #define CONFIG_MP 229 230 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 231 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 232 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 233 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 234 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 235 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 236 237 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 238 #define CONFIG_ENV_OVERWRITE 239 240 #define CONFIG_SYS_SATA_MAX_DEVICE 2 241 #define CONFIG_LBA48 242 243 #if defined(CONFIG_TARGET_P2020RDB) 244 #define CONFIG_SYS_CLK_FREQ 100000000 245 #else 246 #define CONFIG_SYS_CLK_FREQ 66666666 247 #endif 248 #define CONFIG_DDR_CLK_FREQ 66666666 249 250 #define CONFIG_HWCONFIG 251 /* 252 * These can be toggled for performance analysis, otherwise use default. 253 */ 254 #define CONFIG_L2_CACHE 255 #define CONFIG_BTB 256 257 #define CONFIG_ENABLE_36BIT_PHYS 258 259 #ifdef CONFIG_PHYS_64BIT 260 #define CONFIG_ADDR_MAP 1 261 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 262 #endif 263 264 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 265 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 266 267 #define CONFIG_SYS_CCSRBAR 0xffe00000 268 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 269 270 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 271 SPL code*/ 272 #ifdef CONFIG_SPL_BUILD 273 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 274 #endif 275 276 /* DDR Setup */ 277 #define CONFIG_SYS_DDR_RAW_TIMING 278 #define CONFIG_DDR_SPD 279 #define CONFIG_SYS_SPD_BUS_NUM 1 280 #define SPD_EEPROM_ADDRESS 0x52 281 #undef CONFIG_FSL_DDR_INTERACTIVE 282 283 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 284 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 285 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 286 #else 287 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 288 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 289 #endif 290 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 291 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 292 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 293 294 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 295 296 /* Default settings for DDR3 */ 297 #ifndef CONFIG_TARGET_P2020RDB 298 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 299 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 300 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 301 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 302 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 303 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 304 305 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 306 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 307 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 308 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 309 310 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 311 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 312 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 313 #define CONFIG_SYS_DDR_RCW_1 0x00000000 314 #define CONFIG_SYS_DDR_RCW_2 0x00000000 315 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 316 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 317 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 318 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 319 320 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 321 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 322 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 323 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 324 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 325 #define CONFIG_SYS_DDR_MODE_1 0x40461520 326 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 327 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 328 #endif 329 330 #undef CONFIG_CLOCKS_IN_MHZ 331 332 /* 333 * Memory map 334 * 335 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 336 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 337 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 338 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 339 * (early boot only) 340 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 341 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 342 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 343 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 344 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 345 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 346 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 347 */ 348 349 /* 350 * Local Bus Definitions 351 */ 352 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 353 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 354 #define CONFIG_SYS_FLASH_BASE 0xec000000 355 #elif defined(CONFIG_TARGET_P1020UTM) 356 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 357 #define CONFIG_SYS_FLASH_BASE 0xee000000 358 #else 359 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 360 #define CONFIG_SYS_FLASH_BASE 0xef000000 361 #endif 362 363 #ifdef CONFIG_PHYS_64BIT 364 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 365 #else 366 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 367 #endif 368 369 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 370 | BR_PS_16 | BR_V) 371 372 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 373 374 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 375 #define CONFIG_SYS_FLASH_QUIET_TEST 376 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 377 378 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 379 380 #undef CONFIG_SYS_FLASH_CHECKSUM 381 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 382 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 383 384 #define CONFIG_FLASH_CFI_DRIVER 385 #define CONFIG_SYS_FLASH_CFI 386 #define CONFIG_SYS_FLASH_EMPTY_INFO 387 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 388 389 /* Nand Flash */ 390 #ifdef CONFIG_NAND_FSL_ELBC 391 #define CONFIG_SYS_NAND_BASE 0xff800000 392 #ifdef CONFIG_PHYS_64BIT 393 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 394 #else 395 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 396 #endif 397 398 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 399 #define CONFIG_SYS_MAX_NAND_DEVICE 1 400 #if defined(CONFIG_TARGET_P1020RDB_PD) 401 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 402 #else 403 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 404 #endif 405 406 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 407 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 408 | BR_PS_8 /* Port Size = 8 bit */ \ 409 | BR_MS_FCM /* MSEL = FCM */ \ 410 | BR_V) /* valid */ 411 #if defined(CONFIG_TARGET_P1020RDB_PD) 412 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 413 | OR_FCM_PGS /* Large Page*/ \ 414 | OR_FCM_CSCT \ 415 | OR_FCM_CST \ 416 | OR_FCM_CHT \ 417 | OR_FCM_SCY_1 \ 418 | OR_FCM_TRLX \ 419 | OR_FCM_EHTR) 420 #else 421 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 422 | OR_FCM_CSCT \ 423 | OR_FCM_CST \ 424 | OR_FCM_CHT \ 425 | OR_FCM_SCY_1 \ 426 | OR_FCM_TRLX \ 427 | OR_FCM_EHTR) 428 #endif 429 #endif /* CONFIG_NAND_FSL_ELBC */ 430 431 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 432 433 #define CONFIG_SYS_INIT_RAM_LOCK 434 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 435 #ifdef CONFIG_PHYS_64BIT 436 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 437 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 438 /* The assembler doesn't like typecast */ 439 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 440 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 441 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 442 #else 443 /* Initial L1 address */ 444 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 445 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 446 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 447 #endif 448 /* Size of used area in RAM */ 449 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 450 451 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 452 GENERATED_GBL_DATA_SIZE) 453 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 454 455 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 456 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 457 458 #define CONFIG_SYS_CPLD_BASE 0xffa00000 459 #ifdef CONFIG_PHYS_64BIT 460 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 461 #else 462 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 463 #endif 464 /* CPLD config size: 1Mb */ 465 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 466 BR_PS_8 | BR_V) 467 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 468 469 #define CONFIG_SYS_PMC_BASE 0xff980000 470 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 471 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 472 BR_PS_8 | BR_V) 473 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 474 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 475 OR_GPCM_EAD) 476 477 #ifdef CONFIG_NAND 478 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 479 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 480 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 481 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 482 #else 483 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 484 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 485 #ifdef CONFIG_NAND_FSL_ELBC 486 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 487 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 488 #endif 489 #endif 490 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 491 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 492 493 /* Vsc7385 switch */ 494 #ifdef CONFIG_VSC7385_ENET 495 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 496 497 #ifdef CONFIG_PHYS_64BIT 498 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 499 #else 500 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 501 #endif 502 503 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 504 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 505 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 506 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 507 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 508 509 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 510 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 511 512 /* The size of the VSC7385 firmware image */ 513 #define CONFIG_VSC7385_IMAGE_SIZE 8192 514 #endif 515 516 /* 517 * Config the L2 Cache as L2 SRAM 518 */ 519 #if defined(CONFIG_SPL_BUILD) 520 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 521 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 522 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 523 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 524 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 525 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 526 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 527 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 528 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 529 #if defined(CONFIG_TARGET_P2020RDB) 530 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 531 #else 532 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 533 #endif 534 #elif defined(CONFIG_NAND) 535 #ifdef CONFIG_TPL_BUILD 536 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 537 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 538 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 539 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 540 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 541 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 542 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 543 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 544 #else 545 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 546 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 547 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 548 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 549 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 550 #endif /* CONFIG_TPL_BUILD */ 551 #endif 552 #endif 553 554 /* Serial Port - controlled on board with jumper J8 555 * open - index 2 556 * shorted - index 1 557 */ 558 #define CONFIG_CONS_INDEX 1 559 #undef CONFIG_SERIAL_SOFTWARE_FIFO 560 #define CONFIG_SYS_NS16550_SERIAL 561 #define CONFIG_SYS_NS16550_REG_SIZE 1 562 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 563 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 564 #define CONFIG_NS16550_MIN_FUNCTIONS 565 #endif 566 567 #define CONFIG_SYS_BAUDRATE_TABLE \ 568 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 569 570 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 571 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 572 573 /* I2C */ 574 #define CONFIG_SYS_I2C 575 #define CONFIG_SYS_I2C_FSL 576 #define CONFIG_SYS_FSL_I2C_SPEED 400000 577 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 578 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 579 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 580 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 581 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 582 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 583 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 584 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 585 586 /* 587 * I2C2 EEPROM 588 */ 589 #undef CONFIG_ID_EEPROM 590 591 #define CONFIG_RTC_PT7C4338 592 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 593 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 594 595 /* enable read and write access to EEPROM */ 596 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 597 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 598 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 599 600 /* 601 * eSPI - Enhanced SPI 602 */ 603 #define CONFIG_HARD_SPI 604 605 #if defined(CONFIG_SPI_FLASH) 606 #define CONFIG_SF_DEFAULT_SPEED 10000000 607 #define CONFIG_SF_DEFAULT_MODE 0 608 #endif 609 610 #if defined(CONFIG_PCI) 611 /* 612 * General PCI 613 * Memory space is mapped 1-1, but I/O space must start from 0. 614 */ 615 616 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 617 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 618 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 619 #ifdef CONFIG_PHYS_64BIT 620 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 621 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 622 #else 623 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 624 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 625 #endif 626 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 627 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 628 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 629 #ifdef CONFIG_PHYS_64BIT 630 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 631 #else 632 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 633 #endif 634 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 635 636 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 637 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 638 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 639 #ifdef CONFIG_PHYS_64BIT 640 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 641 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 642 #else 643 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 644 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 645 #endif 646 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 647 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 648 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 649 #ifdef CONFIG_PHYS_64BIT 650 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 651 #else 652 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 653 #endif 654 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 655 656 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 657 #endif /* CONFIG_PCI */ 658 659 #if defined(CONFIG_TSEC_ENET) 660 #define CONFIG_MII /* MII PHY management */ 661 #define CONFIG_TSEC1 662 #define CONFIG_TSEC1_NAME "eTSEC1" 663 #define CONFIG_TSEC2 664 #define CONFIG_TSEC2_NAME "eTSEC2" 665 #define CONFIG_TSEC3 666 #define CONFIG_TSEC3_NAME "eTSEC3" 667 668 #define TSEC1_PHY_ADDR 2 669 #define TSEC2_PHY_ADDR 0 670 #define TSEC3_PHY_ADDR 1 671 672 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 673 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 674 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 675 676 #define TSEC1_PHYIDX 0 677 #define TSEC2_PHYIDX 0 678 #define TSEC3_PHYIDX 0 679 680 #define CONFIG_ETHPRIME "eTSEC1" 681 682 #define CONFIG_HAS_ETH0 683 #define CONFIG_HAS_ETH1 684 #define CONFIG_HAS_ETH2 685 #endif /* CONFIG_TSEC_ENET */ 686 687 #ifdef CONFIG_QE 688 /* QE microcode/firmware address */ 689 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 690 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 691 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 692 #endif /* CONFIG_QE */ 693 694 #ifdef CONFIG_TARGET_P1025RDB 695 /* 696 * QE UEC ethernet configuration 697 */ 698 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 699 700 #undef CONFIG_UEC_ETH 701 #define CONFIG_PHY_MODE_NEED_CHANGE 702 703 #define CONFIG_UEC_ETH1 /* ETH1 */ 704 #define CONFIG_HAS_ETH0 705 706 #ifdef CONFIG_UEC_ETH1 707 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 708 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 709 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 710 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 711 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 712 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 713 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 714 #endif /* CONFIG_UEC_ETH1 */ 715 716 #define CONFIG_UEC_ETH5 /* ETH5 */ 717 #define CONFIG_HAS_ETH1 718 719 #ifdef CONFIG_UEC_ETH5 720 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 721 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 722 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 723 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 724 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 725 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 726 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 727 #endif /* CONFIG_UEC_ETH5 */ 728 #endif /* CONFIG_TARGET_P1025RDB */ 729 730 /* 731 * Environment 732 */ 733 #ifdef CONFIG_SPIFLASH 734 #define CONFIG_ENV_SPI_BUS 0 735 #define CONFIG_ENV_SPI_CS 0 736 #define CONFIG_ENV_SPI_MAX_HZ 10000000 737 #define CONFIG_ENV_SPI_MODE 0 738 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 739 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 740 #define CONFIG_ENV_SECT_SIZE 0x10000 741 #elif defined(CONFIG_SDCARD) 742 #define CONFIG_FSL_FIXED_MMC_LOCATION 743 #define CONFIG_ENV_SIZE 0x2000 744 #define CONFIG_SYS_MMC_ENV_DEV 0 745 #elif defined(CONFIG_NAND) 746 #ifdef CONFIG_TPL_BUILD 747 #define CONFIG_ENV_SIZE 0x2000 748 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 749 #else 750 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 751 #endif 752 #define CONFIG_ENV_OFFSET (1024 * 1024) 753 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 754 #elif defined(CONFIG_SYS_RAMBOOT) 755 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 756 #define CONFIG_ENV_SIZE 0x2000 757 #else 758 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 759 #define CONFIG_ENV_SIZE 0x2000 760 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 761 #endif 762 763 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 764 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 765 766 /* 767 * USB 768 */ 769 #define CONFIG_HAS_FSL_DR_USB 770 771 #if defined(CONFIG_HAS_FSL_DR_USB) 772 #ifdef CONFIG_USB_EHCI_HCD 773 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 774 #define CONFIG_USB_EHCI_FSL 775 #define CONFIG_EHCI_DESC_BIG_ENDIAN 776 #endif 777 #endif 778 779 #if defined(CONFIG_TARGET_P1020RDB_PD) 780 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 781 #endif 782 783 #ifdef CONFIG_MMC 784 #define CONFIG_FSL_ESDHC 785 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 786 #endif 787 788 #undef CONFIG_WATCHDOG /* watchdog disabled */ 789 790 /* 791 * Miscellaneous configurable options 792 */ 793 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 794 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 795 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 796 797 /* 798 * For booting Linux, the board info and command line data 799 * have to be in the first 64 MB of memory, since this is 800 * the maximum mapped by the Linux kernel during initialization. 801 */ 802 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 803 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 804 805 #if defined(CONFIG_CMD_KGDB) 806 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 807 #endif 808 809 /* 810 * Environment Configuration 811 */ 812 #define CONFIG_HOSTNAME unknown 813 #define CONFIG_ROOTPATH "/opt/nfsroot" 814 #define CONFIG_BOOTFILE "uImage" 815 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 816 817 /* default location for tftp and bootm */ 818 #define CONFIG_LOADADDR 1000000 819 820 #ifdef __SW_BOOT_NOR 821 #define __NOR_RST_CMD \ 822 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 823 i2c mw 18 3 __SW_BOOT_MASK 1; reset 824 #endif 825 #ifdef __SW_BOOT_SPI 826 #define __SPI_RST_CMD \ 827 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 828 i2c mw 18 3 __SW_BOOT_MASK 1; reset 829 #endif 830 #ifdef __SW_BOOT_SD 831 #define __SD_RST_CMD \ 832 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 833 i2c mw 18 3 __SW_BOOT_MASK 1; reset 834 #endif 835 #ifdef __SW_BOOT_NAND 836 #define __NAND_RST_CMD \ 837 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 838 i2c mw 18 3 __SW_BOOT_MASK 1; reset 839 #endif 840 #ifdef __SW_BOOT_PCIE 841 #define __PCIE_RST_CMD \ 842 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 843 i2c mw 18 3 __SW_BOOT_MASK 1; reset 844 #endif 845 846 #define CONFIG_EXTRA_ENV_SETTINGS \ 847 "netdev=eth0\0" \ 848 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 849 "loadaddr=1000000\0" \ 850 "bootfile=uImage\0" \ 851 "tftpflash=tftpboot $loadaddr $uboot; " \ 852 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 853 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 854 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 855 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 856 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 857 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 858 "consoledev=ttyS0\0" \ 859 "ramdiskaddr=2000000\0" \ 860 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 861 "fdtaddr=1e00000\0" \ 862 "bdev=sda1\0" \ 863 "jffs2nor=mtdblock3\0" \ 864 "norbootaddr=ef080000\0" \ 865 "norfdtaddr=ef040000\0" \ 866 "jffs2nand=mtdblock9\0" \ 867 "nandbootaddr=100000\0" \ 868 "nandfdtaddr=80000\0" \ 869 "ramdisk_size=120000\0" \ 870 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 871 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 872 __stringify(__NOR_RST_CMD)"\0" \ 873 __stringify(__SPI_RST_CMD)"\0" \ 874 __stringify(__SD_RST_CMD)"\0" \ 875 __stringify(__NAND_RST_CMD)"\0" \ 876 __stringify(__PCIE_RST_CMD)"\0" 877 878 #define CONFIG_NFSBOOTCOMMAND \ 879 "setenv bootargs root=/dev/nfs rw " \ 880 "nfsroot=$serverip:$rootpath " \ 881 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 882 "console=$consoledev,$baudrate $othbootargs;" \ 883 "tftp $loadaddr $bootfile;" \ 884 "tftp $fdtaddr $fdtfile;" \ 885 "bootm $loadaddr - $fdtaddr" 886 887 #define CONFIG_HDBOOT \ 888 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 889 "console=$consoledev,$baudrate $othbootargs;" \ 890 "usb start;" \ 891 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 892 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 893 "bootm $loadaddr - $fdtaddr" 894 895 #define CONFIG_USB_FAT_BOOT \ 896 "setenv bootargs root=/dev/ram rw " \ 897 "console=$consoledev,$baudrate $othbootargs " \ 898 "ramdisk_size=$ramdisk_size;" \ 899 "usb start;" \ 900 "fatload usb 0:2 $loadaddr $bootfile;" \ 901 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 902 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 903 "bootm $loadaddr $ramdiskaddr $fdtaddr" 904 905 #define CONFIG_USB_EXT2_BOOT \ 906 "setenv bootargs root=/dev/ram rw " \ 907 "console=$consoledev,$baudrate $othbootargs " \ 908 "ramdisk_size=$ramdisk_size;" \ 909 "usb start;" \ 910 "ext2load usb 0:4 $loadaddr $bootfile;" \ 911 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 912 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 913 "bootm $loadaddr $ramdiskaddr $fdtaddr" 914 915 #define CONFIG_NORBOOT \ 916 "setenv bootargs root=/dev/$jffs2nor rw " \ 917 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 918 "bootm $norbootaddr - $norfdtaddr" 919 920 #define CONFIG_RAMBOOTCOMMAND \ 921 "setenv bootargs root=/dev/ram rw " \ 922 "console=$consoledev,$baudrate $othbootargs " \ 923 "ramdisk_size=$ramdisk_size;" \ 924 "tftp $ramdiskaddr $ramdiskfile;" \ 925 "tftp $loadaddr $bootfile;" \ 926 "tftp $fdtaddr $fdtfile;" \ 927 "bootm $loadaddr $ramdiskaddr $fdtaddr" 928 929 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 930 931 #endif /* __CONFIG_H */ 932