1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 #if defined(CONFIG_P1020MBG) 16 #define CONFIG_BOARDNAME "P1020MBG-PC" 17 #define CONFIG_P1020 18 #define CONFIG_VSC7385_ENET 19 #define CONFIG_SLIC 20 #define __SW_BOOT_MASK 0x03 21 #define __SW_BOOT_NOR 0xe4 22 #define __SW_BOOT_SD 0x54 23 #define CONFIG_SYS_L2_SIZE (256 << 10) 24 #endif 25 26 #if defined(CONFIG_P1020UTM) 27 #define CONFIG_BOARDNAME "P1020UTM-PC" 28 #define CONFIG_P1020 29 #define __SW_BOOT_MASK 0x03 30 #define __SW_BOOT_NOR 0xe0 31 #define __SW_BOOT_SD 0x50 32 #define CONFIG_SYS_L2_SIZE (256 << 10) 33 #endif 34 35 #if defined(CONFIG_P1020RDB_PC) 36 #define CONFIG_BOARDNAME "P1020RDB-PC" 37 #define CONFIG_NAND_FSL_ELBC 38 #define CONFIG_P1020 39 #define CONFIG_VSC7385_ENET 40 #define CONFIG_SLIC 41 #define __SW_BOOT_MASK 0x03 42 #define __SW_BOOT_NOR 0x5c 43 #define __SW_BOOT_SPI 0x1c 44 #define __SW_BOOT_SD 0x9c 45 #define __SW_BOOT_NAND 0xec 46 #define __SW_BOOT_PCIE 0x6c 47 #define CONFIG_SYS_L2_SIZE (256 << 10) 48 #endif 49 50 /* 51 * P1020RDB-PD board has user selectable switches for evaluating different 52 * frequency and boot options for the P1020 device. The table that 53 * follow describe the available options. The front six binary number was in 54 * accordance with SW3[1:6]. 55 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 56 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 57 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 58 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 59 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 60 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 61 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 62 */ 63 #if defined(CONFIG_P1020RDB_PD) 64 #define CONFIG_BOARDNAME "P1020RDB-PD" 65 #define CONFIG_NAND_FSL_ELBC 66 #define CONFIG_P1020 67 #define CONFIG_VSC7385_ENET 68 #define CONFIG_SLIC 69 #define __SW_BOOT_MASK 0x03 70 #define __SW_BOOT_NOR 0x64 71 #define __SW_BOOT_SPI 0x34 72 #define __SW_BOOT_SD 0x24 73 #define __SW_BOOT_NAND 0x44 74 #define __SW_BOOT_PCIE 0x74 75 #define CONFIG_SYS_L2_SIZE (256 << 10) 76 /* 77 * Dynamic MTD Partition support with mtdparts 78 */ 79 #define CONFIG_MTD_DEVICE 80 #define CONFIG_MTD_PARTITIONS 81 #define CONFIG_CMD_MTDPARTS 82 #define CONFIG_FLASH_CFI_MTD 83 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 84 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ 85 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" 86 #endif 87 88 #if defined(CONFIG_P1021RDB) 89 #define CONFIG_BOARDNAME "P1021RDB-PC" 90 #define CONFIG_NAND_FSL_ELBC 91 #define CONFIG_P1021 92 #define CONFIG_QE 93 #define CONFIG_VSC7385_ENET 94 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 95 addresses in the LBC */ 96 #define __SW_BOOT_MASK 0x03 97 #define __SW_BOOT_NOR 0x5c 98 #define __SW_BOOT_SPI 0x1c 99 #define __SW_BOOT_SD 0x9c 100 #define __SW_BOOT_NAND 0xec 101 #define __SW_BOOT_PCIE 0x6c 102 #define CONFIG_SYS_L2_SIZE (256 << 10) 103 /* 104 * Dynamic MTD Partition support with mtdparts 105 */ 106 #define CONFIG_MTD_DEVICE 107 #define CONFIG_MTD_PARTITIONS 108 #define CONFIG_CMD_MTDPARTS 109 #define CONFIG_FLASH_CFI_MTD 110 #ifdef CONFIG_PHYS_64BIT 111 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 112 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 113 "256k(dtb),4608k(kernel),9728k(fs)," \ 114 "256k(qe-ucode-firmware),1280k(u-boot)" 115 #else 116 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 117 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 118 "256k(dtb),4608k(kernel),9728k(fs)," \ 119 "256k(qe-ucode-firmware),1280k(u-boot)" 120 #endif 121 #endif 122 123 #if defined(CONFIG_P1024RDB) 124 #define CONFIG_BOARDNAME "P1024RDB" 125 #define CONFIG_NAND_FSL_ELBC 126 #define CONFIG_P1024 127 #define CONFIG_SLIC 128 #define __SW_BOOT_MASK 0xf3 129 #define __SW_BOOT_NOR 0x00 130 #define __SW_BOOT_SPI 0x08 131 #define __SW_BOOT_SD 0x04 132 #define __SW_BOOT_NAND 0x0c 133 #define CONFIG_SYS_L2_SIZE (256 << 10) 134 #endif 135 136 #if defined(CONFIG_P1025RDB) 137 #define CONFIG_BOARDNAME "P1025RDB" 138 #define CONFIG_NAND_FSL_ELBC 139 #define CONFIG_P1025 140 #define CONFIG_QE 141 #define CONFIG_SLIC 142 143 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 144 addresses in the LBC */ 145 #define __SW_BOOT_MASK 0xf3 146 #define __SW_BOOT_NOR 0x00 147 #define __SW_BOOT_SPI 0x08 148 #define __SW_BOOT_SD 0x04 149 #define __SW_BOOT_NAND 0x0c 150 #define CONFIG_SYS_L2_SIZE (256 << 10) 151 #endif 152 153 #if defined(CONFIG_P2020RDB) 154 #define CONFIG_BOARDNAME "P2020RDB-PCA" 155 #define CONFIG_NAND_FSL_ELBC 156 #define CONFIG_P2020 157 #define CONFIG_VSC7385_ENET 158 #define __SW_BOOT_MASK 0x03 159 #define __SW_BOOT_NOR 0xc8 160 #define __SW_BOOT_SPI 0x28 161 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 162 #define __SW_BOOT_NAND 0xe8 163 #define __SW_BOOT_PCIE 0xa8 164 #define CONFIG_SYS_L2_SIZE (512 << 10) 165 /* 166 * Dynamic MTD Partition support with mtdparts 167 */ 168 #define CONFIG_MTD_DEVICE 169 #define CONFIG_MTD_PARTITIONS 170 #define CONFIG_CMD_MTDPARTS 171 #define CONFIG_FLASH_CFI_MTD 172 #ifdef CONFIG_PHYS_64BIT 173 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 174 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 175 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 176 #else 177 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 178 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 179 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 180 #endif 181 #endif 182 183 #ifdef CONFIG_SDCARD 184 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 185 #define CONFIG_SPL_SERIAL_SUPPORT 186 #define CONFIG_SPL_MMC_MINIMAL 187 #define CONFIG_SPL_FLUSH_IMAGE 188 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 189 #define CONFIG_FSL_LAW /* Use common FSL init code */ 190 #define CONFIG_SYS_TEXT_BASE 0x11001000 191 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 192 #define CONFIG_SPL_PAD_TO 0x20000 193 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 194 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 195 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 196 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 197 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 198 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 199 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 200 #define CONFIG_SPL_MMC_BOOT 201 #ifdef CONFIG_SPL_BUILD 202 #define CONFIG_SPL_COMMON_INIT_DDR 203 #endif 204 #endif 205 206 #ifdef CONFIG_SPIFLASH 207 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 208 #define CONFIG_SPL_SERIAL_SUPPORT 209 #define CONFIG_SPL_SPI_SUPPORT 210 #define CONFIG_SPL_SPI_FLASH_SUPPORT 211 #define CONFIG_SPL_SPI_FLASH_MINIMAL 212 #define CONFIG_SPL_FLUSH_IMAGE 213 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 214 #define CONFIG_FSL_LAW /* Use common FSL init code */ 215 #define CONFIG_SYS_TEXT_BASE 0x11001000 216 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 217 #define CONFIG_SPL_PAD_TO 0x20000 218 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 219 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 220 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 221 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 222 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 223 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 224 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 225 #define CONFIG_SPL_SPI_BOOT 226 #ifdef CONFIG_SPL_BUILD 227 #define CONFIG_SPL_COMMON_INIT_DDR 228 #endif 229 #endif 230 231 #ifdef CONFIG_NAND 232 #ifdef CONFIG_TPL_BUILD 233 #define CONFIG_SPL_NAND_BOOT 234 #define CONFIG_SPL_FLUSH_IMAGE 235 #define CONFIG_SPL_NAND_INIT 236 #define CONFIG_TPL_SERIAL_SUPPORT 237 #define CONFIG_TPL_NAND_SUPPORT 238 #define CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT 239 #define CONFIG_SPL_COMMON_INIT_DDR 240 #define CONFIG_SPL_MAX_SIZE (128 << 10) 241 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 242 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 243 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 244 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 245 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 246 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 247 #elif defined(CONFIG_SPL_BUILD) 248 #define CONFIG_SPL_INIT_MINIMAL 249 #define CONFIG_SPL_SERIAL_SUPPORT 250 #define CONFIG_SPL_NAND_SUPPORT 251 #define CONFIG_SPL_FLUSH_IMAGE 252 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 253 #define CONFIG_SPL_TEXT_BASE 0xff800000 254 #define CONFIG_SPL_MAX_SIZE 4096 255 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 256 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 257 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 258 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 259 #endif /* not CONFIG_TPL_BUILD */ 260 261 #define CONFIG_SPL_PAD_TO 0x20000 262 #define CONFIG_TPL_PAD_TO 0x20000 263 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 264 #define CONFIG_SYS_TEXT_BASE 0x11001000 265 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 266 #endif 267 268 #ifndef CONFIG_SYS_TEXT_BASE 269 #define CONFIG_SYS_TEXT_BASE 0xeff40000 270 #endif 271 272 #ifndef CONFIG_RESET_VECTOR_ADDRESS 273 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 274 #endif 275 276 #ifndef CONFIG_SYS_MONITOR_BASE 277 #ifdef CONFIG_SPL_BUILD 278 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 279 #else 280 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 281 #endif 282 #endif 283 284 /* High Level Configuration Options */ 285 #define CONFIG_BOOKE 286 #define CONFIG_E500 287 288 #define CONFIG_MP 289 290 #define CONFIG_FSL_ELBC 291 #define CONFIG_PCI 292 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 293 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 294 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 295 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 296 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 297 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 298 299 #define CONFIG_FSL_LAW 300 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 301 #define CONFIG_ENV_OVERWRITE 302 303 #define CONFIG_CMD_SATA 304 #define CONFIG_SATA_SIL 305 #define CONFIG_SYS_SATA_MAX_DEVICE 2 306 #define CONFIG_LIBATA 307 #define CONFIG_LBA48 308 309 #if defined(CONFIG_P2020RDB) 310 #define CONFIG_SYS_CLK_FREQ 100000000 311 #else 312 #define CONFIG_SYS_CLK_FREQ 66666666 313 #endif 314 #define CONFIG_DDR_CLK_FREQ 66666666 315 316 #define CONFIG_HWCONFIG 317 /* 318 * These can be toggled for performance analysis, otherwise use default. 319 */ 320 #define CONFIG_L2_CACHE 321 #define CONFIG_BTB 322 323 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 324 325 #define CONFIG_ENABLE_36BIT_PHYS 326 327 #ifdef CONFIG_PHYS_64BIT 328 #define CONFIG_ADDR_MAP 1 329 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 330 #endif 331 332 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 333 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 334 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 335 336 #define CONFIG_SYS_CCSRBAR 0xffe00000 337 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 338 339 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 340 SPL code*/ 341 #ifdef CONFIG_SPL_BUILD 342 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 343 #endif 344 345 /* DDR Setup */ 346 #define CONFIG_SYS_FSL_DDR3 347 #define CONFIG_SYS_DDR_RAW_TIMING 348 #define CONFIG_DDR_SPD 349 #define CONFIG_SYS_SPD_BUS_NUM 1 350 #define SPD_EEPROM_ADDRESS 0x52 351 #undef CONFIG_FSL_DDR_INTERACTIVE 352 353 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 354 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 355 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 356 #else 357 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 358 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 359 #endif 360 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 361 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 362 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 363 364 #define CONFIG_NUM_DDR_CONTROLLERS 1 365 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 366 367 /* Default settings for DDR3 */ 368 #ifndef CONFIG_P2020RDB 369 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 370 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 371 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 372 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 373 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 374 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 375 376 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 377 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 378 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 379 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 380 381 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 382 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 383 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 384 #define CONFIG_SYS_DDR_RCW_1 0x00000000 385 #define CONFIG_SYS_DDR_RCW_2 0x00000000 386 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 387 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 388 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 389 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 390 391 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 392 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 393 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 394 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 395 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 396 #define CONFIG_SYS_DDR_MODE_1 0x40461520 397 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 398 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 399 #endif 400 401 #undef CONFIG_CLOCKS_IN_MHZ 402 403 /* 404 * Memory map 405 * 406 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 407 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 408 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 409 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 410 * (early boot only) 411 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 412 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 413 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 414 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 415 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 416 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 417 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 418 */ 419 420 /* 421 * Local Bus Definitions 422 */ 423 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 424 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 425 #define CONFIG_SYS_FLASH_BASE 0xec000000 426 #elif defined(CONFIG_P1020UTM) 427 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 428 #define CONFIG_SYS_FLASH_BASE 0xee000000 429 #else 430 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 431 #define CONFIG_SYS_FLASH_BASE 0xef000000 432 #endif 433 434 #ifdef CONFIG_PHYS_64BIT 435 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 436 #else 437 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 438 #endif 439 440 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 441 | BR_PS_16 | BR_V) 442 443 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 444 445 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 446 #define CONFIG_SYS_FLASH_QUIET_TEST 447 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 448 449 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 450 451 #undef CONFIG_SYS_FLASH_CHECKSUM 452 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 453 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 454 455 #define CONFIG_FLASH_CFI_DRIVER 456 #define CONFIG_SYS_FLASH_CFI 457 #define CONFIG_SYS_FLASH_EMPTY_INFO 458 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 459 460 /* Nand Flash */ 461 #ifdef CONFIG_NAND_FSL_ELBC 462 #define CONFIG_SYS_NAND_BASE 0xff800000 463 #ifdef CONFIG_PHYS_64BIT 464 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 465 #else 466 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 467 #endif 468 469 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 470 #define CONFIG_SYS_MAX_NAND_DEVICE 1 471 #define CONFIG_CMD_NAND 472 #if defined(CONFIG_P1020RDB_PD) 473 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 474 #else 475 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 476 #endif 477 478 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 479 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 480 | BR_PS_8 /* Port Size = 8 bit */ \ 481 | BR_MS_FCM /* MSEL = FCM */ \ 482 | BR_V) /* valid */ 483 #if defined(CONFIG_P1020RDB_PD) 484 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 485 | OR_FCM_PGS /* Large Page*/ \ 486 | OR_FCM_CSCT \ 487 | OR_FCM_CST \ 488 | OR_FCM_CHT \ 489 | OR_FCM_SCY_1 \ 490 | OR_FCM_TRLX \ 491 | OR_FCM_EHTR) 492 #else 493 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 494 | OR_FCM_CSCT \ 495 | OR_FCM_CST \ 496 | OR_FCM_CHT \ 497 | OR_FCM_SCY_1 \ 498 | OR_FCM_TRLX \ 499 | OR_FCM_EHTR) 500 #endif 501 #endif /* CONFIG_NAND_FSL_ELBC */ 502 503 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 504 505 #define CONFIG_SYS_INIT_RAM_LOCK 506 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 507 #ifdef CONFIG_PHYS_64BIT 508 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 509 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 510 /* The assembler doesn't like typecast */ 511 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 512 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 513 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 514 #else 515 /* Initial L1 address */ 516 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 517 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 518 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 519 #endif 520 /* Size of used area in RAM */ 521 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 522 523 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 524 GENERATED_GBL_DATA_SIZE) 525 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 526 527 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 528 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 529 530 #define CONFIG_SYS_CPLD_BASE 0xffa00000 531 #ifdef CONFIG_PHYS_64BIT 532 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 533 #else 534 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 535 #endif 536 /* CPLD config size: 1Mb */ 537 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 538 BR_PS_8 | BR_V) 539 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 540 541 #define CONFIG_SYS_PMC_BASE 0xff980000 542 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 543 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 544 BR_PS_8 | BR_V) 545 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 546 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 547 OR_GPCM_EAD) 548 549 #ifdef CONFIG_NAND 550 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 551 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 552 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 553 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 554 #else 555 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 556 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 557 #ifdef CONFIG_NAND_FSL_ELBC 558 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 559 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 560 #endif 561 #endif 562 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 563 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 564 565 /* Vsc7385 switch */ 566 #ifdef CONFIG_VSC7385_ENET 567 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 568 569 #ifdef CONFIG_PHYS_64BIT 570 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 571 #else 572 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 573 #endif 574 575 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 576 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 577 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 578 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 579 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 580 581 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 582 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 583 584 /* The size of the VSC7385 firmware image */ 585 #define CONFIG_VSC7385_IMAGE_SIZE 8192 586 #endif 587 588 /* 589 * Config the L2 Cache as L2 SRAM 590 */ 591 #if defined(CONFIG_SPL_BUILD) 592 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 593 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 594 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 595 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 596 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 597 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 598 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 599 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 600 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 601 #if defined(CONFIG_P2020RDB) 602 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 603 #else 604 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 605 #endif 606 #elif defined(CONFIG_NAND) 607 #ifdef CONFIG_TPL_BUILD 608 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 609 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 610 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 611 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 612 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 613 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 614 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 615 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 616 #else 617 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 618 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 619 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 620 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 621 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 622 #endif /* CONFIG_TPL_BUILD */ 623 #endif 624 #endif 625 626 /* Serial Port - controlled on board with jumper J8 627 * open - index 2 628 * shorted - index 1 629 */ 630 #define CONFIG_CONS_INDEX 1 631 #undef CONFIG_SERIAL_SOFTWARE_FIFO 632 #define CONFIG_SYS_NS16550_SERIAL 633 #define CONFIG_SYS_NS16550_REG_SIZE 1 634 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 635 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 636 #define CONFIG_NS16550_MIN_FUNCTIONS 637 #endif 638 639 #define CONFIG_SYS_BAUDRATE_TABLE \ 640 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 641 642 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 643 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 644 645 /* I2C */ 646 #define CONFIG_SYS_I2C 647 #define CONFIG_SYS_I2C_FSL 648 #define CONFIG_SYS_FSL_I2C_SPEED 400000 649 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 650 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 651 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 652 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 653 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 654 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 655 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 656 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 657 658 /* 659 * I2C2 EEPROM 660 */ 661 #undef CONFIG_ID_EEPROM 662 663 #define CONFIG_RTC_PT7C4338 664 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 665 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 666 667 /* enable read and write access to EEPROM */ 668 #define CONFIG_CMD_EEPROM 669 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 670 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 671 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 672 673 /* 674 * eSPI - Enhanced SPI 675 */ 676 #define CONFIG_HARD_SPI 677 678 #if defined(CONFIG_SPI_FLASH) 679 #define CONFIG_SF_DEFAULT_SPEED 10000000 680 #define CONFIG_SF_DEFAULT_MODE 0 681 #endif 682 683 #if defined(CONFIG_PCI) 684 /* 685 * General PCI 686 * Memory space is mapped 1-1, but I/O space must start from 0. 687 */ 688 689 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 690 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 691 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 692 #ifdef CONFIG_PHYS_64BIT 693 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 694 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 695 #else 696 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 697 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 698 #endif 699 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 700 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 701 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 702 #ifdef CONFIG_PHYS_64BIT 703 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 704 #else 705 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 706 #endif 707 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 708 709 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 710 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 711 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 712 #ifdef CONFIG_PHYS_64BIT 713 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 714 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 715 #else 716 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 717 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 718 #endif 719 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 720 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 721 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 722 #ifdef CONFIG_PHYS_64BIT 723 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 724 #else 725 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 726 #endif 727 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 728 729 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 730 #define CONFIG_CMD_PCI 731 732 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 733 #define CONFIG_DOS_PARTITION 734 #endif /* CONFIG_PCI */ 735 736 #if defined(CONFIG_TSEC_ENET) 737 #define CONFIG_MII /* MII PHY management */ 738 #define CONFIG_TSEC1 739 #define CONFIG_TSEC1_NAME "eTSEC1" 740 #define CONFIG_TSEC2 741 #define CONFIG_TSEC2_NAME "eTSEC2" 742 #define CONFIG_TSEC3 743 #define CONFIG_TSEC3_NAME "eTSEC3" 744 745 #define TSEC1_PHY_ADDR 2 746 #define TSEC2_PHY_ADDR 0 747 #define TSEC3_PHY_ADDR 1 748 749 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 750 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 751 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 752 753 #define TSEC1_PHYIDX 0 754 #define TSEC2_PHYIDX 0 755 #define TSEC3_PHYIDX 0 756 757 #define CONFIG_ETHPRIME "eTSEC1" 758 759 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 760 761 #define CONFIG_HAS_ETH0 762 #define CONFIG_HAS_ETH1 763 #define CONFIG_HAS_ETH2 764 #endif /* CONFIG_TSEC_ENET */ 765 766 #ifdef CONFIG_QE 767 /* QE microcode/firmware address */ 768 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 769 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 770 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 771 #endif /* CONFIG_QE */ 772 773 #ifdef CONFIG_P1025RDB 774 /* 775 * QE UEC ethernet configuration 776 */ 777 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 778 779 #undef CONFIG_UEC_ETH 780 #define CONFIG_PHY_MODE_NEED_CHANGE 781 782 #define CONFIG_UEC_ETH1 /* ETH1 */ 783 #define CONFIG_HAS_ETH0 784 785 #ifdef CONFIG_UEC_ETH1 786 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 787 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 788 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 789 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 790 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 791 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 792 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 793 #endif /* CONFIG_UEC_ETH1 */ 794 795 #define CONFIG_UEC_ETH5 /* ETH5 */ 796 #define CONFIG_HAS_ETH1 797 798 #ifdef CONFIG_UEC_ETH5 799 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 800 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 801 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 802 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 803 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 804 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 805 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 806 #endif /* CONFIG_UEC_ETH5 */ 807 #endif /* CONFIG_P1025RDB */ 808 809 /* 810 * Environment 811 */ 812 #ifdef CONFIG_SPIFLASH 813 #define CONFIG_ENV_IS_IN_SPI_FLASH 814 #define CONFIG_ENV_SPI_BUS 0 815 #define CONFIG_ENV_SPI_CS 0 816 #define CONFIG_ENV_SPI_MAX_HZ 10000000 817 #define CONFIG_ENV_SPI_MODE 0 818 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 819 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 820 #define CONFIG_ENV_SECT_SIZE 0x10000 821 #elif defined(CONFIG_SDCARD) 822 #define CONFIG_ENV_IS_IN_MMC 823 #define CONFIG_FSL_FIXED_MMC_LOCATION 824 #define CONFIG_ENV_SIZE 0x2000 825 #define CONFIG_SYS_MMC_ENV_DEV 0 826 #elif defined(CONFIG_NAND) 827 #ifdef CONFIG_TPL_BUILD 828 #define CONFIG_ENV_SIZE 0x2000 829 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 830 #else 831 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 832 #endif 833 #define CONFIG_ENV_IS_IN_NAND 834 #define CONFIG_ENV_OFFSET (1024 * 1024) 835 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 836 #elif defined(CONFIG_SYS_RAMBOOT) 837 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 838 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 839 #define CONFIG_ENV_SIZE 0x2000 840 #else 841 #define CONFIG_ENV_IS_IN_FLASH 842 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 843 #define CONFIG_ENV_SIZE 0x2000 844 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 845 #endif 846 847 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 848 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 849 850 /* 851 * Command line configuration. 852 */ 853 #define CONFIG_CMD_IRQ 854 #define CONFIG_CMD_DATE 855 #define CONFIG_CMD_REGINFO 856 857 /* 858 * USB 859 */ 860 #define CONFIG_HAS_FSL_DR_USB 861 862 #if defined(CONFIG_HAS_FSL_DR_USB) 863 #define CONFIG_USB_EHCI 864 865 #ifdef CONFIG_USB_EHCI 866 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 867 #define CONFIG_USB_EHCI_FSL 868 #endif 869 #endif 870 871 #if defined(CONFIG_P1020RDB_PD) 872 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 873 #endif 874 875 #define CONFIG_MMC 876 877 #ifdef CONFIG_MMC 878 #define CONFIG_FSL_ESDHC 879 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 880 #define CONFIG_GENERIC_MMC 881 #endif 882 883 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 884 || defined(CONFIG_FSL_SATA) 885 #define CONFIG_DOS_PARTITION 886 #endif 887 888 #undef CONFIG_WATCHDOG /* watchdog disabled */ 889 890 /* 891 * Miscellaneous configurable options 892 */ 893 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 894 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 895 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 896 #if defined(CONFIG_CMD_KGDB) 897 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 898 #else 899 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 900 #endif 901 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 902 /* Print Buffer Size */ 903 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 904 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 905 906 /* 907 * For booting Linux, the board info and command line data 908 * have to be in the first 64 MB of memory, since this is 909 * the maximum mapped by the Linux kernel during initialization. 910 */ 911 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 912 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 913 914 #if defined(CONFIG_CMD_KGDB) 915 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 916 #endif 917 918 /* 919 * Environment Configuration 920 */ 921 #define CONFIG_HOSTNAME unknown 922 #define CONFIG_ROOTPATH "/opt/nfsroot" 923 #define CONFIG_BOOTFILE "uImage" 924 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 925 926 /* default location for tftp and bootm */ 927 #define CONFIG_LOADADDR 1000000 928 929 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 930 931 #define CONFIG_BAUDRATE 115200 932 933 #ifdef __SW_BOOT_NOR 934 #define __NOR_RST_CMD \ 935 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 936 i2c mw 18 3 __SW_BOOT_MASK 1; reset 937 #endif 938 #ifdef __SW_BOOT_SPI 939 #define __SPI_RST_CMD \ 940 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 941 i2c mw 18 3 __SW_BOOT_MASK 1; reset 942 #endif 943 #ifdef __SW_BOOT_SD 944 #define __SD_RST_CMD \ 945 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 946 i2c mw 18 3 __SW_BOOT_MASK 1; reset 947 #endif 948 #ifdef __SW_BOOT_NAND 949 #define __NAND_RST_CMD \ 950 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 951 i2c mw 18 3 __SW_BOOT_MASK 1; reset 952 #endif 953 #ifdef __SW_BOOT_PCIE 954 #define __PCIE_RST_CMD \ 955 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 956 i2c mw 18 3 __SW_BOOT_MASK 1; reset 957 #endif 958 959 #define CONFIG_EXTRA_ENV_SETTINGS \ 960 "netdev=eth0\0" \ 961 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 962 "loadaddr=1000000\0" \ 963 "bootfile=uImage\0" \ 964 "tftpflash=tftpboot $loadaddr $uboot; " \ 965 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 966 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 967 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 968 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 969 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 970 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 971 "consoledev=ttyS0\0" \ 972 "ramdiskaddr=2000000\0" \ 973 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 974 "fdtaddr=1e00000\0" \ 975 "bdev=sda1\0" \ 976 "jffs2nor=mtdblock3\0" \ 977 "norbootaddr=ef080000\0" \ 978 "norfdtaddr=ef040000\0" \ 979 "jffs2nand=mtdblock9\0" \ 980 "nandbootaddr=100000\0" \ 981 "nandfdtaddr=80000\0" \ 982 "ramdisk_size=120000\0" \ 983 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 984 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 985 __stringify(__NOR_RST_CMD)"\0" \ 986 __stringify(__SPI_RST_CMD)"\0" \ 987 __stringify(__SD_RST_CMD)"\0" \ 988 __stringify(__NAND_RST_CMD)"\0" \ 989 __stringify(__PCIE_RST_CMD)"\0" 990 991 #define CONFIG_NFSBOOTCOMMAND \ 992 "setenv bootargs root=/dev/nfs rw " \ 993 "nfsroot=$serverip:$rootpath " \ 994 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 995 "console=$consoledev,$baudrate $othbootargs;" \ 996 "tftp $loadaddr $bootfile;" \ 997 "tftp $fdtaddr $fdtfile;" \ 998 "bootm $loadaddr - $fdtaddr" 999 1000 #define CONFIG_HDBOOT \ 1001 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 1002 "console=$consoledev,$baudrate $othbootargs;" \ 1003 "usb start;" \ 1004 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 1005 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 1006 "bootm $loadaddr - $fdtaddr" 1007 1008 #define CONFIG_USB_FAT_BOOT \ 1009 "setenv bootargs root=/dev/ram rw " \ 1010 "console=$consoledev,$baudrate $othbootargs " \ 1011 "ramdisk_size=$ramdisk_size;" \ 1012 "usb start;" \ 1013 "fatload usb 0:2 $loadaddr $bootfile;" \ 1014 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 1015 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 1016 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1017 1018 #define CONFIG_USB_EXT2_BOOT \ 1019 "setenv bootargs root=/dev/ram rw " \ 1020 "console=$consoledev,$baudrate $othbootargs " \ 1021 "ramdisk_size=$ramdisk_size;" \ 1022 "usb start;" \ 1023 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1024 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1025 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1026 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1027 1028 #define CONFIG_NORBOOT \ 1029 "setenv bootargs root=/dev/$jffs2nor rw " \ 1030 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1031 "bootm $norbootaddr - $norfdtaddr" 1032 1033 #define CONFIG_RAMBOOTCOMMAND \ 1034 "setenv bootargs root=/dev/ram rw " \ 1035 "console=$consoledev,$baudrate $othbootargs " \ 1036 "ramdisk_size=$ramdisk_size;" \ 1037 "tftp $ramdiskaddr $ramdiskfile;" \ 1038 "tftp $loadaddr $bootfile;" \ 1039 "tftp $fdtaddr $fdtfile;" \ 1040 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1041 1042 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1043 1044 #endif /* __CONFIG_H */ 1045