1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_SYS_GENERIC_BOARD 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #ifdef CONFIG_36BIT 17 #define CONFIG_PHYS_64BIT 18 #endif 19 20 #if defined(CONFIG_P1020MBG) 21 #define CONFIG_BOARDNAME "P1020MBG-PC" 22 #define CONFIG_P1020 23 #define CONFIG_VSC7385_ENET 24 #define CONFIG_SLIC 25 #define __SW_BOOT_MASK 0x03 26 #define __SW_BOOT_NOR 0xe4 27 #define __SW_BOOT_SD 0x54 28 #define CONFIG_SYS_L2_SIZE (256 << 10) 29 #endif 30 31 #if defined(CONFIG_P1020UTM) 32 #define CONFIG_BOARDNAME "P1020UTM-PC" 33 #define CONFIG_P1020 34 #define __SW_BOOT_MASK 0x03 35 #define __SW_BOOT_NOR 0xe0 36 #define __SW_BOOT_SD 0x50 37 #define CONFIG_SYS_L2_SIZE (256 << 10) 38 #endif 39 40 #if defined(CONFIG_P1020RDB_PC) 41 #define CONFIG_BOARDNAME "P1020RDB-PC" 42 #define CONFIG_NAND_FSL_ELBC 43 #define CONFIG_P1020 44 #define CONFIG_SPI_FLASH 45 #define CONFIG_VSC7385_ENET 46 #define CONFIG_SLIC 47 #define __SW_BOOT_MASK 0x03 48 #define __SW_BOOT_NOR 0x5c 49 #define __SW_BOOT_SPI 0x1c 50 #define __SW_BOOT_SD 0x9c 51 #define __SW_BOOT_NAND 0xec 52 #define __SW_BOOT_PCIE 0x6c 53 #define CONFIG_SYS_L2_SIZE (256 << 10) 54 #endif 55 56 /* 57 * P1020RDB-PD board has user selectable switches for evaluating different 58 * frequency and boot options for the P1020 device. The table that 59 * follow describe the available options. The front six binary number was in 60 * accordance with SW3[1:6]. 61 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 62 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 63 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 64 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 65 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 66 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 67 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 68 */ 69 #if defined(CONFIG_P1020RDB_PD) 70 #define CONFIG_BOARDNAME "P1020RDB-PD" 71 #define CONFIG_NAND_FSL_ELBC 72 #define CONFIG_P1020 73 #define CONFIG_SPI_FLASH 74 #define CONFIG_VSC7385_ENET 75 #define CONFIG_SLIC 76 #define __SW_BOOT_MASK 0x03 77 #define __SW_BOOT_NOR 0x64 78 #define __SW_BOOT_SPI 0x34 79 #define __SW_BOOT_SD 0x24 80 #define __SW_BOOT_NAND 0x44 81 #define __SW_BOOT_PCIE 0x74 82 #define CONFIG_SYS_L2_SIZE (256 << 10) 83 /* 84 * Dynamic MTD Partition support with mtdparts 85 */ 86 #define CONFIG_MTD_DEVICE 87 #define CONFIG_MTD_PARTITIONS 88 #define CONFIG_CMD_MTDPARTS 89 #define CONFIG_FLASH_CFI_MTD 90 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 91 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ 92 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" 93 #endif 94 95 #if defined(CONFIG_P1021RDB) 96 #define CONFIG_BOARDNAME "P1021RDB-PC" 97 #define CONFIG_NAND_FSL_ELBC 98 #define CONFIG_P1021 99 #define CONFIG_QE 100 #define CONFIG_SPI_FLASH 101 #define CONFIG_VSC7385_ENET 102 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 103 addresses in the LBC */ 104 #define __SW_BOOT_MASK 0x03 105 #define __SW_BOOT_NOR 0x5c 106 #define __SW_BOOT_SPI 0x1c 107 #define __SW_BOOT_SD 0x9c 108 #define __SW_BOOT_NAND 0xec 109 #define __SW_BOOT_PCIE 0x6c 110 #define CONFIG_SYS_L2_SIZE (256 << 10) 111 /* 112 * Dynamic MTD Partition support with mtdparts 113 */ 114 #define CONFIG_MTD_DEVICE 115 #define CONFIG_MTD_PARTITIONS 116 #define CONFIG_CMD_MTDPARTS 117 #define CONFIG_FLASH_CFI_MTD 118 #ifdef CONFIG_PHYS_64BIT 119 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 120 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 121 "256k(dtb),4608k(kernel),9728k(fs)," \ 122 "256k(qe-ucode-firmware),1280k(u-boot)" 123 #else 124 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 125 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 126 "256k(dtb),4608k(kernel),9728k(fs)," \ 127 "256k(qe-ucode-firmware),1280k(u-boot)" 128 #endif 129 #endif 130 131 #if defined(CONFIG_P1024RDB) 132 #define CONFIG_BOARDNAME "P1024RDB" 133 #define CONFIG_NAND_FSL_ELBC 134 #define CONFIG_P1024 135 #define CONFIG_SLIC 136 #define CONFIG_SPI_FLASH 137 #define __SW_BOOT_MASK 0xf3 138 #define __SW_BOOT_NOR 0x00 139 #define __SW_BOOT_SPI 0x08 140 #define __SW_BOOT_SD 0x04 141 #define __SW_BOOT_NAND 0x0c 142 #define CONFIG_SYS_L2_SIZE (256 << 10) 143 #endif 144 145 #if defined(CONFIG_P1025RDB) 146 #define CONFIG_BOARDNAME "P1025RDB" 147 #define CONFIG_NAND_FSL_ELBC 148 #define CONFIG_P1025 149 #define CONFIG_QE 150 #define CONFIG_SLIC 151 #define CONFIG_SPI_FLASH 152 153 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 154 addresses in the LBC */ 155 #define __SW_BOOT_MASK 0xf3 156 #define __SW_BOOT_NOR 0x00 157 #define __SW_BOOT_SPI 0x08 158 #define __SW_BOOT_SD 0x04 159 #define __SW_BOOT_NAND 0x0c 160 #define CONFIG_SYS_L2_SIZE (256 << 10) 161 #endif 162 163 #if defined(CONFIG_P2020RDB) 164 #define CONFIG_BOARDNAME "P2020RDB-PCA" 165 #define CONFIG_NAND_FSL_ELBC 166 #define CONFIG_P2020 167 #define CONFIG_SPI_FLASH 168 #define CONFIG_VSC7385_ENET 169 #define __SW_BOOT_MASK 0x03 170 #define __SW_BOOT_NOR 0xc8 171 #define __SW_BOOT_SPI 0x28 172 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 173 #define __SW_BOOT_NAND 0xe8 174 #define __SW_BOOT_PCIE 0xa8 175 #define CONFIG_SYS_L2_SIZE (512 << 10) 176 /* 177 * Dynamic MTD Partition support with mtdparts 178 */ 179 #define CONFIG_MTD_DEVICE 180 #define CONFIG_MTD_PARTITIONS 181 #define CONFIG_CMD_MTDPARTS 182 #define CONFIG_FLASH_CFI_MTD 183 #ifdef CONFIG_PHYS_64BIT 184 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 185 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 186 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 187 #else 188 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 189 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 190 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 191 #endif 192 #endif 193 194 #ifdef CONFIG_SDCARD 195 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 196 #define CONFIG_SPL_ENV_SUPPORT 197 #define CONFIG_SPL_SERIAL_SUPPORT 198 #define CONFIG_SPL_MMC_SUPPORT 199 #define CONFIG_SPL_MMC_MINIMAL 200 #define CONFIG_SPL_FLUSH_IMAGE 201 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 202 #define CONFIG_SPL_LIBGENERIC_SUPPORT 203 #define CONFIG_SPL_LIBCOMMON_SUPPORT 204 #define CONFIG_SPL_I2C_SUPPORT 205 #define CONFIG_FSL_LAW /* Use common FSL init code */ 206 #define CONFIG_SYS_TEXT_BASE 0x11001000 207 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 208 #define CONFIG_SPL_PAD_TO 0x20000 209 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 210 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 211 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 212 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 213 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 214 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 215 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 216 #define CONFIG_SPL_MMC_BOOT 217 #ifdef CONFIG_SPL_BUILD 218 #define CONFIG_SPL_COMMON_INIT_DDR 219 #endif 220 #endif 221 222 #ifdef CONFIG_SPIFLASH 223 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 224 #define CONFIG_SPL_ENV_SUPPORT 225 #define CONFIG_SPL_SERIAL_SUPPORT 226 #define CONFIG_SPL_SPI_SUPPORT 227 #define CONFIG_SPL_SPI_FLASH_SUPPORT 228 #define CONFIG_SPL_SPI_FLASH_MINIMAL 229 #define CONFIG_SPL_FLUSH_IMAGE 230 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 231 #define CONFIG_SPL_LIBGENERIC_SUPPORT 232 #define CONFIG_SPL_LIBCOMMON_SUPPORT 233 #define CONFIG_SPL_I2C_SUPPORT 234 #define CONFIG_FSL_LAW /* Use common FSL init code */ 235 #define CONFIG_SYS_TEXT_BASE 0x11001000 236 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 237 #define CONFIG_SPL_PAD_TO 0x20000 238 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 239 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 240 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 241 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 242 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 243 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 244 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 245 #define CONFIG_SPL_SPI_BOOT 246 #ifdef CONFIG_SPL_BUILD 247 #define CONFIG_SPL_COMMON_INIT_DDR 248 #endif 249 #endif 250 251 #ifdef CONFIG_NAND 252 #ifdef CONFIG_TPL_BUILD 253 #define CONFIG_SPL_NAND_BOOT 254 #define CONFIG_SPL_FLUSH_IMAGE 255 #define CONFIG_SPL_ENV_SUPPORT 256 #define CONFIG_SPL_NAND_INIT 257 #define CONFIG_SPL_SERIAL_SUPPORT 258 #define CONFIG_SPL_LIBGENERIC_SUPPORT 259 #define CONFIG_SPL_LIBCOMMON_SUPPORT 260 #define CONFIG_SPL_I2C_SUPPORT 261 #define CONFIG_SPL_NAND_SUPPORT 262 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 263 #define CONFIG_SPL_COMMON_INIT_DDR 264 #define CONFIG_SPL_MAX_SIZE (128 << 10) 265 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 266 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 267 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 268 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 269 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 270 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 271 #elif defined(CONFIG_SPL_BUILD) 272 #define CONFIG_SPL_INIT_MINIMAL 273 #define CONFIG_SPL_SERIAL_SUPPORT 274 #define CONFIG_SPL_NAND_SUPPORT 275 #define CONFIG_SPL_FLUSH_IMAGE 276 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 277 #define CONFIG_SPL_TEXT_BASE 0xff800000 278 #define CONFIG_SPL_MAX_SIZE 4096 279 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 280 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 281 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 282 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 283 #endif /* not CONFIG_TPL_BUILD */ 284 285 #define CONFIG_SPL_PAD_TO 0x20000 286 #define CONFIG_TPL_PAD_TO 0x20000 287 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 288 #define CONFIG_SYS_TEXT_BASE 0x11001000 289 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 290 #endif 291 292 #ifndef CONFIG_SYS_TEXT_BASE 293 #define CONFIG_SYS_TEXT_BASE 0xeff40000 294 #endif 295 296 #ifndef CONFIG_RESET_VECTOR_ADDRESS 297 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 298 #endif 299 300 #ifndef CONFIG_SYS_MONITOR_BASE 301 #ifdef CONFIG_SPL_BUILD 302 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 303 #else 304 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 305 #endif 306 #endif 307 308 /* High Level Configuration Options */ 309 #define CONFIG_BOOKE 310 #define CONFIG_E500 311 312 #define CONFIG_MP 313 314 #define CONFIG_FSL_ELBC 315 #define CONFIG_PCI 316 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 317 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 318 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 319 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 320 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 321 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 322 323 #define CONFIG_FSL_LAW 324 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 325 #define CONFIG_ENV_OVERWRITE 326 327 #define CONFIG_CMD_SATA 328 #define CONFIG_SATA_SIL 329 #define CONFIG_SYS_SATA_MAX_DEVICE 2 330 #define CONFIG_LIBATA 331 #define CONFIG_LBA48 332 333 #if defined(CONFIG_P2020RDB) 334 #define CONFIG_SYS_CLK_FREQ 100000000 335 #else 336 #define CONFIG_SYS_CLK_FREQ 66666666 337 #endif 338 #define CONFIG_DDR_CLK_FREQ 66666666 339 340 #define CONFIG_HWCONFIG 341 /* 342 * These can be toggled for performance analysis, otherwise use default. 343 */ 344 #define CONFIG_L2_CACHE 345 #define CONFIG_BTB 346 347 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 348 349 #define CONFIG_ENABLE_36BIT_PHYS 350 351 #ifdef CONFIG_PHYS_64BIT 352 #define CONFIG_ADDR_MAP 1 353 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 354 #endif 355 356 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 357 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 358 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 359 360 #define CONFIG_SYS_CCSRBAR 0xffe00000 361 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 362 363 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 364 SPL code*/ 365 #ifdef CONFIG_SPL_BUILD 366 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 367 #endif 368 369 /* DDR Setup */ 370 #define CONFIG_SYS_FSL_DDR3 371 #define CONFIG_SYS_DDR_RAW_TIMING 372 #define CONFIG_DDR_SPD 373 #define CONFIG_SYS_SPD_BUS_NUM 1 374 #define SPD_EEPROM_ADDRESS 0x52 375 #undef CONFIG_FSL_DDR_INTERACTIVE 376 377 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 378 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 379 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 380 #else 381 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 382 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 383 #endif 384 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 385 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 386 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 387 388 #define CONFIG_NUM_DDR_CONTROLLERS 1 389 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 390 391 /* Default settings for DDR3 */ 392 #ifndef CONFIG_P2020RDB 393 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 394 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 395 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 396 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 397 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 398 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 399 400 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 401 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 402 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 403 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 404 405 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 406 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 407 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 408 #define CONFIG_SYS_DDR_RCW_1 0x00000000 409 #define CONFIG_SYS_DDR_RCW_2 0x00000000 410 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 411 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 412 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 413 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 414 415 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 416 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 417 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 418 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 419 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 420 #define CONFIG_SYS_DDR_MODE_1 0x40461520 421 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 422 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 423 #endif 424 425 #undef CONFIG_CLOCKS_IN_MHZ 426 427 /* 428 * Memory map 429 * 430 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 431 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 432 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 433 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 434 * (early boot only) 435 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 436 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 437 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 438 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 439 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 440 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 441 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 442 */ 443 444 445 /* 446 * Local Bus Definitions 447 */ 448 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 449 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 450 #define CONFIG_SYS_FLASH_BASE 0xec000000 451 #elif defined(CONFIG_P1020UTM) 452 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 453 #define CONFIG_SYS_FLASH_BASE 0xee000000 454 #else 455 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 456 #define CONFIG_SYS_FLASH_BASE 0xef000000 457 #endif 458 459 460 #ifdef CONFIG_PHYS_64BIT 461 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 462 #else 463 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 464 #endif 465 466 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 467 | BR_PS_16 | BR_V) 468 469 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 470 471 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 472 #define CONFIG_SYS_FLASH_QUIET_TEST 473 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 474 475 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 476 477 #undef CONFIG_SYS_FLASH_CHECKSUM 478 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 479 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 480 481 #define CONFIG_FLASH_CFI_DRIVER 482 #define CONFIG_SYS_FLASH_CFI 483 #define CONFIG_SYS_FLASH_EMPTY_INFO 484 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 485 486 /* Nand Flash */ 487 #ifdef CONFIG_NAND_FSL_ELBC 488 #define CONFIG_SYS_NAND_BASE 0xff800000 489 #ifdef CONFIG_PHYS_64BIT 490 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 491 #else 492 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 493 #endif 494 495 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 496 #define CONFIG_SYS_MAX_NAND_DEVICE 1 497 #define CONFIG_MTD_NAND_VERIFY_WRITE 498 #define CONFIG_CMD_NAND 499 #if defined(CONFIG_P1020RDB_PD) 500 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 501 #else 502 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 503 #endif 504 505 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 506 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 507 | BR_PS_8 /* Port Size = 8 bit */ \ 508 | BR_MS_FCM /* MSEL = FCM */ \ 509 | BR_V) /* valid */ 510 #if defined(CONFIG_P1020RDB_PD) 511 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 512 | OR_FCM_PGS /* Large Page*/ \ 513 | OR_FCM_CSCT \ 514 | OR_FCM_CST \ 515 | OR_FCM_CHT \ 516 | OR_FCM_SCY_1 \ 517 | OR_FCM_TRLX \ 518 | OR_FCM_EHTR) 519 #else 520 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 521 | OR_FCM_CSCT \ 522 | OR_FCM_CST \ 523 | OR_FCM_CHT \ 524 | OR_FCM_SCY_1 \ 525 | OR_FCM_TRLX \ 526 | OR_FCM_EHTR) 527 #endif 528 #endif /* CONFIG_NAND_FSL_ELBC */ 529 530 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 531 532 #define CONFIG_SYS_INIT_RAM_LOCK 533 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 534 #ifdef CONFIG_PHYS_64BIT 535 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 536 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 537 /* The assembler doesn't like typecast */ 538 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 539 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 540 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 541 #else 542 /* Initial L1 address */ 543 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 544 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 545 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 546 #endif 547 /* Size of used area in RAM */ 548 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 549 550 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 551 GENERATED_GBL_DATA_SIZE) 552 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 553 554 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 555 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 556 557 #define CONFIG_SYS_CPLD_BASE 0xffa00000 558 #ifdef CONFIG_PHYS_64BIT 559 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 560 #else 561 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 562 #endif 563 /* CPLD config size: 1Mb */ 564 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 565 BR_PS_8 | BR_V) 566 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 567 568 #define CONFIG_SYS_PMC_BASE 0xff980000 569 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 570 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 571 BR_PS_8 | BR_V) 572 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 573 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 574 OR_GPCM_EAD) 575 576 #ifdef CONFIG_NAND 577 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 578 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 579 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 580 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 581 #else 582 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 583 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 584 #ifdef CONFIG_NAND_FSL_ELBC 585 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 586 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 587 #endif 588 #endif 589 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 590 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 591 592 593 /* Vsc7385 switch */ 594 #ifdef CONFIG_VSC7385_ENET 595 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 596 597 #ifdef CONFIG_PHYS_64BIT 598 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 599 #else 600 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 601 #endif 602 603 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 604 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 605 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 606 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 607 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 608 609 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 610 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 611 612 /* The size of the VSC7385 firmware image */ 613 #define CONFIG_VSC7385_IMAGE_SIZE 8192 614 #endif 615 616 /* 617 * Config the L2 Cache as L2 SRAM 618 */ 619 #if defined(CONFIG_SPL_BUILD) 620 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 621 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 622 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 623 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 624 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 625 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 626 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 627 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 628 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 629 #if defined(CONFIG_P2020RDB) 630 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 631 #else 632 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 633 #endif 634 #elif defined(CONFIG_NAND) 635 #ifdef CONFIG_TPL_BUILD 636 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 637 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 638 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 639 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 640 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 641 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 642 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 643 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 644 #else 645 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 646 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 647 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 648 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 649 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 650 #endif /* CONFIG_TPL_BUILD */ 651 #endif 652 #endif 653 654 /* Serial Port - controlled on board with jumper J8 655 * open - index 2 656 * shorted - index 1 657 */ 658 #define CONFIG_CONS_INDEX 1 659 #undef CONFIG_SERIAL_SOFTWARE_FIFO 660 #define CONFIG_SYS_NS16550 661 #define CONFIG_SYS_NS16550_SERIAL 662 #define CONFIG_SYS_NS16550_REG_SIZE 1 663 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 664 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 665 #define CONFIG_NS16550_MIN_FUNCTIONS 666 #endif 667 668 #define CONFIG_SYS_BAUDRATE_TABLE \ 669 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 670 671 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 672 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 673 674 /* Use the HUSH parser */ 675 #define CONFIG_SYS_HUSH_PARSER 676 677 /* 678 * Pass open firmware flat tree 679 */ 680 #define CONFIG_OF_LIBFDT 681 #define CONFIG_OF_BOARD_SETUP 682 #define CONFIG_OF_STDOUT_VIA_ALIAS 683 684 /* new uImage format support */ 685 #define CONFIG_FIT 686 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 687 688 /* I2C */ 689 #define CONFIG_SYS_I2C 690 #define CONFIG_SYS_I2C_FSL 691 #define CONFIG_SYS_FSL_I2C_SPEED 400000 692 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 693 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 694 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 695 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 696 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 697 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 698 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 699 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 700 701 /* 702 * I2C2 EEPROM 703 */ 704 #undef CONFIG_ID_EEPROM 705 706 #define CONFIG_RTC_PT7C4338 707 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 708 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 709 710 /* enable read and write access to EEPROM */ 711 #define CONFIG_CMD_EEPROM 712 #define CONFIG_SYS_I2C_MULTI_EEPROMS 713 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 714 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 715 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 716 717 /* 718 * eSPI - Enhanced SPI 719 */ 720 #define CONFIG_HARD_SPI 721 #define CONFIG_FSL_ESPI 722 723 #if defined(CONFIG_SPI_FLASH) 724 #define CONFIG_SPI_FLASH_SPANSION 725 #define CONFIG_CMD_SF 726 #define CONFIG_SF_DEFAULT_SPEED 10000000 727 #define CONFIG_SF_DEFAULT_MODE 0 728 #endif 729 730 #if defined(CONFIG_PCI) 731 /* 732 * General PCI 733 * Memory space is mapped 1-1, but I/O space must start from 0. 734 */ 735 736 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 737 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 738 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 739 #ifdef CONFIG_PHYS_64BIT 740 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 741 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 742 #else 743 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 744 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 745 #endif 746 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 747 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 748 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 749 #ifdef CONFIG_PHYS_64BIT 750 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 751 #else 752 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 753 #endif 754 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 755 756 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 757 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 758 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 759 #ifdef CONFIG_PHYS_64BIT 760 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 761 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 762 #else 763 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 764 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 765 #endif 766 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 767 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 768 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 769 #ifdef CONFIG_PHYS_64BIT 770 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 771 #else 772 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 773 #endif 774 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 775 776 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 777 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ 778 #define CONFIG_CMD_PCI 779 #define CONFIG_CMD_NET 780 781 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 782 #define CONFIG_DOS_PARTITION 783 #endif /* CONFIG_PCI */ 784 785 #if defined(CONFIG_TSEC_ENET) 786 #define CONFIG_MII /* MII PHY management */ 787 #define CONFIG_TSEC1 788 #define CONFIG_TSEC1_NAME "eTSEC1" 789 #define CONFIG_TSEC2 790 #define CONFIG_TSEC2_NAME "eTSEC2" 791 #define CONFIG_TSEC3 792 #define CONFIG_TSEC3_NAME "eTSEC3" 793 794 #define TSEC1_PHY_ADDR 2 795 #define TSEC2_PHY_ADDR 0 796 #define TSEC3_PHY_ADDR 1 797 798 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 799 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 800 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 801 802 #define TSEC1_PHYIDX 0 803 #define TSEC2_PHYIDX 0 804 #define TSEC3_PHYIDX 0 805 806 #define CONFIG_ETHPRIME "eTSEC1" 807 808 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 809 810 #define CONFIG_HAS_ETH0 811 #define CONFIG_HAS_ETH1 812 #define CONFIG_HAS_ETH2 813 #endif /* CONFIG_TSEC_ENET */ 814 815 #ifdef CONFIG_QE 816 /* QE microcode/firmware address */ 817 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 818 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 819 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 820 #endif /* CONFIG_QE */ 821 822 #ifdef CONFIG_P1025RDB 823 /* 824 * QE UEC ethernet configuration 825 */ 826 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 827 828 #undef CONFIG_UEC_ETH 829 #define CONFIG_PHY_MODE_NEED_CHANGE 830 831 #define CONFIG_UEC_ETH1 /* ETH1 */ 832 #define CONFIG_HAS_ETH0 833 834 #ifdef CONFIG_UEC_ETH1 835 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 836 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 837 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 838 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 839 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 840 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 841 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 842 #endif /* CONFIG_UEC_ETH1 */ 843 844 #define CONFIG_UEC_ETH5 /* ETH5 */ 845 #define CONFIG_HAS_ETH1 846 847 #ifdef CONFIG_UEC_ETH5 848 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 849 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 850 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 851 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 852 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 853 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 854 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 855 #endif /* CONFIG_UEC_ETH5 */ 856 #endif /* CONFIG_P1025RDB */ 857 858 /* 859 * Environment 860 */ 861 #ifdef CONFIG_SPIFLASH 862 #define CONFIG_ENV_IS_IN_SPI_FLASH 863 #define CONFIG_ENV_SPI_BUS 0 864 #define CONFIG_ENV_SPI_CS 0 865 #define CONFIG_ENV_SPI_MAX_HZ 10000000 866 #define CONFIG_ENV_SPI_MODE 0 867 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 868 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 869 #define CONFIG_ENV_SECT_SIZE 0x10000 870 #elif defined(CONFIG_SDCARD) 871 #define CONFIG_ENV_IS_IN_MMC 872 #define CONFIG_FSL_FIXED_MMC_LOCATION 873 #define CONFIG_ENV_SIZE 0x2000 874 #define CONFIG_SYS_MMC_ENV_DEV 0 875 #elif defined(CONFIG_NAND) 876 #ifdef CONFIG_TPL_BUILD 877 #define CONFIG_ENV_SIZE 0x2000 878 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 879 #else 880 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 881 #endif 882 #define CONFIG_ENV_IS_IN_NAND 883 #define CONFIG_ENV_OFFSET (1024 * 1024) 884 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 885 #elif defined(CONFIG_SYS_RAMBOOT) 886 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 887 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 888 #define CONFIG_ENV_SIZE 0x2000 889 #else 890 #define CONFIG_ENV_IS_IN_FLASH 891 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 892 #define CONFIG_ENV_SIZE 0x2000 893 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 894 #endif 895 896 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 897 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 898 899 /* 900 * Command line configuration. 901 */ 902 #include <config_cmd_default.h> 903 904 #define CONFIG_CMD_IRQ 905 #define CONFIG_CMD_PING 906 #define CONFIG_CMD_I2C 907 #define CONFIG_CMD_MII 908 #define CONFIG_CMD_DATE 909 #define CONFIG_CMD_ELF 910 #define CONFIG_CMD_SETEXPR 911 #define CONFIG_CMD_REGINFO 912 913 /* 914 * USB 915 */ 916 #define CONFIG_HAS_FSL_DR_USB 917 918 #if defined(CONFIG_HAS_FSL_DR_USB) 919 #define CONFIG_USB_EHCI 920 921 #ifdef CONFIG_USB_EHCI 922 #define CONFIG_CMD_USB 923 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 924 #define CONFIG_USB_EHCI_FSL 925 #define CONFIG_USB_STORAGE 926 #endif 927 #endif 928 929 #if defined(CONFIG_P1020RDB_PD) 930 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 931 #endif 932 933 #define CONFIG_MMC 934 935 #ifdef CONFIG_MMC 936 #define CONFIG_FSL_ESDHC 937 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 938 #define CONFIG_CMD_MMC 939 #define CONFIG_GENERIC_MMC 940 #endif 941 942 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 943 || defined(CONFIG_FSL_SATA) 944 #define CONFIG_CMD_EXT2 945 #define CONFIG_CMD_FAT 946 #define CONFIG_DOS_PARTITION 947 #endif 948 949 #undef CONFIG_WATCHDOG /* watchdog disabled */ 950 951 /* 952 * Miscellaneous configurable options 953 */ 954 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 955 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 956 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 957 #if defined(CONFIG_CMD_KGDB) 958 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 959 #else 960 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 961 #endif 962 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 963 /* Print Buffer Size */ 964 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 965 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 966 967 /* 968 * For booting Linux, the board info and command line data 969 * have to be in the first 64 MB of memory, since this is 970 * the maximum mapped by the Linux kernel during initialization. 971 */ 972 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 973 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 974 975 #if defined(CONFIG_CMD_KGDB) 976 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 977 #endif 978 979 /* 980 * Environment Configuration 981 */ 982 #define CONFIG_HOSTNAME unknown 983 #define CONFIG_ROOTPATH "/opt/nfsroot" 984 #define CONFIG_BOOTFILE "uImage" 985 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 986 987 /* default location for tftp and bootm */ 988 #define CONFIG_LOADADDR 1000000 989 990 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 991 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 992 993 #define CONFIG_BAUDRATE 115200 994 995 #ifdef __SW_BOOT_NOR 996 #define __NOR_RST_CMD \ 997 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 998 i2c mw 18 3 __SW_BOOT_MASK 1; reset 999 #endif 1000 #ifdef __SW_BOOT_SPI 1001 #define __SPI_RST_CMD \ 1002 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 1003 i2c mw 18 3 __SW_BOOT_MASK 1; reset 1004 #endif 1005 #ifdef __SW_BOOT_SD 1006 #define __SD_RST_CMD \ 1007 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 1008 i2c mw 18 3 __SW_BOOT_MASK 1; reset 1009 #endif 1010 #ifdef __SW_BOOT_NAND 1011 #define __NAND_RST_CMD \ 1012 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 1013 i2c mw 18 3 __SW_BOOT_MASK 1; reset 1014 #endif 1015 #ifdef __SW_BOOT_PCIE 1016 #define __PCIE_RST_CMD \ 1017 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 1018 i2c mw 18 3 __SW_BOOT_MASK 1; reset 1019 #endif 1020 1021 #define CONFIG_EXTRA_ENV_SETTINGS \ 1022 "netdev=eth0\0" \ 1023 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 1024 "loadaddr=1000000\0" \ 1025 "bootfile=uImage\0" \ 1026 "tftpflash=tftpboot $loadaddr $uboot; " \ 1027 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 1028 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 1029 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 1030 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 1031 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 1032 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 1033 "consoledev=ttyS0\0" \ 1034 "ramdiskaddr=2000000\0" \ 1035 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 1036 "fdtaddr=c00000\0" \ 1037 "bdev=sda1\0" \ 1038 "jffs2nor=mtdblock3\0" \ 1039 "norbootaddr=ef080000\0" \ 1040 "norfdtaddr=ef040000\0" \ 1041 "jffs2nand=mtdblock9\0" \ 1042 "nandbootaddr=100000\0" \ 1043 "nandfdtaddr=80000\0" \ 1044 "ramdisk_size=120000\0" \ 1045 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 1046 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 1047 __stringify(__NOR_RST_CMD)"\0" \ 1048 __stringify(__SPI_RST_CMD)"\0" \ 1049 __stringify(__SD_RST_CMD)"\0" \ 1050 __stringify(__NAND_RST_CMD)"\0" \ 1051 __stringify(__PCIE_RST_CMD)"\0" 1052 1053 #define CONFIG_NFSBOOTCOMMAND \ 1054 "setenv bootargs root=/dev/nfs rw " \ 1055 "nfsroot=$serverip:$rootpath " \ 1056 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 1057 "console=$consoledev,$baudrate $othbootargs;" \ 1058 "tftp $loadaddr $bootfile;" \ 1059 "tftp $fdtaddr $fdtfile;" \ 1060 "bootm $loadaddr - $fdtaddr" 1061 1062 #define CONFIG_HDBOOT \ 1063 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 1064 "console=$consoledev,$baudrate $othbootargs;" \ 1065 "usb start;" \ 1066 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 1067 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 1068 "bootm $loadaddr - $fdtaddr" 1069 1070 #define CONFIG_USB_FAT_BOOT \ 1071 "setenv bootargs root=/dev/ram rw " \ 1072 "console=$consoledev,$baudrate $othbootargs " \ 1073 "ramdisk_size=$ramdisk_size;" \ 1074 "usb start;" \ 1075 "fatload usb 0:2 $loadaddr $bootfile;" \ 1076 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 1077 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 1078 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1079 1080 #define CONFIG_USB_EXT2_BOOT \ 1081 "setenv bootargs root=/dev/ram rw " \ 1082 "console=$consoledev,$baudrate $othbootargs " \ 1083 "ramdisk_size=$ramdisk_size;" \ 1084 "usb start;" \ 1085 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1086 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1087 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1088 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1089 1090 #define CONFIG_NORBOOT \ 1091 "setenv bootargs root=/dev/$jffs2nor rw " \ 1092 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1093 "bootm $norbootaddr - $norfdtaddr" 1094 1095 #define CONFIG_RAMBOOTCOMMAND \ 1096 "setenv bootargs root=/dev/ram rw " \ 1097 "console=$consoledev,$baudrate $othbootargs " \ 1098 "ramdisk_size=$ramdisk_size;" \ 1099 "tftp $ramdiskaddr $ramdiskfile;" \ 1100 "tftp $loadaddr $bootfile;" \ 1101 "tftp $fdtaddr $fdtfile;" \ 1102 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1103 1104 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1105 1106 #endif /* __CONFIG_H */ 1107