1 /*
2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 /*
8  * QorIQ RDB boards configuration file
9  */
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 #if defined(CONFIG_TARGET_P1020MBG)
14 #define CONFIG_BOARDNAME "P1020MBG-PC"
15 #define CONFIG_VSC7385_ENET
16 #define CONFIG_SLIC
17 #define __SW_BOOT_MASK		0x03
18 #define __SW_BOOT_NOR		0xe4
19 #define __SW_BOOT_SD		0x54
20 #define CONFIG_SYS_L2_SIZE	(256 << 10)
21 #endif
22 
23 #if defined(CONFIG_TARGET_P1020UTM)
24 #define CONFIG_BOARDNAME "P1020UTM-PC"
25 #define __SW_BOOT_MASK		0x03
26 #define __SW_BOOT_NOR		0xe0
27 #define __SW_BOOT_SD		0x50
28 #define CONFIG_SYS_L2_SIZE	(256 << 10)
29 #endif
30 
31 #if defined(CONFIG_TARGET_P1020RDB_PC)
32 #define CONFIG_BOARDNAME "P1020RDB-PC"
33 #define CONFIG_NAND_FSL_ELBC
34 #define CONFIG_VSC7385_ENET
35 #define CONFIG_SLIC
36 #define __SW_BOOT_MASK		0x03
37 #define __SW_BOOT_NOR		0x5c
38 #define __SW_BOOT_SPI		0x1c
39 #define __SW_BOOT_SD		0x9c
40 #define __SW_BOOT_NAND		0xec
41 #define __SW_BOOT_PCIE		0x6c
42 #define CONFIG_SYS_L2_SIZE	(256 << 10)
43 #endif
44 
45 /*
46  * P1020RDB-PD board has user selectable switches for evaluating different
47  * frequency and boot options for the P1020 device. The table that
48  * follow describe the available options. The front six binary number was in
49  * accordance with SW3[1:6].
50  * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
51  * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
52  * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
53  * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
54  * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
55  * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
56  * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
57  */
58 #if defined(CONFIG_TARGET_P1020RDB_PD)
59 #define CONFIG_BOARDNAME "P1020RDB-PD"
60 #define CONFIG_NAND_FSL_ELBC
61 #define CONFIG_VSC7385_ENET
62 #define CONFIG_SLIC
63 #define __SW_BOOT_MASK		0x03
64 #define __SW_BOOT_NOR		0x64
65 #define __SW_BOOT_SPI		0x34
66 #define __SW_BOOT_SD		0x24
67 #define __SW_BOOT_NAND		0x44
68 #define __SW_BOOT_PCIE		0x74
69 #define CONFIG_SYS_L2_SIZE	(256 << 10)
70 /*
71  * Dynamic MTD Partition support with mtdparts
72  */
73 #define CONFIG_MTD_DEVICE
74 #define CONFIG_MTD_PARTITIONS
75 #define CONFIG_CMD_MTDPARTS
76 #define CONFIG_FLASH_CFI_MTD
77 #define MTDIDS_DEFAULT "nor0=ec000000.nor"
78 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \
79 			"57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
80 #endif
81 
82 #if defined(CONFIG_TARGET_P1021RDB)
83 #define CONFIG_BOARDNAME "P1021RDB-PC"
84 #define CONFIG_NAND_FSL_ELBC
85 #define CONFIG_QE
86 #define CONFIG_VSC7385_ENET
87 #define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
88 						addresses in the LBC */
89 #define __SW_BOOT_MASK		0x03
90 #define __SW_BOOT_NOR		0x5c
91 #define __SW_BOOT_SPI		0x1c
92 #define __SW_BOOT_SD		0x9c
93 #define __SW_BOOT_NAND		0xec
94 #define __SW_BOOT_PCIE		0x6c
95 #define CONFIG_SYS_L2_SIZE	(256 << 10)
96 /*
97  * Dynamic MTD Partition support with mtdparts
98  */
99 #define CONFIG_MTD_DEVICE
100 #define CONFIG_MTD_PARTITIONS
101 #define CONFIG_CMD_MTDPARTS
102 #define CONFIG_FLASH_CFI_MTD
103 #ifdef CONFIG_PHYS_64BIT
104 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
105 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
106 			"256k(dtb),4608k(kernel),9728k(fs)," \
107 			"256k(qe-ucode-firmware),1280k(u-boot)"
108 #else
109 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
110 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
111 			"256k(dtb),4608k(kernel),9728k(fs)," \
112 			"256k(qe-ucode-firmware),1280k(u-boot)"
113 #endif
114 #endif
115 
116 #if defined(CONFIG_TARGET_P1024RDB)
117 #define CONFIG_BOARDNAME "P1024RDB"
118 #define CONFIG_NAND_FSL_ELBC
119 #define CONFIG_SLIC
120 #define __SW_BOOT_MASK		0xf3
121 #define __SW_BOOT_NOR		0x00
122 #define __SW_BOOT_SPI		0x08
123 #define __SW_BOOT_SD		0x04
124 #define __SW_BOOT_NAND		0x0c
125 #define CONFIG_SYS_L2_SIZE	(256 << 10)
126 #endif
127 
128 #if defined(CONFIG_TARGET_P1025RDB)
129 #define CONFIG_BOARDNAME "P1025RDB"
130 #define CONFIG_NAND_FSL_ELBC
131 #define CONFIG_QE
132 #define CONFIG_SLIC
133 
134 #define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
135 						addresses in the LBC */
136 #define __SW_BOOT_MASK		0xf3
137 #define __SW_BOOT_NOR		0x00
138 #define __SW_BOOT_SPI		0x08
139 #define __SW_BOOT_SD		0x04
140 #define __SW_BOOT_NAND		0x0c
141 #define CONFIG_SYS_L2_SIZE	(256 << 10)
142 #endif
143 
144 #if defined(CONFIG_TARGET_P2020RDB)
145 #define CONFIG_BOARDNAME "P2020RDB-PC"
146 #define CONFIG_NAND_FSL_ELBC
147 #define CONFIG_VSC7385_ENET
148 #define __SW_BOOT_MASK		0x03
149 #define __SW_BOOT_NOR		0xc8
150 #define __SW_BOOT_SPI		0x28
151 #define __SW_BOOT_SD		0x68 /* or 0x18 */
152 #define __SW_BOOT_NAND		0xe8
153 #define __SW_BOOT_PCIE		0xa8
154 #define CONFIG_SYS_L2_SIZE	(512 << 10)
155 /*
156  * Dynamic MTD Partition support with mtdparts
157  */
158 #define CONFIG_MTD_DEVICE
159 #define CONFIG_MTD_PARTITIONS
160 #define CONFIG_CMD_MTDPARTS
161 #define CONFIG_FLASH_CFI_MTD
162 #ifdef CONFIG_PHYS_64BIT
163 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
164 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
165 			"256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
166 #else
167 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
168 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
169 			"256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
170 #endif
171 #endif
172 
173 #ifdef CONFIG_SDCARD
174 #define CONFIG_SPL_MMC_MINIMAL
175 #define CONFIG_SPL_FLUSH_IMAGE
176 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
177 #define CONFIG_SYS_TEXT_BASE		0x11001000
178 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
179 #define CONFIG_SPL_PAD_TO		0x20000
180 #define CONFIG_SPL_MAX_SIZE		(128 * 1024)
181 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
182 #define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
183 #define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
184 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(128 << 10)
185 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
186 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
187 #define CONFIG_SPL_MMC_BOOT
188 #ifdef CONFIG_SPL_BUILD
189 #define CONFIG_SPL_COMMON_INIT_DDR
190 #endif
191 #endif
192 
193 #ifdef CONFIG_SPIFLASH
194 #define CONFIG_SPL_SPI_FLASH_MINIMAL
195 #define CONFIG_SPL_FLUSH_IMAGE
196 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
197 #define CONFIG_SYS_TEXT_BASE		0x11001000
198 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
199 #define CONFIG_SPL_PAD_TO		0x20000
200 #define CONFIG_SPL_MAX_SIZE		(128 * 1024)
201 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
202 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
203 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
204 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(128 << 10)
205 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
206 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
207 #define CONFIG_SPL_SPI_BOOT
208 #ifdef CONFIG_SPL_BUILD
209 #define CONFIG_SPL_COMMON_INIT_DDR
210 #endif
211 #endif
212 
213 #ifdef CONFIG_NAND
214 #ifdef CONFIG_TPL_BUILD
215 #define CONFIG_SPL_NAND_BOOT
216 #define CONFIG_SPL_FLUSH_IMAGE
217 #define CONFIG_SPL_NAND_INIT
218 #define CONFIG_SPL_COMMON_INIT_DDR
219 #define CONFIG_SPL_MAX_SIZE		(128 << 10)
220 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
221 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
222 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
223 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
224 #define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
225 #define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
226 #elif defined(CONFIG_SPL_BUILD)
227 #define CONFIG_SPL_INIT_MINIMAL
228 #define CONFIG_SPL_FLUSH_IMAGE
229 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
230 #define CONFIG_SPL_TEXT_BASE		0xff800000
231 #define CONFIG_SPL_MAX_SIZE		4096
232 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
233 #define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
234 #define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
235 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
236 #endif /* not CONFIG_TPL_BUILD */
237 
238 #define CONFIG_SPL_PAD_TO		0x20000
239 #define CONFIG_TPL_PAD_TO		0x20000
240 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
241 #define CONFIG_SYS_TEXT_BASE		0x11001000
242 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
243 #endif
244 
245 #ifndef CONFIG_SYS_TEXT_BASE
246 #define CONFIG_SYS_TEXT_BASE		0xeff40000
247 #endif
248 
249 #ifndef CONFIG_RESET_VECTOR_ADDRESS
250 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
251 #endif
252 
253 #ifndef CONFIG_SYS_MONITOR_BASE
254 #ifdef CONFIG_SPL_BUILD
255 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
256 #else
257 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
258 #endif
259 #endif
260 
261 #define CONFIG_MP
262 
263 #define CONFIG_FSL_ELBC
264 #define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
265 #define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
266 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
267 #define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
268 #define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
269 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
270 
271 #define CONFIG_TSEC_ENET	/* tsec ethernet support */
272 #define CONFIG_ENV_OVERWRITE
273 
274 #define CONFIG_CMD_SATA
275 #define CONFIG_SATA_SIL
276 #define CONFIG_SYS_SATA_MAX_DEVICE	2
277 #define CONFIG_LIBATA
278 #define CONFIG_LBA48
279 
280 #if defined(CONFIG_TARGET_P2020RDB)
281 #define CONFIG_SYS_CLK_FREQ	100000000
282 #else
283 #define CONFIG_SYS_CLK_FREQ	66666666
284 #endif
285 #define CONFIG_DDR_CLK_FREQ	66666666
286 
287 #define CONFIG_HWCONFIG
288 /*
289  * These can be toggled for performance analysis, otherwise use default.
290  */
291 #define CONFIG_L2_CACHE
292 #define CONFIG_BTB
293 
294 #define CONFIG_BOARD_EARLY_INIT_F	/* Call board_pre_init */
295 
296 #define CONFIG_ENABLE_36BIT_PHYS
297 
298 #ifdef CONFIG_PHYS_64BIT
299 #define CONFIG_ADDR_MAP			1
300 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
301 #endif
302 
303 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
304 #define CONFIG_SYS_MEMTEST_END		0x1fffffff
305 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
306 
307 #define CONFIG_SYS_CCSRBAR		0xffe00000
308 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
309 
310 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
311        SPL code*/
312 #ifdef CONFIG_SPL_BUILD
313 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
314 #endif
315 
316 /* DDR Setup */
317 #define CONFIG_SYS_DDR_RAW_TIMING
318 #define CONFIG_DDR_SPD
319 #define CONFIG_SYS_SPD_BUS_NUM 1
320 #define SPD_EEPROM_ADDRESS 0x52
321 #undef CONFIG_FSL_DDR_INTERACTIVE
322 
323 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
324 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
325 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
326 #else
327 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_1G
328 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
329 #endif
330 #define CONFIG_SYS_SDRAM_SIZE		(1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
331 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
332 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
333 
334 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
335 
336 /* Default settings for DDR3 */
337 #ifndef CONFIG_TARGET_P2020RDB
338 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
339 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
340 #define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
341 #define CONFIG_SYS_DDR_CS1_BNDS		0x0040007f
342 #define CONFIG_SYS_DDR_CS1_CONFIG	0x80014302
343 #define CONFIG_SYS_DDR_CS1_CONFIG_2	0x00000000
344 
345 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
346 #define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
347 #define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
348 #define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
349 
350 #define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
351 #define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8655A608
352 #define CONFIG_SYS_DDR_SR_CNTR		0x00000000
353 #define CONFIG_SYS_DDR_RCW_1		0x00000000
354 #define CONFIG_SYS_DDR_RCW_2		0x00000000
355 #define CONFIG_SYS_DDR_CONTROL		0xC70C0000	/* Type = DDR3	*/
356 #define CONFIG_SYS_DDR_CONTROL_2	0x04401050
357 #define CONFIG_SYS_DDR_TIMING_4		0x00220001
358 #define CONFIG_SYS_DDR_TIMING_5		0x03402400
359 
360 #define CONFIG_SYS_DDR_TIMING_3		0x00020000
361 #define CONFIG_SYS_DDR_TIMING_0		0x00330004
362 #define CONFIG_SYS_DDR_TIMING_1		0x6f6B4846
363 #define CONFIG_SYS_DDR_TIMING_2		0x0FA8C8CF
364 #define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
365 #define CONFIG_SYS_DDR_MODE_1		0x40461520
366 #define CONFIG_SYS_DDR_MODE_2		0x8000c000
367 #define CONFIG_SYS_DDR_INTERVAL		0x0C300000
368 #endif
369 
370 #undef CONFIG_CLOCKS_IN_MHZ
371 
372 /*
373  * Memory map
374  *
375  * 0x0000_0000 0x7fff_ffff	DDR		Up to 2GB cacheable
376  * 0x8000_0000 0xdfff_ffff	PCI Express Mem	1.5G non-cacheable(PCIe * 3)
377  * 0xec00_0000 0xefff_ffff	NOR flash	Up to 64M non-cacheable	CS0/1
378  * 0xf8f8_0000 0xf8ff_ffff	L2 SRAM		Up to 512K cacheable
379  *   (early boot only)
380  * 0xff80_0000 0xff80_7fff	NAND flash	32K non-cacheable	CS1/0
381  * 0xff98_0000 0xff98_ffff	PMC		64K non-cacheable	CS2
382  * 0xffa0_0000 0xffaf_ffff	CPLD		1M non-cacheable	CS3
383  * 0xffb0_0000 0xffbf_ffff	VSC7385 switch  1M non-cacheable	CS2
384  * 0xffc0_0000 0xffc3_ffff	PCI IO range	256k non-cacheable
385  * 0xffd0_0000 0xffd0_3fff	L1 for stack	16K cacheable
386  * 0xffe0_0000 0xffef_ffff	CCSR		1M non-cacheable
387  */
388 
389 /*
390  * Local Bus Definitions
391  */
392 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
393 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
394 #define CONFIG_SYS_FLASH_BASE		0xec000000
395 #elif defined(CONFIG_TARGET_P1020UTM)
396 #define CONFIG_SYS_MAX_FLASH_SECT	256	/* 32M */
397 #define CONFIG_SYS_FLASH_BASE		0xee000000
398 #else
399 #define CONFIG_SYS_MAX_FLASH_SECT	128	/* 16M */
400 #define CONFIG_SYS_FLASH_BASE		0xef000000
401 #endif
402 
403 #ifdef CONFIG_PHYS_64BIT
404 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
405 #else
406 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
407 #endif
408 
409 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
410 	| BR_PS_16 | BR_V)
411 
412 #define CONFIG_FLASH_OR_PRELIM	0xfc000ff7
413 
414 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
415 #define CONFIG_SYS_FLASH_QUIET_TEST
416 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
417 
418 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
419 
420 #undef CONFIG_SYS_FLASH_CHECKSUM
421 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
422 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
423 
424 #define CONFIG_FLASH_CFI_DRIVER
425 #define CONFIG_SYS_FLASH_CFI
426 #define CONFIG_SYS_FLASH_EMPTY_INFO
427 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
428 
429 /* Nand Flash */
430 #ifdef CONFIG_NAND_FSL_ELBC
431 #define CONFIG_SYS_NAND_BASE		0xff800000
432 #ifdef CONFIG_PHYS_64BIT
433 #define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
434 #else
435 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
436 #endif
437 
438 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
439 #define CONFIG_SYS_MAX_NAND_DEVICE	1
440 #define CONFIG_CMD_NAND
441 #if defined(CONFIG_TARGET_P1020RDB_PD)
442 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
443 #else
444 #define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
445 #endif
446 
447 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
448 	| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
449 	| BR_PS_8	/* Port Size = 8 bit */ \
450 	| BR_MS_FCM	/* MSEL = FCM */ \
451 	| BR_V)	/* valid */
452 #if defined(CONFIG_TARGET_P1020RDB_PD)
453 #define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB \
454 	| OR_FCM_PGS	/* Large Page*/ \
455 	| OR_FCM_CSCT \
456 	| OR_FCM_CST \
457 	| OR_FCM_CHT \
458 	| OR_FCM_SCY_1 \
459 	| OR_FCM_TRLX \
460 	| OR_FCM_EHTR)
461 #else
462 #define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB	/* small page */ \
463 	| OR_FCM_CSCT \
464 	| OR_FCM_CST \
465 	| OR_FCM_CHT \
466 	| OR_FCM_SCY_1 \
467 	| OR_FCM_TRLX \
468 	| OR_FCM_EHTR)
469 #endif
470 #endif /* CONFIG_NAND_FSL_ELBC */
471 
472 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
473 
474 #define CONFIG_SYS_INIT_RAM_LOCK
475 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* stack in RAM */
476 #ifdef CONFIG_PHYS_64BIT
477 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
478 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
479 /* The assembler doesn't like typecast */
480 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
481 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
482 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
483 #else
484 /* Initial L1 address */
485 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
486 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
487 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
488 #endif
489 /* Size of used area in RAM */
490 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
491 
492 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
493 					GENERATED_GBL_DATA_SIZE)
494 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
495 
496 #define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
497 #define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)/* Reserved for malloc */
498 
499 #define CONFIG_SYS_CPLD_BASE	0xffa00000
500 #ifdef CONFIG_PHYS_64BIT
501 #define CONFIG_SYS_CPLD_BASE_PHYS	0xfffa00000ull
502 #else
503 #define CONFIG_SYS_CPLD_BASE_PHYS	CONFIG_SYS_CPLD_BASE
504 #endif
505 /* CPLD config size: 1Mb */
506 #define CONFIG_CPLD_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
507 					BR_PS_8 | BR_V)
508 #define CONFIG_CPLD_OR_PRELIM	(0xfff009f7)
509 
510 #define CONFIG_SYS_PMC_BASE	0xff980000
511 #define CONFIG_SYS_PMC_BASE_PHYS	CONFIG_SYS_PMC_BASE
512 #define CONFIG_PMC_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
513 					BR_PS_8 | BR_V)
514 #define CONFIG_PMC_OR_PRELIM	(OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
515 				 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
516 				 OR_GPCM_EAD)
517 
518 #ifdef CONFIG_NAND
519 #define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
520 #define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
521 #define CONFIG_SYS_BR1_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
522 #define CONFIG_SYS_OR1_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
523 #else
524 #define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
525 #define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
526 #ifdef CONFIG_NAND_FSL_ELBC
527 #define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
528 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
529 #endif
530 #endif
531 #define CONFIG_SYS_BR3_PRELIM	CONFIG_CPLD_BR_PRELIM	/* CPLD Base Address */
532 #define CONFIG_SYS_OR3_PRELIM	CONFIG_CPLD_OR_PRELIM	/* CPLD Options */
533 
534 /* Vsc7385 switch */
535 #ifdef CONFIG_VSC7385_ENET
536 #define CONFIG_SYS_VSC7385_BASE		0xffb00000
537 
538 #ifdef CONFIG_PHYS_64BIT
539 #define CONFIG_SYS_VSC7385_BASE_PHYS	0xfffb00000ull
540 #else
541 #define CONFIG_SYS_VSC7385_BASE_PHYS	CONFIG_SYS_VSC7385_BASE
542 #endif
543 
544 #define CONFIG_SYS_VSC7385_BR_PRELIM	\
545 	(BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
546 #define CONFIG_SYS_VSC7385_OR_PRELIM	(OR_AM_128KB | OR_GPCM_CSNT | \
547 			OR_GPCM_XACS |  OR_GPCM_SCY_15 | OR_GPCM_SETA | \
548 			OR_GPCM_TRLX |  OR_GPCM_EHTR | OR_GPCM_EAD)
549 
550 #define CONFIG_SYS_BR2_PRELIM	CONFIG_SYS_VSC7385_BR_PRELIM
551 #define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_VSC7385_OR_PRELIM
552 
553 /* The size of the VSC7385 firmware image */
554 #define CONFIG_VSC7385_IMAGE_SIZE	8192
555 #endif
556 
557 /*
558  * Config the L2 Cache as L2 SRAM
559 */
560 #if defined(CONFIG_SPL_BUILD)
561 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
562 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
563 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
564 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
565 #define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
566 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
567 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
568 #define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
569 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
570 #if defined(CONFIG_TARGET_P2020RDB)
571 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(364 << 10)
572 #else
573 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(108 << 10)
574 #endif
575 #elif defined(CONFIG_NAND)
576 #ifdef CONFIG_TPL_BUILD
577 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
578 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
579 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
580 #define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
581 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
582 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
583 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
584 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
585 #else
586 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
587 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
588 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
589 #define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x2000)
590 #define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
591 #endif /* CONFIG_TPL_BUILD */
592 #endif
593 #endif
594 
595 /* Serial Port - controlled on board with jumper J8
596  * open - index 2
597  * shorted - index 1
598  */
599 #define CONFIG_CONS_INDEX		1
600 #undef CONFIG_SERIAL_SOFTWARE_FIFO
601 #define CONFIG_SYS_NS16550_SERIAL
602 #define CONFIG_SYS_NS16550_REG_SIZE	1
603 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
604 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
605 #define CONFIG_NS16550_MIN_FUNCTIONS
606 #endif
607 
608 #define CONFIG_SYS_BAUDRATE_TABLE	\
609 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
610 
611 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
612 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
613 
614 /* I2C */
615 #define CONFIG_SYS_I2C
616 #define CONFIG_SYS_I2C_FSL
617 #define CONFIG_SYS_FSL_I2C_SPEED	400000
618 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
619 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
620 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
621 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
622 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
623 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
624 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
625 #define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash bank */
626 
627 /*
628  * I2C2 EEPROM
629  */
630 #undef CONFIG_ID_EEPROM
631 
632 #define CONFIG_RTC_PT7C4338
633 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
634 #define CONFIG_SYS_I2C_PCA9557_ADDR	0x18
635 
636 /* enable read and write access to EEPROM */
637 #define CONFIG_CMD_EEPROM
638 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
639 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
640 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
641 
642 /*
643  * eSPI - Enhanced SPI
644  */
645 #define CONFIG_HARD_SPI
646 
647 #if defined(CONFIG_SPI_FLASH)
648 #define CONFIG_SF_DEFAULT_SPEED	10000000
649 #define CONFIG_SF_DEFAULT_MODE	0
650 #endif
651 
652 #if defined(CONFIG_PCI)
653 /*
654  * General PCI
655  * Memory space is mapped 1-1, but I/O space must start from 0.
656  */
657 
658 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
659 #define CONFIG_SYS_PCIE2_NAME		"PCIe SLOT"
660 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
661 #ifdef CONFIG_PHYS_64BIT
662 #define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
663 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
664 #else
665 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
666 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
667 #endif
668 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
669 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
670 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
671 #ifdef CONFIG_PHYS_64BIT
672 #define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
673 #else
674 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
675 #endif
676 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
677 
678 /* controller 1, Slot 2, tgtid 1, Base address a000 */
679 #define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
680 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
681 #ifdef CONFIG_PHYS_64BIT
682 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
683 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
684 #else
685 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
686 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
687 #endif
688 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
689 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
690 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
691 #ifdef CONFIG_PHYS_64BIT
692 #define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
693 #else
694 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
695 #endif
696 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
697 
698 #define CONFIG_CMD_PCI
699 
700 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
701 #define CONFIG_DOS_PARTITION
702 #endif /* CONFIG_PCI */
703 
704 #if defined(CONFIG_TSEC_ENET)
705 #define CONFIG_MII		/* MII PHY management */
706 #define CONFIG_TSEC1
707 #define CONFIG_TSEC1_NAME	"eTSEC1"
708 #define CONFIG_TSEC2
709 #define CONFIG_TSEC2_NAME	"eTSEC2"
710 #define CONFIG_TSEC3
711 #define CONFIG_TSEC3_NAME	"eTSEC3"
712 
713 #define TSEC1_PHY_ADDR	2
714 #define TSEC2_PHY_ADDR	0
715 #define TSEC3_PHY_ADDR	1
716 
717 #define TSEC1_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
718 #define TSEC2_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
719 #define TSEC3_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
720 
721 #define TSEC1_PHYIDX	0
722 #define TSEC2_PHYIDX	0
723 #define TSEC3_PHYIDX	0
724 
725 #define CONFIG_ETHPRIME	"eTSEC1"
726 
727 #define CONFIG_PHY_GIGE	1	/* Include GbE speed/duplex detection */
728 
729 #define CONFIG_HAS_ETH0
730 #define CONFIG_HAS_ETH1
731 #define CONFIG_HAS_ETH2
732 #endif /* CONFIG_TSEC_ENET */
733 
734 #ifdef CONFIG_QE
735 /* QE microcode/firmware address */
736 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
737 #define CONFIG_SYS_QE_FW_ADDR	0xefec0000
738 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
739 #endif /* CONFIG_QE */
740 
741 #ifdef CONFIG_TARGET_P1025RDB
742 /*
743  * QE UEC ethernet configuration
744  */
745 #define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
746 
747 #undef CONFIG_UEC_ETH
748 #define CONFIG_PHY_MODE_NEED_CHANGE
749 
750 #define CONFIG_UEC_ETH1	/* ETH1 */
751 #define CONFIG_HAS_ETH0
752 
753 #ifdef CONFIG_UEC_ETH1
754 #define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
755 #define CONFIG_SYS_UEC1_RX_CLK	QE_CLK12 /* CLK12 for MII */
756 #define CONFIG_SYS_UEC1_TX_CLK	QE_CLK9 /* CLK9 for MII */
757 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
758 #define CONFIG_SYS_UEC1_PHY_ADDR	0x0	/* 0x0 for MII */
759 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
760 #define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
761 #endif /* CONFIG_UEC_ETH1 */
762 
763 #define CONFIG_UEC_ETH5	/* ETH5 */
764 #define CONFIG_HAS_ETH1
765 
766 #ifdef CONFIG_UEC_ETH5
767 #define CONFIG_SYS_UEC5_UCC_NUM	4	/* UCC5 */
768 #define CONFIG_SYS_UEC5_RX_CLK	QE_CLK_NONE
769 #define CONFIG_SYS_UEC5_TX_CLK	QE_CLK13 /* CLK 13 for RMII */
770 #define CONFIG_SYS_UEC5_ETH_TYPE	FAST_ETH
771 #define CONFIG_SYS_UEC5_PHY_ADDR	0x3	/* 0x3 for RMII */
772 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
773 #define CONFIG_SYS_UEC5_INTERFACE_SPEED	100
774 #endif /* CONFIG_UEC_ETH5 */
775 #endif /* CONFIG_TARGET_P1025RDB */
776 
777 /*
778  * Environment
779  */
780 #ifdef CONFIG_SPIFLASH
781 #define CONFIG_ENV_IS_IN_SPI_FLASH
782 #define CONFIG_ENV_SPI_BUS	0
783 #define CONFIG_ENV_SPI_CS	0
784 #define CONFIG_ENV_SPI_MAX_HZ	10000000
785 #define CONFIG_ENV_SPI_MODE	0
786 #define CONFIG_ENV_SIZE		0x2000	/* 8KB */
787 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
788 #define CONFIG_ENV_SECT_SIZE	0x10000
789 #elif defined(CONFIG_SDCARD)
790 #define CONFIG_ENV_IS_IN_MMC
791 #define CONFIG_FSL_FIXED_MMC_LOCATION
792 #define CONFIG_ENV_SIZE		0x2000
793 #define CONFIG_SYS_MMC_ENV_DEV	0
794 #elif defined(CONFIG_NAND)
795 #ifdef CONFIG_TPL_BUILD
796 #define CONFIG_ENV_SIZE		0x2000
797 #define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
798 #else
799 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
800 #endif
801 #define CONFIG_ENV_IS_IN_NAND
802 #define CONFIG_ENV_OFFSET	(1024 * 1024)
803 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
804 #elif defined(CONFIG_SYS_RAMBOOT)
805 #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
806 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
807 #define CONFIG_ENV_SIZE		0x2000
808 #else
809 #define CONFIG_ENV_IS_IN_FLASH
810 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
811 #define CONFIG_ENV_SIZE		0x2000
812 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
813 #endif
814 
815 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
816 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
817 
818 /*
819  * Command line configuration.
820  */
821 #define CONFIG_CMD_IRQ
822 #define CONFIG_CMD_DATE
823 #define CONFIG_CMD_REGINFO
824 
825 /*
826  * USB
827  */
828 #define CONFIG_HAS_FSL_DR_USB
829 
830 #if defined(CONFIG_HAS_FSL_DR_USB)
831 #define CONFIG_USB_EHCI
832 
833 #ifdef CONFIG_USB_EHCI
834 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
835 #define CONFIG_USB_EHCI_FSL
836 #endif
837 #endif
838 
839 #if defined(CONFIG_TARGET_P1020RDB_PD)
840 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
841 #endif
842 
843 #ifdef CONFIG_MMC
844 #define CONFIG_FSL_ESDHC
845 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
846 #define CONFIG_GENERIC_MMC
847 #endif
848 
849 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
850 		 || defined(CONFIG_FSL_SATA)
851 #define CONFIG_DOS_PARTITION
852 #endif
853 
854 #undef CONFIG_WATCHDOG	/* watchdog disabled */
855 
856 /*
857  * Miscellaneous configurable options
858  */
859 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
860 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
861 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
862 #if defined(CONFIG_CMD_KGDB)
863 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
864 #else
865 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
866 #endif
867 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
868 	/* Print Buffer Size */
869 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
870 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
871 
872 /*
873  * For booting Linux, the board info and command line data
874  * have to be in the first 64 MB of memory, since this is
875  * the maximum mapped by the Linux kernel during initialization.
876  */
877 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
878 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
879 
880 #if defined(CONFIG_CMD_KGDB)
881 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
882 #endif
883 
884 /*
885  * Environment Configuration
886  */
887 #define CONFIG_HOSTNAME		unknown
888 #define CONFIG_ROOTPATH		"/opt/nfsroot"
889 #define CONFIG_BOOTFILE		"uImage"
890 #define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
891 
892 /* default location for tftp and bootm */
893 #define CONFIG_LOADADDR	1000000
894 
895 #define CONFIG_BOOTARGS	/* the boot command will set bootargs */
896 
897 #define CONFIG_BAUDRATE	115200
898 
899 #ifdef __SW_BOOT_NOR
900 #define __NOR_RST_CMD	\
901 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
902 i2c mw 18 3 __SW_BOOT_MASK 1; reset
903 #endif
904 #ifdef __SW_BOOT_SPI
905 #define __SPI_RST_CMD	\
906 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
907 i2c mw 18 3 __SW_BOOT_MASK 1; reset
908 #endif
909 #ifdef __SW_BOOT_SD
910 #define __SD_RST_CMD	\
911 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
912 i2c mw 18 3 __SW_BOOT_MASK 1; reset
913 #endif
914 #ifdef __SW_BOOT_NAND
915 #define __NAND_RST_CMD	\
916 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
917 i2c mw 18 3 __SW_BOOT_MASK 1; reset
918 #endif
919 #ifdef __SW_BOOT_PCIE
920 #define __PCIE_RST_CMD	\
921 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
922 i2c mw 18 3 __SW_BOOT_MASK 1; reset
923 #endif
924 
925 #define	CONFIG_EXTRA_ENV_SETTINGS	\
926 "netdev=eth0\0"	\
927 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
928 "loadaddr=1000000\0"	\
929 "bootfile=uImage\0"	\
930 "tftpflash=tftpboot $loadaddr $uboot; "	\
931 	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
932 	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
933 	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
934 	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
935 	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
936 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
937 "consoledev=ttyS0\0"	\
938 "ramdiskaddr=2000000\0"	\
939 "ramdiskfile=rootfs.ext2.gz.uboot\0"	\
940 "fdtaddr=1e00000\0"	\
941 "bdev=sda1\0" \
942 "jffs2nor=mtdblock3\0"	\
943 "norbootaddr=ef080000\0"	\
944 "norfdtaddr=ef040000\0"	\
945 "jffs2nand=mtdblock9\0"	\
946 "nandbootaddr=100000\0"	\
947 "nandfdtaddr=80000\0"		\
948 "ramdisk_size=120000\0"	\
949 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
950 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
951 __stringify(__NOR_RST_CMD)"\0" \
952 __stringify(__SPI_RST_CMD)"\0" \
953 __stringify(__SD_RST_CMD)"\0" \
954 __stringify(__NAND_RST_CMD)"\0" \
955 __stringify(__PCIE_RST_CMD)"\0"
956 
957 #define CONFIG_NFSBOOTCOMMAND	\
958 "setenv bootargs root=/dev/nfs rw "	\
959 "nfsroot=$serverip:$rootpath "	\
960 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
961 "console=$consoledev,$baudrate $othbootargs;" \
962 "tftp $loadaddr $bootfile;"	\
963 "tftp $fdtaddr $fdtfile;"	\
964 "bootm $loadaddr - $fdtaddr"
965 
966 #define CONFIG_HDBOOT	\
967 "setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
968 "console=$consoledev,$baudrate $othbootargs;" \
969 "usb start;"	\
970 "ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
971 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
972 "bootm $loadaddr - $fdtaddr"
973 
974 #define CONFIG_USB_FAT_BOOT	\
975 "setenv bootargs root=/dev/ram rw "	\
976 "console=$consoledev,$baudrate $othbootargs " \
977 "ramdisk_size=$ramdisk_size;"	\
978 "usb start;"	\
979 "fatload usb 0:2 $loadaddr $bootfile;"	\
980 "fatload usb 0:2 $fdtaddr $fdtfile;"	\
981 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
982 "bootm $loadaddr $ramdiskaddr $fdtaddr"
983 
984 #define CONFIG_USB_EXT2_BOOT	\
985 "setenv bootargs root=/dev/ram rw "	\
986 "console=$consoledev,$baudrate $othbootargs " \
987 "ramdisk_size=$ramdisk_size;"	\
988 "usb start;"	\
989 "ext2load usb 0:4 $loadaddr $bootfile;"	\
990 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
991 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
992 "bootm $loadaddr $ramdiskaddr $fdtaddr"
993 
994 #define CONFIG_NORBOOT	\
995 "setenv bootargs root=/dev/$jffs2nor rw "	\
996 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
997 "bootm $norbootaddr - $norfdtaddr"
998 
999 #define CONFIG_RAMBOOTCOMMAND	\
1000 "setenv bootargs root=/dev/ram rw "	\
1001 "console=$consoledev,$baudrate $othbootargs " \
1002 "ramdisk_size=$ramdisk_size;"	\
1003 "tftp $ramdiskaddr $ramdiskfile;"	\
1004 "tftp $loadaddr $bootfile;"	\
1005 "tftp $fdtaddr $fdtfile;"	\
1006 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1007 
1008 #define CONFIG_BOOTCOMMAND	CONFIG_HDBOOT
1009 
1010 #endif /* __CONFIG_H */
1011