1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_P1020MBG) 14 #define CONFIG_BOARDNAME "P1020MBG-PC" 15 #define CONFIG_P1020 16 #define CONFIG_VSC7385_ENET 17 #define CONFIG_SLIC 18 #define __SW_BOOT_MASK 0x03 19 #define __SW_BOOT_NOR 0xe4 20 #define __SW_BOOT_SD 0x54 21 #define CONFIG_SYS_L2_SIZE (256 << 10) 22 #endif 23 24 #if defined(CONFIG_P1020UTM) 25 #define CONFIG_BOARDNAME "P1020UTM-PC" 26 #define CONFIG_P1020 27 #define __SW_BOOT_MASK 0x03 28 #define __SW_BOOT_NOR 0xe0 29 #define __SW_BOOT_SD 0x50 30 #define CONFIG_SYS_L2_SIZE (256 << 10) 31 #endif 32 33 #if defined(CONFIG_P1020RDB_PC) 34 #define CONFIG_BOARDNAME "P1020RDB-PC" 35 #define CONFIG_NAND_FSL_ELBC 36 #define CONFIG_P1020 37 #define CONFIG_VSC7385_ENET 38 #define CONFIG_SLIC 39 #define __SW_BOOT_MASK 0x03 40 #define __SW_BOOT_NOR 0x5c 41 #define __SW_BOOT_SPI 0x1c 42 #define __SW_BOOT_SD 0x9c 43 #define __SW_BOOT_NAND 0xec 44 #define __SW_BOOT_PCIE 0x6c 45 #define CONFIG_SYS_L2_SIZE (256 << 10) 46 #endif 47 48 /* 49 * P1020RDB-PD board has user selectable switches for evaluating different 50 * frequency and boot options for the P1020 device. The table that 51 * follow describe the available options. The front six binary number was in 52 * accordance with SW3[1:6]. 53 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 54 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 55 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 56 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 57 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 58 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 59 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 60 */ 61 #if defined(CONFIG_P1020RDB_PD) 62 #define CONFIG_BOARDNAME "P1020RDB-PD" 63 #define CONFIG_NAND_FSL_ELBC 64 #define CONFIG_P1020 65 #define CONFIG_VSC7385_ENET 66 #define CONFIG_SLIC 67 #define __SW_BOOT_MASK 0x03 68 #define __SW_BOOT_NOR 0x64 69 #define __SW_BOOT_SPI 0x34 70 #define __SW_BOOT_SD 0x24 71 #define __SW_BOOT_NAND 0x44 72 #define __SW_BOOT_PCIE 0x74 73 #define CONFIG_SYS_L2_SIZE (256 << 10) 74 /* 75 * Dynamic MTD Partition support with mtdparts 76 */ 77 #define CONFIG_MTD_DEVICE 78 #define CONFIG_MTD_PARTITIONS 79 #define CONFIG_CMD_MTDPARTS 80 #define CONFIG_FLASH_CFI_MTD 81 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 82 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ 83 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" 84 #endif 85 86 #if defined(CONFIG_P1021RDB) 87 #define CONFIG_BOARDNAME "P1021RDB-PC" 88 #define CONFIG_NAND_FSL_ELBC 89 #define CONFIG_P1021 90 #define CONFIG_QE 91 #define CONFIG_VSC7385_ENET 92 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 93 addresses in the LBC */ 94 #define __SW_BOOT_MASK 0x03 95 #define __SW_BOOT_NOR 0x5c 96 #define __SW_BOOT_SPI 0x1c 97 #define __SW_BOOT_SD 0x9c 98 #define __SW_BOOT_NAND 0xec 99 #define __SW_BOOT_PCIE 0x6c 100 #define CONFIG_SYS_L2_SIZE (256 << 10) 101 /* 102 * Dynamic MTD Partition support with mtdparts 103 */ 104 #define CONFIG_MTD_DEVICE 105 #define CONFIG_MTD_PARTITIONS 106 #define CONFIG_CMD_MTDPARTS 107 #define CONFIG_FLASH_CFI_MTD 108 #ifdef CONFIG_PHYS_64BIT 109 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 110 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 111 "256k(dtb),4608k(kernel),9728k(fs)," \ 112 "256k(qe-ucode-firmware),1280k(u-boot)" 113 #else 114 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 115 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 116 "256k(dtb),4608k(kernel),9728k(fs)," \ 117 "256k(qe-ucode-firmware),1280k(u-boot)" 118 #endif 119 #endif 120 121 #if defined(CONFIG_P1024RDB) 122 #define CONFIG_BOARDNAME "P1024RDB" 123 #define CONFIG_NAND_FSL_ELBC 124 #define CONFIG_P1024 125 #define CONFIG_SLIC 126 #define __SW_BOOT_MASK 0xf3 127 #define __SW_BOOT_NOR 0x00 128 #define __SW_BOOT_SPI 0x08 129 #define __SW_BOOT_SD 0x04 130 #define __SW_BOOT_NAND 0x0c 131 #define CONFIG_SYS_L2_SIZE (256 << 10) 132 #endif 133 134 #if defined(CONFIG_P1025RDB) 135 #define CONFIG_BOARDNAME "P1025RDB" 136 #define CONFIG_NAND_FSL_ELBC 137 #define CONFIG_P1025 138 #define CONFIG_QE 139 #define CONFIG_SLIC 140 141 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 142 addresses in the LBC */ 143 #define __SW_BOOT_MASK 0xf3 144 #define __SW_BOOT_NOR 0x00 145 #define __SW_BOOT_SPI 0x08 146 #define __SW_BOOT_SD 0x04 147 #define __SW_BOOT_NAND 0x0c 148 #define CONFIG_SYS_L2_SIZE (256 << 10) 149 #endif 150 151 #if defined(CONFIG_P2020RDB) 152 #define CONFIG_BOARDNAME "P2020RDB-PCA" 153 #define CONFIG_NAND_FSL_ELBC 154 #define CONFIG_P2020 155 #define CONFIG_VSC7385_ENET 156 #define __SW_BOOT_MASK 0x03 157 #define __SW_BOOT_NOR 0xc8 158 #define __SW_BOOT_SPI 0x28 159 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 160 #define __SW_BOOT_NAND 0xe8 161 #define __SW_BOOT_PCIE 0xa8 162 #define CONFIG_SYS_L2_SIZE (512 << 10) 163 /* 164 * Dynamic MTD Partition support with mtdparts 165 */ 166 #define CONFIG_MTD_DEVICE 167 #define CONFIG_MTD_PARTITIONS 168 #define CONFIG_CMD_MTDPARTS 169 #define CONFIG_FLASH_CFI_MTD 170 #ifdef CONFIG_PHYS_64BIT 171 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 172 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 173 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 174 #else 175 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 176 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 177 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 178 #endif 179 #endif 180 181 #ifdef CONFIG_SDCARD 182 #define CONFIG_SPL_MMC_MINIMAL 183 #define CONFIG_SPL_FLUSH_IMAGE 184 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 185 #define CONFIG_FSL_LAW /* Use common FSL init code */ 186 #define CONFIG_SYS_TEXT_BASE 0x11001000 187 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 188 #define CONFIG_SPL_PAD_TO 0x20000 189 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 190 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 191 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 192 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 193 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 194 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 195 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 196 #define CONFIG_SPL_MMC_BOOT 197 #ifdef CONFIG_SPL_BUILD 198 #define CONFIG_SPL_COMMON_INIT_DDR 199 #endif 200 #endif 201 202 #ifdef CONFIG_SPIFLASH 203 #define CONFIG_SPL_SPI_FLASH_MINIMAL 204 #define CONFIG_SPL_FLUSH_IMAGE 205 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 206 #define CONFIG_FSL_LAW /* Use common FSL init code */ 207 #define CONFIG_SYS_TEXT_BASE 0x11001000 208 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 209 #define CONFIG_SPL_PAD_TO 0x20000 210 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 211 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 212 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 213 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 214 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 215 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 216 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 217 #define CONFIG_SPL_SPI_BOOT 218 #ifdef CONFIG_SPL_BUILD 219 #define CONFIG_SPL_COMMON_INIT_DDR 220 #endif 221 #endif 222 223 #ifdef CONFIG_NAND 224 #ifdef CONFIG_TPL_BUILD 225 #define CONFIG_SPL_NAND_BOOT 226 #define CONFIG_SPL_FLUSH_IMAGE 227 #define CONFIG_SPL_NAND_INIT 228 #define CONFIG_SPL_COMMON_INIT_DDR 229 #define CONFIG_SPL_MAX_SIZE (128 << 10) 230 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 231 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 232 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 233 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 234 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 235 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 236 #elif defined(CONFIG_SPL_BUILD) 237 #define CONFIG_SPL_INIT_MINIMAL 238 #define CONFIG_SPL_FLUSH_IMAGE 239 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 240 #define CONFIG_SPL_TEXT_BASE 0xff800000 241 #define CONFIG_SPL_MAX_SIZE 4096 242 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 243 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 244 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 245 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 246 #endif /* not CONFIG_TPL_BUILD */ 247 248 #define CONFIG_SPL_PAD_TO 0x20000 249 #define CONFIG_TPL_PAD_TO 0x20000 250 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 251 #define CONFIG_SYS_TEXT_BASE 0x11001000 252 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 253 #endif 254 255 #ifndef CONFIG_SYS_TEXT_BASE 256 #define CONFIG_SYS_TEXT_BASE 0xeff40000 257 #endif 258 259 #ifndef CONFIG_RESET_VECTOR_ADDRESS 260 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 261 #endif 262 263 #ifndef CONFIG_SYS_MONITOR_BASE 264 #ifdef CONFIG_SPL_BUILD 265 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 266 #else 267 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 268 #endif 269 #endif 270 271 /* High Level Configuration Options */ 272 #define CONFIG_BOOKE 273 #define CONFIG_E500 274 275 #define CONFIG_MP 276 277 #define CONFIG_FSL_ELBC 278 #define CONFIG_PCI 279 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 280 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 281 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 282 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 283 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 284 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 285 286 #define CONFIG_FSL_LAW 287 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 288 #define CONFIG_ENV_OVERWRITE 289 290 #define CONFIG_CMD_SATA 291 #define CONFIG_SATA_SIL 292 #define CONFIG_SYS_SATA_MAX_DEVICE 2 293 #define CONFIG_LIBATA 294 #define CONFIG_LBA48 295 296 #if defined(CONFIG_P2020RDB) 297 #define CONFIG_SYS_CLK_FREQ 100000000 298 #else 299 #define CONFIG_SYS_CLK_FREQ 66666666 300 #endif 301 #define CONFIG_DDR_CLK_FREQ 66666666 302 303 #define CONFIG_HWCONFIG 304 /* 305 * These can be toggled for performance analysis, otherwise use default. 306 */ 307 #define CONFIG_L2_CACHE 308 #define CONFIG_BTB 309 310 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 311 312 #define CONFIG_ENABLE_36BIT_PHYS 313 314 #ifdef CONFIG_PHYS_64BIT 315 #define CONFIG_ADDR_MAP 1 316 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 317 #endif 318 319 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 320 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 321 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 322 323 #define CONFIG_SYS_CCSRBAR 0xffe00000 324 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 325 326 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 327 SPL code*/ 328 #ifdef CONFIG_SPL_BUILD 329 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 330 #endif 331 332 /* DDR Setup */ 333 #define CONFIG_SYS_FSL_DDR3 334 #define CONFIG_SYS_DDR_RAW_TIMING 335 #define CONFIG_DDR_SPD 336 #define CONFIG_SYS_SPD_BUS_NUM 1 337 #define SPD_EEPROM_ADDRESS 0x52 338 #undef CONFIG_FSL_DDR_INTERACTIVE 339 340 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 341 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 342 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 343 #else 344 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 345 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 346 #endif 347 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 348 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 349 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 350 351 #define CONFIG_NUM_DDR_CONTROLLERS 1 352 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 353 354 /* Default settings for DDR3 */ 355 #ifndef CONFIG_P2020RDB 356 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 357 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 358 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 359 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 360 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 361 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 362 363 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 364 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 365 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 366 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 367 368 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 369 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 370 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 371 #define CONFIG_SYS_DDR_RCW_1 0x00000000 372 #define CONFIG_SYS_DDR_RCW_2 0x00000000 373 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 374 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 375 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 376 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 377 378 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 379 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 380 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 381 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 382 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 383 #define CONFIG_SYS_DDR_MODE_1 0x40461520 384 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 385 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 386 #endif 387 388 #undef CONFIG_CLOCKS_IN_MHZ 389 390 /* 391 * Memory map 392 * 393 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 394 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 395 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 396 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 397 * (early boot only) 398 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 399 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 400 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 401 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 402 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 403 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 404 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 405 */ 406 407 /* 408 * Local Bus Definitions 409 */ 410 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 411 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 412 #define CONFIG_SYS_FLASH_BASE 0xec000000 413 #elif defined(CONFIG_P1020UTM) 414 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 415 #define CONFIG_SYS_FLASH_BASE 0xee000000 416 #else 417 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 418 #define CONFIG_SYS_FLASH_BASE 0xef000000 419 #endif 420 421 #ifdef CONFIG_PHYS_64BIT 422 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 423 #else 424 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 425 #endif 426 427 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 428 | BR_PS_16 | BR_V) 429 430 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 431 432 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 433 #define CONFIG_SYS_FLASH_QUIET_TEST 434 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 435 436 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 437 438 #undef CONFIG_SYS_FLASH_CHECKSUM 439 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 440 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 441 442 #define CONFIG_FLASH_CFI_DRIVER 443 #define CONFIG_SYS_FLASH_CFI 444 #define CONFIG_SYS_FLASH_EMPTY_INFO 445 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 446 447 /* Nand Flash */ 448 #ifdef CONFIG_NAND_FSL_ELBC 449 #define CONFIG_SYS_NAND_BASE 0xff800000 450 #ifdef CONFIG_PHYS_64BIT 451 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 452 #else 453 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 454 #endif 455 456 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 457 #define CONFIG_SYS_MAX_NAND_DEVICE 1 458 #define CONFIG_CMD_NAND 459 #if defined(CONFIG_P1020RDB_PD) 460 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 461 #else 462 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 463 #endif 464 465 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 466 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 467 | BR_PS_8 /* Port Size = 8 bit */ \ 468 | BR_MS_FCM /* MSEL = FCM */ \ 469 | BR_V) /* valid */ 470 #if defined(CONFIG_P1020RDB_PD) 471 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 472 | OR_FCM_PGS /* Large Page*/ \ 473 | OR_FCM_CSCT \ 474 | OR_FCM_CST \ 475 | OR_FCM_CHT \ 476 | OR_FCM_SCY_1 \ 477 | OR_FCM_TRLX \ 478 | OR_FCM_EHTR) 479 #else 480 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 481 | OR_FCM_CSCT \ 482 | OR_FCM_CST \ 483 | OR_FCM_CHT \ 484 | OR_FCM_SCY_1 \ 485 | OR_FCM_TRLX \ 486 | OR_FCM_EHTR) 487 #endif 488 #endif /* CONFIG_NAND_FSL_ELBC */ 489 490 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 491 492 #define CONFIG_SYS_INIT_RAM_LOCK 493 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 494 #ifdef CONFIG_PHYS_64BIT 495 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 496 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 497 /* The assembler doesn't like typecast */ 498 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 499 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 500 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 501 #else 502 /* Initial L1 address */ 503 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 504 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 505 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 506 #endif 507 /* Size of used area in RAM */ 508 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 509 510 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 511 GENERATED_GBL_DATA_SIZE) 512 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 513 514 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 515 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 516 517 #define CONFIG_SYS_CPLD_BASE 0xffa00000 518 #ifdef CONFIG_PHYS_64BIT 519 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 520 #else 521 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 522 #endif 523 /* CPLD config size: 1Mb */ 524 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 525 BR_PS_8 | BR_V) 526 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 527 528 #define CONFIG_SYS_PMC_BASE 0xff980000 529 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 530 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 531 BR_PS_8 | BR_V) 532 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 533 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 534 OR_GPCM_EAD) 535 536 #ifdef CONFIG_NAND 537 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 538 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 539 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 540 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 541 #else 542 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 543 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 544 #ifdef CONFIG_NAND_FSL_ELBC 545 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 546 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 547 #endif 548 #endif 549 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 550 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 551 552 /* Vsc7385 switch */ 553 #ifdef CONFIG_VSC7385_ENET 554 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 555 556 #ifdef CONFIG_PHYS_64BIT 557 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 558 #else 559 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 560 #endif 561 562 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 563 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 564 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 565 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 566 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 567 568 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 569 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 570 571 /* The size of the VSC7385 firmware image */ 572 #define CONFIG_VSC7385_IMAGE_SIZE 8192 573 #endif 574 575 /* 576 * Config the L2 Cache as L2 SRAM 577 */ 578 #if defined(CONFIG_SPL_BUILD) 579 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 580 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 581 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 582 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 583 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 584 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 585 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 586 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 587 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 588 #if defined(CONFIG_P2020RDB) 589 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 590 #else 591 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 592 #endif 593 #elif defined(CONFIG_NAND) 594 #ifdef CONFIG_TPL_BUILD 595 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 596 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 597 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 598 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 599 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 600 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 601 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 602 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 603 #else 604 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 605 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 606 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 607 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 608 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 609 #endif /* CONFIG_TPL_BUILD */ 610 #endif 611 #endif 612 613 /* Serial Port - controlled on board with jumper J8 614 * open - index 2 615 * shorted - index 1 616 */ 617 #define CONFIG_CONS_INDEX 1 618 #undef CONFIG_SERIAL_SOFTWARE_FIFO 619 #define CONFIG_SYS_NS16550_SERIAL 620 #define CONFIG_SYS_NS16550_REG_SIZE 1 621 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 622 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 623 #define CONFIG_NS16550_MIN_FUNCTIONS 624 #endif 625 626 #define CONFIG_SYS_BAUDRATE_TABLE \ 627 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 628 629 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 630 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 631 632 /* I2C */ 633 #define CONFIG_SYS_I2C 634 #define CONFIG_SYS_I2C_FSL 635 #define CONFIG_SYS_FSL_I2C_SPEED 400000 636 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 637 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 638 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 639 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 640 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 641 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 642 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 643 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 644 645 /* 646 * I2C2 EEPROM 647 */ 648 #undef CONFIG_ID_EEPROM 649 650 #define CONFIG_RTC_PT7C4338 651 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 652 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 653 654 /* enable read and write access to EEPROM */ 655 #define CONFIG_CMD_EEPROM 656 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 657 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 658 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 659 660 /* 661 * eSPI - Enhanced SPI 662 */ 663 #define CONFIG_HARD_SPI 664 665 #if defined(CONFIG_SPI_FLASH) 666 #define CONFIG_SF_DEFAULT_SPEED 10000000 667 #define CONFIG_SF_DEFAULT_MODE 0 668 #endif 669 670 #if defined(CONFIG_PCI) 671 /* 672 * General PCI 673 * Memory space is mapped 1-1, but I/O space must start from 0. 674 */ 675 676 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 677 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 678 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 679 #ifdef CONFIG_PHYS_64BIT 680 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 681 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 682 #else 683 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 684 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 685 #endif 686 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 687 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 688 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 689 #ifdef CONFIG_PHYS_64BIT 690 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 691 #else 692 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 693 #endif 694 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 695 696 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 697 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 698 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 699 #ifdef CONFIG_PHYS_64BIT 700 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 701 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 702 #else 703 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 704 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 705 #endif 706 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 707 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 708 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 709 #ifdef CONFIG_PHYS_64BIT 710 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 711 #else 712 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 713 #endif 714 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 715 716 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 717 #define CONFIG_CMD_PCI 718 719 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 720 #define CONFIG_DOS_PARTITION 721 #endif /* CONFIG_PCI */ 722 723 #if defined(CONFIG_TSEC_ENET) 724 #define CONFIG_MII /* MII PHY management */ 725 #define CONFIG_TSEC1 726 #define CONFIG_TSEC1_NAME "eTSEC1" 727 #define CONFIG_TSEC2 728 #define CONFIG_TSEC2_NAME "eTSEC2" 729 #define CONFIG_TSEC3 730 #define CONFIG_TSEC3_NAME "eTSEC3" 731 732 #define TSEC1_PHY_ADDR 2 733 #define TSEC2_PHY_ADDR 0 734 #define TSEC3_PHY_ADDR 1 735 736 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 737 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 738 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 739 740 #define TSEC1_PHYIDX 0 741 #define TSEC2_PHYIDX 0 742 #define TSEC3_PHYIDX 0 743 744 #define CONFIG_ETHPRIME "eTSEC1" 745 746 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 747 748 #define CONFIG_HAS_ETH0 749 #define CONFIG_HAS_ETH1 750 #define CONFIG_HAS_ETH2 751 #endif /* CONFIG_TSEC_ENET */ 752 753 #ifdef CONFIG_QE 754 /* QE microcode/firmware address */ 755 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 756 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 757 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 758 #endif /* CONFIG_QE */ 759 760 #ifdef CONFIG_P1025RDB 761 /* 762 * QE UEC ethernet configuration 763 */ 764 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 765 766 #undef CONFIG_UEC_ETH 767 #define CONFIG_PHY_MODE_NEED_CHANGE 768 769 #define CONFIG_UEC_ETH1 /* ETH1 */ 770 #define CONFIG_HAS_ETH0 771 772 #ifdef CONFIG_UEC_ETH1 773 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 774 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 775 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 776 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 777 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 778 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 779 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 780 #endif /* CONFIG_UEC_ETH1 */ 781 782 #define CONFIG_UEC_ETH5 /* ETH5 */ 783 #define CONFIG_HAS_ETH1 784 785 #ifdef CONFIG_UEC_ETH5 786 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 787 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 788 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 789 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 790 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 791 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 792 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 793 #endif /* CONFIG_UEC_ETH5 */ 794 #endif /* CONFIG_P1025RDB */ 795 796 /* 797 * Environment 798 */ 799 #ifdef CONFIG_SPIFLASH 800 #define CONFIG_ENV_IS_IN_SPI_FLASH 801 #define CONFIG_ENV_SPI_BUS 0 802 #define CONFIG_ENV_SPI_CS 0 803 #define CONFIG_ENV_SPI_MAX_HZ 10000000 804 #define CONFIG_ENV_SPI_MODE 0 805 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 806 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 807 #define CONFIG_ENV_SECT_SIZE 0x10000 808 #elif defined(CONFIG_SDCARD) 809 #define CONFIG_ENV_IS_IN_MMC 810 #define CONFIG_FSL_FIXED_MMC_LOCATION 811 #define CONFIG_ENV_SIZE 0x2000 812 #define CONFIG_SYS_MMC_ENV_DEV 0 813 #elif defined(CONFIG_NAND) 814 #ifdef CONFIG_TPL_BUILD 815 #define CONFIG_ENV_SIZE 0x2000 816 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 817 #else 818 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 819 #endif 820 #define CONFIG_ENV_IS_IN_NAND 821 #define CONFIG_ENV_OFFSET (1024 * 1024) 822 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 823 #elif defined(CONFIG_SYS_RAMBOOT) 824 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 825 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 826 #define CONFIG_ENV_SIZE 0x2000 827 #else 828 #define CONFIG_ENV_IS_IN_FLASH 829 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 830 #define CONFIG_ENV_SIZE 0x2000 831 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 832 #endif 833 834 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 835 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 836 837 /* 838 * Command line configuration. 839 */ 840 #define CONFIG_CMD_IRQ 841 #define CONFIG_CMD_DATE 842 #define CONFIG_CMD_REGINFO 843 844 /* 845 * USB 846 */ 847 #define CONFIG_HAS_FSL_DR_USB 848 849 #if defined(CONFIG_HAS_FSL_DR_USB) 850 #define CONFIG_USB_EHCI 851 852 #ifdef CONFIG_USB_EHCI 853 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 854 #define CONFIG_USB_EHCI_FSL 855 #endif 856 #endif 857 858 #if defined(CONFIG_P1020RDB_PD) 859 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 860 #endif 861 862 #define CONFIG_MMC 863 864 #ifdef CONFIG_MMC 865 #define CONFIG_FSL_ESDHC 866 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 867 #define CONFIG_GENERIC_MMC 868 #endif 869 870 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 871 || defined(CONFIG_FSL_SATA) 872 #define CONFIG_DOS_PARTITION 873 #endif 874 875 #undef CONFIG_WATCHDOG /* watchdog disabled */ 876 877 /* 878 * Miscellaneous configurable options 879 */ 880 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 881 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 882 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 883 #if defined(CONFIG_CMD_KGDB) 884 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 885 #else 886 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 887 #endif 888 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 889 /* Print Buffer Size */ 890 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 891 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 892 893 /* 894 * For booting Linux, the board info and command line data 895 * have to be in the first 64 MB of memory, since this is 896 * the maximum mapped by the Linux kernel during initialization. 897 */ 898 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 899 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 900 901 #if defined(CONFIG_CMD_KGDB) 902 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 903 #endif 904 905 /* 906 * Environment Configuration 907 */ 908 #define CONFIG_HOSTNAME unknown 909 #define CONFIG_ROOTPATH "/opt/nfsroot" 910 #define CONFIG_BOOTFILE "uImage" 911 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 912 913 /* default location for tftp and bootm */ 914 #define CONFIG_LOADADDR 1000000 915 916 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 917 918 #define CONFIG_BAUDRATE 115200 919 920 #ifdef __SW_BOOT_NOR 921 #define __NOR_RST_CMD \ 922 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 923 i2c mw 18 3 __SW_BOOT_MASK 1; reset 924 #endif 925 #ifdef __SW_BOOT_SPI 926 #define __SPI_RST_CMD \ 927 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 928 i2c mw 18 3 __SW_BOOT_MASK 1; reset 929 #endif 930 #ifdef __SW_BOOT_SD 931 #define __SD_RST_CMD \ 932 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 933 i2c mw 18 3 __SW_BOOT_MASK 1; reset 934 #endif 935 #ifdef __SW_BOOT_NAND 936 #define __NAND_RST_CMD \ 937 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 938 i2c mw 18 3 __SW_BOOT_MASK 1; reset 939 #endif 940 #ifdef __SW_BOOT_PCIE 941 #define __PCIE_RST_CMD \ 942 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 943 i2c mw 18 3 __SW_BOOT_MASK 1; reset 944 #endif 945 946 #define CONFIG_EXTRA_ENV_SETTINGS \ 947 "netdev=eth0\0" \ 948 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 949 "loadaddr=1000000\0" \ 950 "bootfile=uImage\0" \ 951 "tftpflash=tftpboot $loadaddr $uboot; " \ 952 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 953 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 954 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 955 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 956 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 957 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 958 "consoledev=ttyS0\0" \ 959 "ramdiskaddr=2000000\0" \ 960 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 961 "fdtaddr=1e00000\0" \ 962 "bdev=sda1\0" \ 963 "jffs2nor=mtdblock3\0" \ 964 "norbootaddr=ef080000\0" \ 965 "norfdtaddr=ef040000\0" \ 966 "jffs2nand=mtdblock9\0" \ 967 "nandbootaddr=100000\0" \ 968 "nandfdtaddr=80000\0" \ 969 "ramdisk_size=120000\0" \ 970 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 971 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 972 __stringify(__NOR_RST_CMD)"\0" \ 973 __stringify(__SPI_RST_CMD)"\0" \ 974 __stringify(__SD_RST_CMD)"\0" \ 975 __stringify(__NAND_RST_CMD)"\0" \ 976 __stringify(__PCIE_RST_CMD)"\0" 977 978 #define CONFIG_NFSBOOTCOMMAND \ 979 "setenv bootargs root=/dev/nfs rw " \ 980 "nfsroot=$serverip:$rootpath " \ 981 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 982 "console=$consoledev,$baudrate $othbootargs;" \ 983 "tftp $loadaddr $bootfile;" \ 984 "tftp $fdtaddr $fdtfile;" \ 985 "bootm $loadaddr - $fdtaddr" 986 987 #define CONFIG_HDBOOT \ 988 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 989 "console=$consoledev,$baudrate $othbootargs;" \ 990 "usb start;" \ 991 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 992 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 993 "bootm $loadaddr - $fdtaddr" 994 995 #define CONFIG_USB_FAT_BOOT \ 996 "setenv bootargs root=/dev/ram rw " \ 997 "console=$consoledev,$baudrate $othbootargs " \ 998 "ramdisk_size=$ramdisk_size;" \ 999 "usb start;" \ 1000 "fatload usb 0:2 $loadaddr $bootfile;" \ 1001 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 1002 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 1003 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1004 1005 #define CONFIG_USB_EXT2_BOOT \ 1006 "setenv bootargs root=/dev/ram rw " \ 1007 "console=$consoledev,$baudrate $othbootargs " \ 1008 "ramdisk_size=$ramdisk_size;" \ 1009 "usb start;" \ 1010 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1011 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1012 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1013 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1014 1015 #define CONFIG_NORBOOT \ 1016 "setenv bootargs root=/dev/$jffs2nor rw " \ 1017 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1018 "bootm $norbootaddr - $norfdtaddr" 1019 1020 #define CONFIG_RAMBOOTCOMMAND \ 1021 "setenv bootargs root=/dev/ram rw " \ 1022 "console=$consoledev,$baudrate $othbootargs " \ 1023 "ramdisk_size=$ramdisk_size;" \ 1024 "tftp $ramdiskaddr $ramdiskfile;" \ 1025 "tftp $loadaddr $bootfile;" \ 1026 "tftp $fdtaddr $fdtfile;" \ 1027 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1028 1029 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1030 1031 #endif /* __CONFIG_H */ 1032