1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 #if defined(CONFIG_P1020MBG) 16 #define CONFIG_BOARDNAME "P1020MBG-PC" 17 #define CONFIG_P1020 18 #define CONFIG_VSC7385_ENET 19 #define CONFIG_SLIC 20 #define __SW_BOOT_MASK 0x03 21 #define __SW_BOOT_NOR 0xe4 22 #define __SW_BOOT_SD 0x54 23 #define CONFIG_SYS_L2_SIZE (256 << 10) 24 #endif 25 26 #if defined(CONFIG_P1020UTM) 27 #define CONFIG_BOARDNAME "P1020UTM-PC" 28 #define CONFIG_P1020 29 #define __SW_BOOT_MASK 0x03 30 #define __SW_BOOT_NOR 0xe0 31 #define __SW_BOOT_SD 0x50 32 #define CONFIG_SYS_L2_SIZE (256 << 10) 33 #endif 34 35 #if defined(CONFIG_P1020RDB_PC) 36 #define CONFIG_BOARDNAME "P1020RDB-PC" 37 #define CONFIG_NAND_FSL_ELBC 38 #define CONFIG_P1020 39 #define CONFIG_VSC7385_ENET 40 #define CONFIG_SLIC 41 #define __SW_BOOT_MASK 0x03 42 #define __SW_BOOT_NOR 0x5c 43 #define __SW_BOOT_SPI 0x1c 44 #define __SW_BOOT_SD 0x9c 45 #define __SW_BOOT_NAND 0xec 46 #define __SW_BOOT_PCIE 0x6c 47 #define CONFIG_SYS_L2_SIZE (256 << 10) 48 #endif 49 50 /* 51 * P1020RDB-PD board has user selectable switches for evaluating different 52 * frequency and boot options for the P1020 device. The table that 53 * follow describe the available options. The front six binary number was in 54 * accordance with SW3[1:6]. 55 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 56 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 57 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 58 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 59 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 60 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 61 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 62 */ 63 #if defined(CONFIG_P1020RDB_PD) 64 #define CONFIG_BOARDNAME "P1020RDB-PD" 65 #define CONFIG_NAND_FSL_ELBC 66 #define CONFIG_P1020 67 #define CONFIG_VSC7385_ENET 68 #define CONFIG_SLIC 69 #define __SW_BOOT_MASK 0x03 70 #define __SW_BOOT_NOR 0x64 71 #define __SW_BOOT_SPI 0x34 72 #define __SW_BOOT_SD 0x24 73 #define __SW_BOOT_NAND 0x44 74 #define __SW_BOOT_PCIE 0x74 75 #define CONFIG_SYS_L2_SIZE (256 << 10) 76 /* 77 * Dynamic MTD Partition support with mtdparts 78 */ 79 #define CONFIG_MTD_DEVICE 80 #define CONFIG_MTD_PARTITIONS 81 #define CONFIG_CMD_MTDPARTS 82 #define CONFIG_FLASH_CFI_MTD 83 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 84 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ 85 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" 86 #endif 87 88 #if defined(CONFIG_P1021RDB) 89 #define CONFIG_BOARDNAME "P1021RDB-PC" 90 #define CONFIG_NAND_FSL_ELBC 91 #define CONFIG_P1021 92 #define CONFIG_QE 93 #define CONFIG_VSC7385_ENET 94 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 95 addresses in the LBC */ 96 #define __SW_BOOT_MASK 0x03 97 #define __SW_BOOT_NOR 0x5c 98 #define __SW_BOOT_SPI 0x1c 99 #define __SW_BOOT_SD 0x9c 100 #define __SW_BOOT_NAND 0xec 101 #define __SW_BOOT_PCIE 0x6c 102 #define CONFIG_SYS_L2_SIZE (256 << 10) 103 /* 104 * Dynamic MTD Partition support with mtdparts 105 */ 106 #define CONFIG_MTD_DEVICE 107 #define CONFIG_MTD_PARTITIONS 108 #define CONFIG_CMD_MTDPARTS 109 #define CONFIG_FLASH_CFI_MTD 110 #ifdef CONFIG_PHYS_64BIT 111 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 112 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 113 "256k(dtb),4608k(kernel),9728k(fs)," \ 114 "256k(qe-ucode-firmware),1280k(u-boot)" 115 #else 116 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 117 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 118 "256k(dtb),4608k(kernel),9728k(fs)," \ 119 "256k(qe-ucode-firmware),1280k(u-boot)" 120 #endif 121 #endif 122 123 #if defined(CONFIG_P1024RDB) 124 #define CONFIG_BOARDNAME "P1024RDB" 125 #define CONFIG_NAND_FSL_ELBC 126 #define CONFIG_P1024 127 #define CONFIG_SLIC 128 #define __SW_BOOT_MASK 0xf3 129 #define __SW_BOOT_NOR 0x00 130 #define __SW_BOOT_SPI 0x08 131 #define __SW_BOOT_SD 0x04 132 #define __SW_BOOT_NAND 0x0c 133 #define CONFIG_SYS_L2_SIZE (256 << 10) 134 #endif 135 136 #if defined(CONFIG_P1025RDB) 137 #define CONFIG_BOARDNAME "P1025RDB" 138 #define CONFIG_NAND_FSL_ELBC 139 #define CONFIG_P1025 140 #define CONFIG_QE 141 #define CONFIG_SLIC 142 143 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 144 addresses in the LBC */ 145 #define __SW_BOOT_MASK 0xf3 146 #define __SW_BOOT_NOR 0x00 147 #define __SW_BOOT_SPI 0x08 148 #define __SW_BOOT_SD 0x04 149 #define __SW_BOOT_NAND 0x0c 150 #define CONFIG_SYS_L2_SIZE (256 << 10) 151 #endif 152 153 #if defined(CONFIG_P2020RDB) 154 #define CONFIG_BOARDNAME "P2020RDB-PCA" 155 #define CONFIG_NAND_FSL_ELBC 156 #define CONFIG_P2020 157 #define CONFIG_VSC7385_ENET 158 #define __SW_BOOT_MASK 0x03 159 #define __SW_BOOT_NOR 0xc8 160 #define __SW_BOOT_SPI 0x28 161 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 162 #define __SW_BOOT_NAND 0xe8 163 #define __SW_BOOT_PCIE 0xa8 164 #define CONFIG_SYS_L2_SIZE (512 << 10) 165 /* 166 * Dynamic MTD Partition support with mtdparts 167 */ 168 #define CONFIG_MTD_DEVICE 169 #define CONFIG_MTD_PARTITIONS 170 #define CONFIG_CMD_MTDPARTS 171 #define CONFIG_FLASH_CFI_MTD 172 #ifdef CONFIG_PHYS_64BIT 173 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 174 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 175 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 176 #else 177 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 178 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 179 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 180 #endif 181 #endif 182 183 #ifdef CONFIG_SDCARD 184 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 185 #define CONFIG_SPL_ENV_SUPPORT 186 #define CONFIG_SPL_SERIAL_SUPPORT 187 #define CONFIG_SPL_MMC_SUPPORT 188 #define CONFIG_SPL_MMC_MINIMAL 189 #define CONFIG_SPL_FLUSH_IMAGE 190 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 191 #define CONFIG_SPL_LIBGENERIC_SUPPORT 192 #define CONFIG_SPL_LIBCOMMON_SUPPORT 193 #define CONFIG_SPL_I2C_SUPPORT 194 #define CONFIG_FSL_LAW /* Use common FSL init code */ 195 #define CONFIG_SYS_TEXT_BASE 0x11001000 196 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 197 #define CONFIG_SPL_PAD_TO 0x20000 198 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 199 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 200 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 201 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 202 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 203 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 204 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 205 #define CONFIG_SPL_MMC_BOOT 206 #ifdef CONFIG_SPL_BUILD 207 #define CONFIG_SPL_COMMON_INIT_DDR 208 #endif 209 #endif 210 211 #ifdef CONFIG_SPIFLASH 212 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 213 #define CONFIG_SPL_ENV_SUPPORT 214 #define CONFIG_SPL_SERIAL_SUPPORT 215 #define CONFIG_SPL_SPI_SUPPORT 216 #define CONFIG_SPL_SPI_FLASH_SUPPORT 217 #define CONFIG_SPL_SPI_FLASH_MINIMAL 218 #define CONFIG_SPL_FLUSH_IMAGE 219 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 220 #define CONFIG_SPL_LIBGENERIC_SUPPORT 221 #define CONFIG_SPL_LIBCOMMON_SUPPORT 222 #define CONFIG_SPL_I2C_SUPPORT 223 #define CONFIG_FSL_LAW /* Use common FSL init code */ 224 #define CONFIG_SYS_TEXT_BASE 0x11001000 225 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 226 #define CONFIG_SPL_PAD_TO 0x20000 227 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 228 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 229 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 230 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 231 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 232 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 233 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 234 #define CONFIG_SPL_SPI_BOOT 235 #ifdef CONFIG_SPL_BUILD 236 #define CONFIG_SPL_COMMON_INIT_DDR 237 #endif 238 #endif 239 240 #ifdef CONFIG_NAND 241 #ifdef CONFIG_TPL_BUILD 242 #define CONFIG_SPL_NAND_BOOT 243 #define CONFIG_SPL_FLUSH_IMAGE 244 #define CONFIG_SPL_ENV_SUPPORT 245 #define CONFIG_SPL_NAND_INIT 246 #define CONFIG_SPL_SERIAL_SUPPORT 247 #define CONFIG_SPL_LIBGENERIC_SUPPORT 248 #define CONFIG_SPL_LIBCOMMON_SUPPORT 249 #define CONFIG_SPL_I2C_SUPPORT 250 #define CONFIG_SPL_NAND_SUPPORT 251 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 252 #define CONFIG_SPL_COMMON_INIT_DDR 253 #define CONFIG_SPL_MAX_SIZE (128 << 10) 254 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 255 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 256 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 257 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 258 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 259 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 260 #elif defined(CONFIG_SPL_BUILD) 261 #define CONFIG_SPL_INIT_MINIMAL 262 #define CONFIG_SPL_SERIAL_SUPPORT 263 #define CONFIG_SPL_NAND_SUPPORT 264 #define CONFIG_SPL_FLUSH_IMAGE 265 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 266 #define CONFIG_SPL_TEXT_BASE 0xff800000 267 #define CONFIG_SPL_MAX_SIZE 4096 268 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 269 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 270 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 271 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 272 #endif /* not CONFIG_TPL_BUILD */ 273 274 #define CONFIG_SPL_PAD_TO 0x20000 275 #define CONFIG_TPL_PAD_TO 0x20000 276 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 277 #define CONFIG_SYS_TEXT_BASE 0x11001000 278 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 279 #endif 280 281 #ifndef CONFIG_SYS_TEXT_BASE 282 #define CONFIG_SYS_TEXT_BASE 0xeff40000 283 #endif 284 285 #ifndef CONFIG_RESET_VECTOR_ADDRESS 286 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 287 #endif 288 289 #ifndef CONFIG_SYS_MONITOR_BASE 290 #ifdef CONFIG_SPL_BUILD 291 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 292 #else 293 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 294 #endif 295 #endif 296 297 /* High Level Configuration Options */ 298 #define CONFIG_BOOKE 299 #define CONFIG_E500 300 301 #define CONFIG_MP 302 303 #define CONFIG_FSL_ELBC 304 #define CONFIG_PCI 305 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 306 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 307 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 308 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 309 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 310 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 311 312 #define CONFIG_FSL_LAW 313 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 314 #define CONFIG_ENV_OVERWRITE 315 316 #define CONFIG_CMD_SATA 317 #define CONFIG_SATA_SIL 318 #define CONFIG_SYS_SATA_MAX_DEVICE 2 319 #define CONFIG_LIBATA 320 #define CONFIG_LBA48 321 322 #if defined(CONFIG_P2020RDB) 323 #define CONFIG_SYS_CLK_FREQ 100000000 324 #else 325 #define CONFIG_SYS_CLK_FREQ 66666666 326 #endif 327 #define CONFIG_DDR_CLK_FREQ 66666666 328 329 #define CONFIG_HWCONFIG 330 /* 331 * These can be toggled for performance analysis, otherwise use default. 332 */ 333 #define CONFIG_L2_CACHE 334 #define CONFIG_BTB 335 336 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 337 338 #define CONFIG_ENABLE_36BIT_PHYS 339 340 #ifdef CONFIG_PHYS_64BIT 341 #define CONFIG_ADDR_MAP 1 342 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 343 #endif 344 345 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 346 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 347 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 348 349 #define CONFIG_SYS_CCSRBAR 0xffe00000 350 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 351 352 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 353 SPL code*/ 354 #ifdef CONFIG_SPL_BUILD 355 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 356 #endif 357 358 /* DDR Setup */ 359 #define CONFIG_SYS_FSL_DDR3 360 #define CONFIG_SYS_DDR_RAW_TIMING 361 #define CONFIG_DDR_SPD 362 #define CONFIG_SYS_SPD_BUS_NUM 1 363 #define SPD_EEPROM_ADDRESS 0x52 364 #undef CONFIG_FSL_DDR_INTERACTIVE 365 366 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 367 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 368 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 369 #else 370 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 371 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 372 #endif 373 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 374 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 375 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 376 377 #define CONFIG_NUM_DDR_CONTROLLERS 1 378 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 379 380 /* Default settings for DDR3 */ 381 #ifndef CONFIG_P2020RDB 382 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 383 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 384 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 385 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 386 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 387 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 388 389 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 390 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 391 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 392 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 393 394 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 395 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 396 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 397 #define CONFIG_SYS_DDR_RCW_1 0x00000000 398 #define CONFIG_SYS_DDR_RCW_2 0x00000000 399 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 400 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 401 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 402 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 403 404 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 405 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 406 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 407 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 408 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 409 #define CONFIG_SYS_DDR_MODE_1 0x40461520 410 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 411 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 412 #endif 413 414 #undef CONFIG_CLOCKS_IN_MHZ 415 416 /* 417 * Memory map 418 * 419 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 420 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 421 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 422 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 423 * (early boot only) 424 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 425 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 426 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 427 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 428 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 429 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 430 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 431 */ 432 433 /* 434 * Local Bus Definitions 435 */ 436 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 437 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 438 #define CONFIG_SYS_FLASH_BASE 0xec000000 439 #elif defined(CONFIG_P1020UTM) 440 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 441 #define CONFIG_SYS_FLASH_BASE 0xee000000 442 #else 443 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 444 #define CONFIG_SYS_FLASH_BASE 0xef000000 445 #endif 446 447 #ifdef CONFIG_PHYS_64BIT 448 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 449 #else 450 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 451 #endif 452 453 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 454 | BR_PS_16 | BR_V) 455 456 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 457 458 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 459 #define CONFIG_SYS_FLASH_QUIET_TEST 460 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 461 462 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 463 464 #undef CONFIG_SYS_FLASH_CHECKSUM 465 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 466 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 467 468 #define CONFIG_FLASH_CFI_DRIVER 469 #define CONFIG_SYS_FLASH_CFI 470 #define CONFIG_SYS_FLASH_EMPTY_INFO 471 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 472 473 /* Nand Flash */ 474 #ifdef CONFIG_NAND_FSL_ELBC 475 #define CONFIG_SYS_NAND_BASE 0xff800000 476 #ifdef CONFIG_PHYS_64BIT 477 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 478 #else 479 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 480 #endif 481 482 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 483 #define CONFIG_SYS_MAX_NAND_DEVICE 1 484 #define CONFIG_CMD_NAND 485 #if defined(CONFIG_P1020RDB_PD) 486 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 487 #else 488 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 489 #endif 490 491 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 492 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 493 | BR_PS_8 /* Port Size = 8 bit */ \ 494 | BR_MS_FCM /* MSEL = FCM */ \ 495 | BR_V) /* valid */ 496 #if defined(CONFIG_P1020RDB_PD) 497 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 498 | OR_FCM_PGS /* Large Page*/ \ 499 | OR_FCM_CSCT \ 500 | OR_FCM_CST \ 501 | OR_FCM_CHT \ 502 | OR_FCM_SCY_1 \ 503 | OR_FCM_TRLX \ 504 | OR_FCM_EHTR) 505 #else 506 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 507 | OR_FCM_CSCT \ 508 | OR_FCM_CST \ 509 | OR_FCM_CHT \ 510 | OR_FCM_SCY_1 \ 511 | OR_FCM_TRLX \ 512 | OR_FCM_EHTR) 513 #endif 514 #endif /* CONFIG_NAND_FSL_ELBC */ 515 516 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 517 518 #define CONFIG_SYS_INIT_RAM_LOCK 519 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 520 #ifdef CONFIG_PHYS_64BIT 521 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 522 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 523 /* The assembler doesn't like typecast */ 524 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 525 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 526 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 527 #else 528 /* Initial L1 address */ 529 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 530 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 531 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 532 #endif 533 /* Size of used area in RAM */ 534 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 535 536 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 537 GENERATED_GBL_DATA_SIZE) 538 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 539 540 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 541 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 542 543 #define CONFIG_SYS_CPLD_BASE 0xffa00000 544 #ifdef CONFIG_PHYS_64BIT 545 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 546 #else 547 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 548 #endif 549 /* CPLD config size: 1Mb */ 550 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 551 BR_PS_8 | BR_V) 552 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 553 554 #define CONFIG_SYS_PMC_BASE 0xff980000 555 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 556 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 557 BR_PS_8 | BR_V) 558 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 559 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 560 OR_GPCM_EAD) 561 562 #ifdef CONFIG_NAND 563 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 564 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 565 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 566 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 567 #else 568 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 569 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 570 #ifdef CONFIG_NAND_FSL_ELBC 571 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 572 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 573 #endif 574 #endif 575 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 576 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 577 578 /* Vsc7385 switch */ 579 #ifdef CONFIG_VSC7385_ENET 580 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 581 582 #ifdef CONFIG_PHYS_64BIT 583 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 584 #else 585 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 586 #endif 587 588 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 589 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 590 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 591 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 592 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 593 594 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 595 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 596 597 /* The size of the VSC7385 firmware image */ 598 #define CONFIG_VSC7385_IMAGE_SIZE 8192 599 #endif 600 601 /* 602 * Config the L2 Cache as L2 SRAM 603 */ 604 #if defined(CONFIG_SPL_BUILD) 605 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 606 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 607 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 608 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 609 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 610 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 611 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 612 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 613 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 614 #if defined(CONFIG_P2020RDB) 615 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 616 #else 617 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 618 #endif 619 #elif defined(CONFIG_NAND) 620 #ifdef CONFIG_TPL_BUILD 621 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 622 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 623 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 624 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 625 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 626 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 627 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 628 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 629 #else 630 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 631 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 632 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 633 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 634 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 635 #endif /* CONFIG_TPL_BUILD */ 636 #endif 637 #endif 638 639 /* Serial Port - controlled on board with jumper J8 640 * open - index 2 641 * shorted - index 1 642 */ 643 #define CONFIG_CONS_INDEX 1 644 #undef CONFIG_SERIAL_SOFTWARE_FIFO 645 #define CONFIG_SYS_NS16550_SERIAL 646 #define CONFIG_SYS_NS16550_REG_SIZE 1 647 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 648 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 649 #define CONFIG_NS16550_MIN_FUNCTIONS 650 #endif 651 652 #define CONFIG_SYS_BAUDRATE_TABLE \ 653 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 654 655 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 656 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 657 658 /* I2C */ 659 #define CONFIG_SYS_I2C 660 #define CONFIG_SYS_I2C_FSL 661 #define CONFIG_SYS_FSL_I2C_SPEED 400000 662 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 663 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 664 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 665 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 666 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 667 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 668 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 669 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 670 671 /* 672 * I2C2 EEPROM 673 */ 674 #undef CONFIG_ID_EEPROM 675 676 #define CONFIG_RTC_PT7C4338 677 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 678 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 679 680 /* enable read and write access to EEPROM */ 681 #define CONFIG_CMD_EEPROM 682 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 683 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 684 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 685 686 /* 687 * eSPI - Enhanced SPI 688 */ 689 #define CONFIG_HARD_SPI 690 691 #if defined(CONFIG_SPI_FLASH) 692 #define CONFIG_SF_DEFAULT_SPEED 10000000 693 #define CONFIG_SF_DEFAULT_MODE 0 694 #endif 695 696 #if defined(CONFIG_PCI) 697 /* 698 * General PCI 699 * Memory space is mapped 1-1, but I/O space must start from 0. 700 */ 701 702 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 703 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 704 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 705 #ifdef CONFIG_PHYS_64BIT 706 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 707 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 708 #else 709 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 710 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 711 #endif 712 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 713 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 714 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 715 #ifdef CONFIG_PHYS_64BIT 716 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 717 #else 718 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 719 #endif 720 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 721 722 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 723 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 724 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 725 #ifdef CONFIG_PHYS_64BIT 726 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 727 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 728 #else 729 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 730 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 731 #endif 732 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 733 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 734 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 735 #ifdef CONFIG_PHYS_64BIT 736 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 737 #else 738 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 739 #endif 740 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 741 742 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 743 #define CONFIG_CMD_PCI 744 745 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 746 #define CONFIG_DOS_PARTITION 747 #endif /* CONFIG_PCI */ 748 749 #if defined(CONFIG_TSEC_ENET) 750 #define CONFIG_MII /* MII PHY management */ 751 #define CONFIG_TSEC1 752 #define CONFIG_TSEC1_NAME "eTSEC1" 753 #define CONFIG_TSEC2 754 #define CONFIG_TSEC2_NAME "eTSEC2" 755 #define CONFIG_TSEC3 756 #define CONFIG_TSEC3_NAME "eTSEC3" 757 758 #define TSEC1_PHY_ADDR 2 759 #define TSEC2_PHY_ADDR 0 760 #define TSEC3_PHY_ADDR 1 761 762 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 763 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 764 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 765 766 #define TSEC1_PHYIDX 0 767 #define TSEC2_PHYIDX 0 768 #define TSEC3_PHYIDX 0 769 770 #define CONFIG_ETHPRIME "eTSEC1" 771 772 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 773 774 #define CONFIG_HAS_ETH0 775 #define CONFIG_HAS_ETH1 776 #define CONFIG_HAS_ETH2 777 #endif /* CONFIG_TSEC_ENET */ 778 779 #ifdef CONFIG_QE 780 /* QE microcode/firmware address */ 781 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 782 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 783 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 784 #endif /* CONFIG_QE */ 785 786 #ifdef CONFIG_P1025RDB 787 /* 788 * QE UEC ethernet configuration 789 */ 790 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 791 792 #undef CONFIG_UEC_ETH 793 #define CONFIG_PHY_MODE_NEED_CHANGE 794 795 #define CONFIG_UEC_ETH1 /* ETH1 */ 796 #define CONFIG_HAS_ETH0 797 798 #ifdef CONFIG_UEC_ETH1 799 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 800 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 801 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 802 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 803 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 804 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 805 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 806 #endif /* CONFIG_UEC_ETH1 */ 807 808 #define CONFIG_UEC_ETH5 /* ETH5 */ 809 #define CONFIG_HAS_ETH1 810 811 #ifdef CONFIG_UEC_ETH5 812 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 813 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 814 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 815 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 816 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 817 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 818 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 819 #endif /* CONFIG_UEC_ETH5 */ 820 #endif /* CONFIG_P1025RDB */ 821 822 /* 823 * Environment 824 */ 825 #ifdef CONFIG_SPIFLASH 826 #define CONFIG_ENV_IS_IN_SPI_FLASH 827 #define CONFIG_ENV_SPI_BUS 0 828 #define CONFIG_ENV_SPI_CS 0 829 #define CONFIG_ENV_SPI_MAX_HZ 10000000 830 #define CONFIG_ENV_SPI_MODE 0 831 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 832 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 833 #define CONFIG_ENV_SECT_SIZE 0x10000 834 #elif defined(CONFIG_SDCARD) 835 #define CONFIG_ENV_IS_IN_MMC 836 #define CONFIG_FSL_FIXED_MMC_LOCATION 837 #define CONFIG_ENV_SIZE 0x2000 838 #define CONFIG_SYS_MMC_ENV_DEV 0 839 #elif defined(CONFIG_NAND) 840 #ifdef CONFIG_TPL_BUILD 841 #define CONFIG_ENV_SIZE 0x2000 842 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 843 #else 844 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 845 #endif 846 #define CONFIG_ENV_IS_IN_NAND 847 #define CONFIG_ENV_OFFSET (1024 * 1024) 848 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 849 #elif defined(CONFIG_SYS_RAMBOOT) 850 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 851 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 852 #define CONFIG_ENV_SIZE 0x2000 853 #else 854 #define CONFIG_ENV_IS_IN_FLASH 855 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 856 #define CONFIG_ENV_SIZE 0x2000 857 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 858 #endif 859 860 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 861 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 862 863 /* 864 * Command line configuration. 865 */ 866 #define CONFIG_CMD_IRQ 867 #define CONFIG_CMD_DATE 868 #define CONFIG_CMD_REGINFO 869 870 /* 871 * USB 872 */ 873 #define CONFIG_HAS_FSL_DR_USB 874 875 #if defined(CONFIG_HAS_FSL_DR_USB) 876 #define CONFIG_USB_EHCI 877 878 #ifdef CONFIG_USB_EHCI 879 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 880 #define CONFIG_USB_EHCI_FSL 881 #endif 882 #endif 883 884 #if defined(CONFIG_P1020RDB_PD) 885 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 886 #endif 887 888 #define CONFIG_MMC 889 890 #ifdef CONFIG_MMC 891 #define CONFIG_FSL_ESDHC 892 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 893 #define CONFIG_GENERIC_MMC 894 #endif 895 896 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 897 || defined(CONFIG_FSL_SATA) 898 #define CONFIG_DOS_PARTITION 899 #endif 900 901 #undef CONFIG_WATCHDOG /* watchdog disabled */ 902 903 /* 904 * Miscellaneous configurable options 905 */ 906 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 907 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 908 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 909 #if defined(CONFIG_CMD_KGDB) 910 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 911 #else 912 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 913 #endif 914 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 915 /* Print Buffer Size */ 916 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 917 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 918 919 /* 920 * For booting Linux, the board info and command line data 921 * have to be in the first 64 MB of memory, since this is 922 * the maximum mapped by the Linux kernel during initialization. 923 */ 924 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 925 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 926 927 #if defined(CONFIG_CMD_KGDB) 928 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 929 #endif 930 931 /* 932 * Environment Configuration 933 */ 934 #define CONFIG_HOSTNAME unknown 935 #define CONFIG_ROOTPATH "/opt/nfsroot" 936 #define CONFIG_BOOTFILE "uImage" 937 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 938 939 /* default location for tftp and bootm */ 940 #define CONFIG_LOADADDR 1000000 941 942 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 943 944 #define CONFIG_BAUDRATE 115200 945 946 #ifdef __SW_BOOT_NOR 947 #define __NOR_RST_CMD \ 948 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 949 i2c mw 18 3 __SW_BOOT_MASK 1; reset 950 #endif 951 #ifdef __SW_BOOT_SPI 952 #define __SPI_RST_CMD \ 953 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 954 i2c mw 18 3 __SW_BOOT_MASK 1; reset 955 #endif 956 #ifdef __SW_BOOT_SD 957 #define __SD_RST_CMD \ 958 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 959 i2c mw 18 3 __SW_BOOT_MASK 1; reset 960 #endif 961 #ifdef __SW_BOOT_NAND 962 #define __NAND_RST_CMD \ 963 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 964 i2c mw 18 3 __SW_BOOT_MASK 1; reset 965 #endif 966 #ifdef __SW_BOOT_PCIE 967 #define __PCIE_RST_CMD \ 968 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 969 i2c mw 18 3 __SW_BOOT_MASK 1; reset 970 #endif 971 972 #define CONFIG_EXTRA_ENV_SETTINGS \ 973 "netdev=eth0\0" \ 974 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 975 "loadaddr=1000000\0" \ 976 "bootfile=uImage\0" \ 977 "tftpflash=tftpboot $loadaddr $uboot; " \ 978 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 979 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 980 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 981 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 982 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 983 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 984 "consoledev=ttyS0\0" \ 985 "ramdiskaddr=2000000\0" \ 986 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 987 "fdtaddr=1e00000\0" \ 988 "bdev=sda1\0" \ 989 "jffs2nor=mtdblock3\0" \ 990 "norbootaddr=ef080000\0" \ 991 "norfdtaddr=ef040000\0" \ 992 "jffs2nand=mtdblock9\0" \ 993 "nandbootaddr=100000\0" \ 994 "nandfdtaddr=80000\0" \ 995 "ramdisk_size=120000\0" \ 996 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 997 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 998 __stringify(__NOR_RST_CMD)"\0" \ 999 __stringify(__SPI_RST_CMD)"\0" \ 1000 __stringify(__SD_RST_CMD)"\0" \ 1001 __stringify(__NAND_RST_CMD)"\0" \ 1002 __stringify(__PCIE_RST_CMD)"\0" 1003 1004 #define CONFIG_NFSBOOTCOMMAND \ 1005 "setenv bootargs root=/dev/nfs rw " \ 1006 "nfsroot=$serverip:$rootpath " \ 1007 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 1008 "console=$consoledev,$baudrate $othbootargs;" \ 1009 "tftp $loadaddr $bootfile;" \ 1010 "tftp $fdtaddr $fdtfile;" \ 1011 "bootm $loadaddr - $fdtaddr" 1012 1013 #define CONFIG_HDBOOT \ 1014 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 1015 "console=$consoledev,$baudrate $othbootargs;" \ 1016 "usb start;" \ 1017 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 1018 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 1019 "bootm $loadaddr - $fdtaddr" 1020 1021 #define CONFIG_USB_FAT_BOOT \ 1022 "setenv bootargs root=/dev/ram rw " \ 1023 "console=$consoledev,$baudrate $othbootargs " \ 1024 "ramdisk_size=$ramdisk_size;" \ 1025 "usb start;" \ 1026 "fatload usb 0:2 $loadaddr $bootfile;" \ 1027 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 1028 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 1029 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1030 1031 #define CONFIG_USB_EXT2_BOOT \ 1032 "setenv bootargs root=/dev/ram rw " \ 1033 "console=$consoledev,$baudrate $othbootargs " \ 1034 "ramdisk_size=$ramdisk_size;" \ 1035 "usb start;" \ 1036 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1037 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1038 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1039 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1040 1041 #define CONFIG_NORBOOT \ 1042 "setenv bootargs root=/dev/$jffs2nor rw " \ 1043 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1044 "bootm $norbootaddr - $norfdtaddr" 1045 1046 #define CONFIG_RAMBOOTCOMMAND \ 1047 "setenv bootargs root=/dev/ram rw " \ 1048 "console=$consoledev,$baudrate $othbootargs " \ 1049 "ramdisk_size=$ramdisk_size;" \ 1050 "tftp $ramdiskaddr $ramdiskfile;" \ 1051 "tftp $loadaddr $bootfile;" \ 1052 "tftp $fdtaddr $fdtfile;" \ 1053 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1054 1055 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1056 1057 #endif /* __CONFIG_H */ 1058