1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TARGET_P1020MBG) 14 #define CONFIG_BOARDNAME "P1020MBG-PC" 15 #define CONFIG_VSC7385_ENET 16 #define CONFIG_SLIC 17 #define __SW_BOOT_MASK 0x03 18 #define __SW_BOOT_NOR 0xe4 19 #define __SW_BOOT_SD 0x54 20 #define CONFIG_SYS_L2_SIZE (256 << 10) 21 #endif 22 23 #if defined(CONFIG_TARGET_P1020UTM) 24 #define CONFIG_BOARDNAME "P1020UTM-PC" 25 #define __SW_BOOT_MASK 0x03 26 #define __SW_BOOT_NOR 0xe0 27 #define __SW_BOOT_SD 0x50 28 #define CONFIG_SYS_L2_SIZE (256 << 10) 29 #endif 30 31 #if defined(CONFIG_TARGET_P1020RDB_PC) 32 #define CONFIG_BOARDNAME "P1020RDB-PC" 33 #define CONFIG_NAND_FSL_ELBC 34 #define CONFIG_VSC7385_ENET 35 #define CONFIG_SLIC 36 #define __SW_BOOT_MASK 0x03 37 #define __SW_BOOT_NOR 0x5c 38 #define __SW_BOOT_SPI 0x1c 39 #define __SW_BOOT_SD 0x9c 40 #define __SW_BOOT_NAND 0xec 41 #define __SW_BOOT_PCIE 0x6c 42 #define CONFIG_SYS_L2_SIZE (256 << 10) 43 #endif 44 45 /* 46 * P1020RDB-PD board has user selectable switches for evaluating different 47 * frequency and boot options for the P1020 device. The table that 48 * follow describe the available options. The front six binary number was in 49 * accordance with SW3[1:6]. 50 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 51 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 52 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 53 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 54 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 55 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 56 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 57 */ 58 #if defined(CONFIG_TARGET_P1020RDB_PD) 59 #define CONFIG_BOARDNAME "P1020RDB-PD" 60 #define CONFIG_NAND_FSL_ELBC 61 #define CONFIG_VSC7385_ENET 62 #define CONFIG_SLIC 63 #define __SW_BOOT_MASK 0x03 64 #define __SW_BOOT_NOR 0x64 65 #define __SW_BOOT_SPI 0x34 66 #define __SW_BOOT_SD 0x24 67 #define __SW_BOOT_NAND 0x44 68 #define __SW_BOOT_PCIE 0x74 69 #define CONFIG_SYS_L2_SIZE (256 << 10) 70 /* 71 * Dynamic MTD Partition support with mtdparts 72 */ 73 #define CONFIG_MTD_DEVICE 74 #define CONFIG_MTD_PARTITIONS 75 #define CONFIG_FLASH_CFI_MTD 76 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 77 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ 78 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" 79 #endif 80 81 #if defined(CONFIG_TARGET_P1021RDB) 82 #define CONFIG_BOARDNAME "P1021RDB-PC" 83 #define CONFIG_NAND_FSL_ELBC 84 #define CONFIG_QE 85 #define CONFIG_VSC7385_ENET 86 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 87 addresses in the LBC */ 88 #define __SW_BOOT_MASK 0x03 89 #define __SW_BOOT_NOR 0x5c 90 #define __SW_BOOT_SPI 0x1c 91 #define __SW_BOOT_SD 0x9c 92 #define __SW_BOOT_NAND 0xec 93 #define __SW_BOOT_PCIE 0x6c 94 #define CONFIG_SYS_L2_SIZE (256 << 10) 95 /* 96 * Dynamic MTD Partition support with mtdparts 97 */ 98 #define CONFIG_MTD_DEVICE 99 #define CONFIG_MTD_PARTITIONS 100 #define CONFIG_FLASH_CFI_MTD 101 #ifdef CONFIG_PHYS_64BIT 102 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 103 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 104 "256k(dtb),4608k(kernel),9728k(fs)," \ 105 "256k(qe-ucode-firmware),1280k(u-boot)" 106 #else 107 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 108 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 109 "256k(dtb),4608k(kernel),9728k(fs)," \ 110 "256k(qe-ucode-firmware),1280k(u-boot)" 111 #endif 112 #endif 113 114 #if defined(CONFIG_TARGET_P1024RDB) 115 #define CONFIG_BOARDNAME "P1024RDB" 116 #define CONFIG_NAND_FSL_ELBC 117 #define CONFIG_SLIC 118 #define __SW_BOOT_MASK 0xf3 119 #define __SW_BOOT_NOR 0x00 120 #define __SW_BOOT_SPI 0x08 121 #define __SW_BOOT_SD 0x04 122 #define __SW_BOOT_NAND 0x0c 123 #define CONFIG_SYS_L2_SIZE (256 << 10) 124 #endif 125 126 #if defined(CONFIG_TARGET_P1025RDB) 127 #define CONFIG_BOARDNAME "P1025RDB" 128 #define CONFIG_NAND_FSL_ELBC 129 #define CONFIG_QE 130 #define CONFIG_SLIC 131 132 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 133 addresses in the LBC */ 134 #define __SW_BOOT_MASK 0xf3 135 #define __SW_BOOT_NOR 0x00 136 #define __SW_BOOT_SPI 0x08 137 #define __SW_BOOT_SD 0x04 138 #define __SW_BOOT_NAND 0x0c 139 #define CONFIG_SYS_L2_SIZE (256 << 10) 140 #endif 141 142 #if defined(CONFIG_TARGET_P2020RDB) 143 #define CONFIG_BOARDNAME "P2020RDB-PC" 144 #define CONFIG_NAND_FSL_ELBC 145 #define CONFIG_VSC7385_ENET 146 #define __SW_BOOT_MASK 0x03 147 #define __SW_BOOT_NOR 0xc8 148 #define __SW_BOOT_SPI 0x28 149 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 150 #define __SW_BOOT_NAND 0xe8 151 #define __SW_BOOT_PCIE 0xa8 152 #define CONFIG_SYS_L2_SIZE (512 << 10) 153 /* 154 * Dynamic MTD Partition support with mtdparts 155 */ 156 #define CONFIG_MTD_DEVICE 157 #define CONFIG_MTD_PARTITIONS 158 #define CONFIG_FLASH_CFI_MTD 159 #ifdef CONFIG_PHYS_64BIT 160 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 161 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 162 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 163 #else 164 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 165 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 166 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 167 #endif 168 #endif 169 170 #ifdef CONFIG_SDCARD 171 #define CONFIG_SPL_MMC_MINIMAL 172 #define CONFIG_SPL_FLUSH_IMAGE 173 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 174 #define CONFIG_SYS_TEXT_BASE 0x11001000 175 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 176 #define CONFIG_SPL_PAD_TO 0x20000 177 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 178 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 179 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 180 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 181 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 182 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 183 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 184 #define CONFIG_SPL_MMC_BOOT 185 #ifdef CONFIG_SPL_BUILD 186 #define CONFIG_SPL_COMMON_INIT_DDR 187 #endif 188 #endif 189 190 #ifdef CONFIG_SPIFLASH 191 #define CONFIG_SPL_SPI_FLASH_MINIMAL 192 #define CONFIG_SPL_FLUSH_IMAGE 193 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 194 #define CONFIG_SYS_TEXT_BASE 0x11001000 195 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 196 #define CONFIG_SPL_PAD_TO 0x20000 197 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 198 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 199 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 200 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 201 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 202 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 203 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 204 #define CONFIG_SPL_SPI_BOOT 205 #ifdef CONFIG_SPL_BUILD 206 #define CONFIG_SPL_COMMON_INIT_DDR 207 #endif 208 #endif 209 210 #ifdef CONFIG_NAND 211 #ifdef CONFIG_TPL_BUILD 212 #define CONFIG_SPL_NAND_BOOT 213 #define CONFIG_SPL_FLUSH_IMAGE 214 #define CONFIG_SPL_NAND_INIT 215 #define CONFIG_SPL_COMMON_INIT_DDR 216 #define CONFIG_SPL_MAX_SIZE (128 << 10) 217 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 218 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 219 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 220 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 221 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 222 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 223 #elif defined(CONFIG_SPL_BUILD) 224 #define CONFIG_SPL_INIT_MINIMAL 225 #define CONFIG_SPL_FLUSH_IMAGE 226 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 227 #define CONFIG_SPL_TEXT_BASE 0xff800000 228 #define CONFIG_SPL_MAX_SIZE 4096 229 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 230 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 231 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 232 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 233 #endif /* not CONFIG_TPL_BUILD */ 234 235 #define CONFIG_SPL_PAD_TO 0x20000 236 #define CONFIG_TPL_PAD_TO 0x20000 237 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 238 #define CONFIG_SYS_TEXT_BASE 0x11001000 239 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 240 #endif 241 242 #ifndef CONFIG_SYS_TEXT_BASE 243 #define CONFIG_SYS_TEXT_BASE 0xeff40000 244 #endif 245 246 #ifndef CONFIG_RESET_VECTOR_ADDRESS 247 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 248 #endif 249 250 #ifndef CONFIG_SYS_MONITOR_BASE 251 #ifdef CONFIG_SPL_BUILD 252 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 253 #else 254 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 255 #endif 256 #endif 257 258 #define CONFIG_MP 259 260 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 261 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 262 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 263 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 264 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 265 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 266 267 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 268 #define CONFIG_ENV_OVERWRITE 269 270 #define CONFIG_SATA_SIL 271 #define CONFIG_SYS_SATA_MAX_DEVICE 2 272 #define CONFIG_LIBATA 273 #define CONFIG_LBA48 274 275 #if defined(CONFIG_TARGET_P2020RDB) 276 #define CONFIG_SYS_CLK_FREQ 100000000 277 #else 278 #define CONFIG_SYS_CLK_FREQ 66666666 279 #endif 280 #define CONFIG_DDR_CLK_FREQ 66666666 281 282 #define CONFIG_HWCONFIG 283 /* 284 * These can be toggled for performance analysis, otherwise use default. 285 */ 286 #define CONFIG_L2_CACHE 287 #define CONFIG_BTB 288 289 #define CONFIG_ENABLE_36BIT_PHYS 290 291 #ifdef CONFIG_PHYS_64BIT 292 #define CONFIG_ADDR_MAP 1 293 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 294 #endif 295 296 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 297 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 298 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 299 300 #define CONFIG_SYS_CCSRBAR 0xffe00000 301 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 302 303 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 304 SPL code*/ 305 #ifdef CONFIG_SPL_BUILD 306 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 307 #endif 308 309 /* DDR Setup */ 310 #define CONFIG_SYS_DDR_RAW_TIMING 311 #define CONFIG_DDR_SPD 312 #define CONFIG_SYS_SPD_BUS_NUM 1 313 #define SPD_EEPROM_ADDRESS 0x52 314 #undef CONFIG_FSL_DDR_INTERACTIVE 315 316 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 317 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 318 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 319 #else 320 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 321 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 322 #endif 323 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 324 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 325 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 326 327 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 328 329 /* Default settings for DDR3 */ 330 #ifndef CONFIG_TARGET_P2020RDB 331 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 332 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 333 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 334 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 335 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 336 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 337 338 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 339 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 340 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 341 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 342 343 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 344 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 345 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 346 #define CONFIG_SYS_DDR_RCW_1 0x00000000 347 #define CONFIG_SYS_DDR_RCW_2 0x00000000 348 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 349 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 350 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 351 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 352 353 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 354 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 355 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 356 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 357 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 358 #define CONFIG_SYS_DDR_MODE_1 0x40461520 359 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 360 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 361 #endif 362 363 #undef CONFIG_CLOCKS_IN_MHZ 364 365 /* 366 * Memory map 367 * 368 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 369 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 370 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 371 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 372 * (early boot only) 373 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 374 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 375 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 376 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 377 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 378 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 379 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 380 */ 381 382 /* 383 * Local Bus Definitions 384 */ 385 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 386 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 387 #define CONFIG_SYS_FLASH_BASE 0xec000000 388 #elif defined(CONFIG_TARGET_P1020UTM) 389 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 390 #define CONFIG_SYS_FLASH_BASE 0xee000000 391 #else 392 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 393 #define CONFIG_SYS_FLASH_BASE 0xef000000 394 #endif 395 396 #ifdef CONFIG_PHYS_64BIT 397 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 398 #else 399 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 400 #endif 401 402 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 403 | BR_PS_16 | BR_V) 404 405 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 406 407 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 408 #define CONFIG_SYS_FLASH_QUIET_TEST 409 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 410 411 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 412 413 #undef CONFIG_SYS_FLASH_CHECKSUM 414 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 415 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 416 417 #define CONFIG_FLASH_CFI_DRIVER 418 #define CONFIG_SYS_FLASH_CFI 419 #define CONFIG_SYS_FLASH_EMPTY_INFO 420 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 421 422 /* Nand Flash */ 423 #ifdef CONFIG_NAND_FSL_ELBC 424 #define CONFIG_SYS_NAND_BASE 0xff800000 425 #ifdef CONFIG_PHYS_64BIT 426 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 427 #else 428 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 429 #endif 430 431 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 432 #define CONFIG_SYS_MAX_NAND_DEVICE 1 433 #if defined(CONFIG_TARGET_P1020RDB_PD) 434 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 435 #else 436 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 437 #endif 438 439 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 440 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 441 | BR_PS_8 /* Port Size = 8 bit */ \ 442 | BR_MS_FCM /* MSEL = FCM */ \ 443 | BR_V) /* valid */ 444 #if defined(CONFIG_TARGET_P1020RDB_PD) 445 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 446 | OR_FCM_PGS /* Large Page*/ \ 447 | OR_FCM_CSCT \ 448 | OR_FCM_CST \ 449 | OR_FCM_CHT \ 450 | OR_FCM_SCY_1 \ 451 | OR_FCM_TRLX \ 452 | OR_FCM_EHTR) 453 #else 454 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 455 | OR_FCM_CSCT \ 456 | OR_FCM_CST \ 457 | OR_FCM_CHT \ 458 | OR_FCM_SCY_1 \ 459 | OR_FCM_TRLX \ 460 | OR_FCM_EHTR) 461 #endif 462 #endif /* CONFIG_NAND_FSL_ELBC */ 463 464 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 465 466 #define CONFIG_SYS_INIT_RAM_LOCK 467 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 468 #ifdef CONFIG_PHYS_64BIT 469 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 471 /* The assembler doesn't like typecast */ 472 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 473 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 474 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 475 #else 476 /* Initial L1 address */ 477 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 478 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 479 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 480 #endif 481 /* Size of used area in RAM */ 482 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 483 484 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 485 GENERATED_GBL_DATA_SIZE) 486 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 487 488 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 489 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 490 491 #define CONFIG_SYS_CPLD_BASE 0xffa00000 492 #ifdef CONFIG_PHYS_64BIT 493 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 494 #else 495 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 496 #endif 497 /* CPLD config size: 1Mb */ 498 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 499 BR_PS_8 | BR_V) 500 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 501 502 #define CONFIG_SYS_PMC_BASE 0xff980000 503 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 504 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 505 BR_PS_8 | BR_V) 506 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 507 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 508 OR_GPCM_EAD) 509 510 #ifdef CONFIG_NAND 511 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 512 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 513 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 514 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 515 #else 516 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 517 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 518 #ifdef CONFIG_NAND_FSL_ELBC 519 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 520 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 521 #endif 522 #endif 523 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 524 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 525 526 /* Vsc7385 switch */ 527 #ifdef CONFIG_VSC7385_ENET 528 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 529 530 #ifdef CONFIG_PHYS_64BIT 531 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 532 #else 533 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 534 #endif 535 536 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 537 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 538 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 539 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 540 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 541 542 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 543 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 544 545 /* The size of the VSC7385 firmware image */ 546 #define CONFIG_VSC7385_IMAGE_SIZE 8192 547 #endif 548 549 /* 550 * Config the L2 Cache as L2 SRAM 551 */ 552 #if defined(CONFIG_SPL_BUILD) 553 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 554 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 555 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 556 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 557 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 558 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 559 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 560 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 561 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 562 #if defined(CONFIG_TARGET_P2020RDB) 563 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 564 #else 565 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 566 #endif 567 #elif defined(CONFIG_NAND) 568 #ifdef CONFIG_TPL_BUILD 569 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 570 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 571 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 572 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 573 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 574 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 575 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 576 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 577 #else 578 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 579 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 580 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 581 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 582 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 583 #endif /* CONFIG_TPL_BUILD */ 584 #endif 585 #endif 586 587 /* Serial Port - controlled on board with jumper J8 588 * open - index 2 589 * shorted - index 1 590 */ 591 #define CONFIG_CONS_INDEX 1 592 #undef CONFIG_SERIAL_SOFTWARE_FIFO 593 #define CONFIG_SYS_NS16550_SERIAL 594 #define CONFIG_SYS_NS16550_REG_SIZE 1 595 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 596 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 597 #define CONFIG_NS16550_MIN_FUNCTIONS 598 #endif 599 600 #define CONFIG_SYS_BAUDRATE_TABLE \ 601 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 602 603 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 604 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 605 606 /* I2C */ 607 #define CONFIG_SYS_I2C 608 #define CONFIG_SYS_I2C_FSL 609 #define CONFIG_SYS_FSL_I2C_SPEED 400000 610 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 611 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 612 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 613 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 614 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 615 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 616 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 617 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 618 619 /* 620 * I2C2 EEPROM 621 */ 622 #undef CONFIG_ID_EEPROM 623 624 #define CONFIG_RTC_PT7C4338 625 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 626 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 627 628 /* enable read and write access to EEPROM */ 629 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 630 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 631 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 632 633 /* 634 * eSPI - Enhanced SPI 635 */ 636 #define CONFIG_HARD_SPI 637 638 #if defined(CONFIG_SPI_FLASH) 639 #define CONFIG_SF_DEFAULT_SPEED 10000000 640 #define CONFIG_SF_DEFAULT_MODE 0 641 #endif 642 643 #if defined(CONFIG_PCI) 644 /* 645 * General PCI 646 * Memory space is mapped 1-1, but I/O space must start from 0. 647 */ 648 649 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 650 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 651 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 652 #ifdef CONFIG_PHYS_64BIT 653 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 654 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 655 #else 656 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 657 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 658 #endif 659 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 660 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 661 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 662 #ifdef CONFIG_PHYS_64BIT 663 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 664 #else 665 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 666 #endif 667 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 668 669 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 670 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 671 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 672 #ifdef CONFIG_PHYS_64BIT 673 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 674 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 675 #else 676 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 677 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 678 #endif 679 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 680 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 681 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 682 #ifdef CONFIG_PHYS_64BIT 683 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 684 #else 685 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 686 #endif 687 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 688 689 #define CONFIG_CMD_PCI 690 691 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 692 #endif /* CONFIG_PCI */ 693 694 #if defined(CONFIG_TSEC_ENET) 695 #define CONFIG_MII /* MII PHY management */ 696 #define CONFIG_TSEC1 697 #define CONFIG_TSEC1_NAME "eTSEC1" 698 #define CONFIG_TSEC2 699 #define CONFIG_TSEC2_NAME "eTSEC2" 700 #define CONFIG_TSEC3 701 #define CONFIG_TSEC3_NAME "eTSEC3" 702 703 #define TSEC1_PHY_ADDR 2 704 #define TSEC2_PHY_ADDR 0 705 #define TSEC3_PHY_ADDR 1 706 707 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 708 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 709 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 710 711 #define TSEC1_PHYIDX 0 712 #define TSEC2_PHYIDX 0 713 #define TSEC3_PHYIDX 0 714 715 #define CONFIG_ETHPRIME "eTSEC1" 716 717 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 718 719 #define CONFIG_HAS_ETH0 720 #define CONFIG_HAS_ETH1 721 #define CONFIG_HAS_ETH2 722 #endif /* CONFIG_TSEC_ENET */ 723 724 #ifdef CONFIG_QE 725 /* QE microcode/firmware address */ 726 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 727 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 728 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 729 #endif /* CONFIG_QE */ 730 731 #ifdef CONFIG_TARGET_P1025RDB 732 /* 733 * QE UEC ethernet configuration 734 */ 735 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 736 737 #undef CONFIG_UEC_ETH 738 #define CONFIG_PHY_MODE_NEED_CHANGE 739 740 #define CONFIG_UEC_ETH1 /* ETH1 */ 741 #define CONFIG_HAS_ETH0 742 743 #ifdef CONFIG_UEC_ETH1 744 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 745 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 746 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 747 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 748 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 749 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 750 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 751 #endif /* CONFIG_UEC_ETH1 */ 752 753 #define CONFIG_UEC_ETH5 /* ETH5 */ 754 #define CONFIG_HAS_ETH1 755 756 #ifdef CONFIG_UEC_ETH5 757 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 758 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 759 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 760 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 761 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 762 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 763 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 764 #endif /* CONFIG_UEC_ETH5 */ 765 #endif /* CONFIG_TARGET_P1025RDB */ 766 767 /* 768 * Environment 769 */ 770 #ifdef CONFIG_SPIFLASH 771 #define CONFIG_ENV_SPI_BUS 0 772 #define CONFIG_ENV_SPI_CS 0 773 #define CONFIG_ENV_SPI_MAX_HZ 10000000 774 #define CONFIG_ENV_SPI_MODE 0 775 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 776 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 777 #define CONFIG_ENV_SECT_SIZE 0x10000 778 #elif defined(CONFIG_SDCARD) 779 #define CONFIG_FSL_FIXED_MMC_LOCATION 780 #define CONFIG_ENV_SIZE 0x2000 781 #define CONFIG_SYS_MMC_ENV_DEV 0 782 #elif defined(CONFIG_NAND) 783 #ifdef CONFIG_TPL_BUILD 784 #define CONFIG_ENV_SIZE 0x2000 785 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 786 #else 787 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 788 #endif 789 #define CONFIG_ENV_OFFSET (1024 * 1024) 790 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 791 #elif defined(CONFIG_SYS_RAMBOOT) 792 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 793 #define CONFIG_ENV_SIZE 0x2000 794 #else 795 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 796 #define CONFIG_ENV_SIZE 0x2000 797 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 798 #endif 799 800 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 801 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 802 803 /* 804 * Command line configuration. 805 */ 806 #define CONFIG_CMD_REGINFO 807 808 /* 809 * USB 810 */ 811 #define CONFIG_HAS_FSL_DR_USB 812 813 #if defined(CONFIG_HAS_FSL_DR_USB) 814 #ifdef CONFIG_USB_EHCI_HCD 815 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 816 #define CONFIG_USB_EHCI_FSL 817 #endif 818 #endif 819 820 #if defined(CONFIG_TARGET_P1020RDB_PD) 821 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 822 #endif 823 824 #ifdef CONFIG_MMC 825 #define CONFIG_FSL_ESDHC 826 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 827 #endif 828 829 #undef CONFIG_WATCHDOG /* watchdog disabled */ 830 831 /* 832 * Miscellaneous configurable options 833 */ 834 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 835 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 836 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 837 #if defined(CONFIG_CMD_KGDB) 838 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 839 #else 840 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 841 #endif 842 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 843 /* Print Buffer Size */ 844 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 845 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 846 847 /* 848 * For booting Linux, the board info and command line data 849 * have to be in the first 64 MB of memory, since this is 850 * the maximum mapped by the Linux kernel during initialization. 851 */ 852 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 853 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 854 855 #if defined(CONFIG_CMD_KGDB) 856 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 857 #endif 858 859 /* 860 * Environment Configuration 861 */ 862 #define CONFIG_HOSTNAME unknown 863 #define CONFIG_ROOTPATH "/opt/nfsroot" 864 #define CONFIG_BOOTFILE "uImage" 865 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 866 867 /* default location for tftp and bootm */ 868 #define CONFIG_LOADADDR 1000000 869 870 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 871 872 #ifdef __SW_BOOT_NOR 873 #define __NOR_RST_CMD \ 874 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 875 i2c mw 18 3 __SW_BOOT_MASK 1; reset 876 #endif 877 #ifdef __SW_BOOT_SPI 878 #define __SPI_RST_CMD \ 879 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 880 i2c mw 18 3 __SW_BOOT_MASK 1; reset 881 #endif 882 #ifdef __SW_BOOT_SD 883 #define __SD_RST_CMD \ 884 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 885 i2c mw 18 3 __SW_BOOT_MASK 1; reset 886 #endif 887 #ifdef __SW_BOOT_NAND 888 #define __NAND_RST_CMD \ 889 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 890 i2c mw 18 3 __SW_BOOT_MASK 1; reset 891 #endif 892 #ifdef __SW_BOOT_PCIE 893 #define __PCIE_RST_CMD \ 894 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 895 i2c mw 18 3 __SW_BOOT_MASK 1; reset 896 #endif 897 898 #define CONFIG_EXTRA_ENV_SETTINGS \ 899 "netdev=eth0\0" \ 900 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 901 "loadaddr=1000000\0" \ 902 "bootfile=uImage\0" \ 903 "tftpflash=tftpboot $loadaddr $uboot; " \ 904 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 905 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 906 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 907 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 908 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 909 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 910 "consoledev=ttyS0\0" \ 911 "ramdiskaddr=2000000\0" \ 912 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 913 "fdtaddr=1e00000\0" \ 914 "bdev=sda1\0" \ 915 "jffs2nor=mtdblock3\0" \ 916 "norbootaddr=ef080000\0" \ 917 "norfdtaddr=ef040000\0" \ 918 "jffs2nand=mtdblock9\0" \ 919 "nandbootaddr=100000\0" \ 920 "nandfdtaddr=80000\0" \ 921 "ramdisk_size=120000\0" \ 922 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 923 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 924 __stringify(__NOR_RST_CMD)"\0" \ 925 __stringify(__SPI_RST_CMD)"\0" \ 926 __stringify(__SD_RST_CMD)"\0" \ 927 __stringify(__NAND_RST_CMD)"\0" \ 928 __stringify(__PCIE_RST_CMD)"\0" 929 930 #define CONFIG_NFSBOOTCOMMAND \ 931 "setenv bootargs root=/dev/nfs rw " \ 932 "nfsroot=$serverip:$rootpath " \ 933 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 934 "console=$consoledev,$baudrate $othbootargs;" \ 935 "tftp $loadaddr $bootfile;" \ 936 "tftp $fdtaddr $fdtfile;" \ 937 "bootm $loadaddr - $fdtaddr" 938 939 #define CONFIG_HDBOOT \ 940 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 941 "console=$consoledev,$baudrate $othbootargs;" \ 942 "usb start;" \ 943 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 944 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 945 "bootm $loadaddr - $fdtaddr" 946 947 #define CONFIG_USB_FAT_BOOT \ 948 "setenv bootargs root=/dev/ram rw " \ 949 "console=$consoledev,$baudrate $othbootargs " \ 950 "ramdisk_size=$ramdisk_size;" \ 951 "usb start;" \ 952 "fatload usb 0:2 $loadaddr $bootfile;" \ 953 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 954 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 955 "bootm $loadaddr $ramdiskaddr $fdtaddr" 956 957 #define CONFIG_USB_EXT2_BOOT \ 958 "setenv bootargs root=/dev/ram rw " \ 959 "console=$consoledev,$baudrate $othbootargs " \ 960 "ramdisk_size=$ramdisk_size;" \ 961 "usb start;" \ 962 "ext2load usb 0:4 $loadaddr $bootfile;" \ 963 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 964 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 965 "bootm $loadaddr $ramdiskaddr $fdtaddr" 966 967 #define CONFIG_NORBOOT \ 968 "setenv bootargs root=/dev/$jffs2nor rw " \ 969 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 970 "bootm $norbootaddr - $norfdtaddr" 971 972 #define CONFIG_RAMBOOTCOMMAND \ 973 "setenv bootargs root=/dev/ram rw " \ 974 "console=$consoledev,$baudrate $othbootargs " \ 975 "ramdisk_size=$ramdisk_size;" \ 976 "tftp $ramdiskaddr $ramdiskfile;" \ 977 "tftp $loadaddr $bootfile;" \ 978 "tftp $fdtaddr $fdtfile;" \ 979 "bootm $loadaddr $ramdiskaddr $fdtaddr" 980 981 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 982 983 #endif /* __CONFIG_H */ 984