1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_SYS_GENERIC_BOARD 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #ifdef CONFIG_36BIT 17 #define CONFIG_PHYS_64BIT 18 #endif 19 20 #if defined(CONFIG_P1020MBG) 21 #define CONFIG_BOARDNAME "P1020MBG-PC" 22 #define CONFIG_P1020 23 #define CONFIG_VSC7385_ENET 24 #define CONFIG_SLIC 25 #define __SW_BOOT_MASK 0x03 26 #define __SW_BOOT_NOR 0xe4 27 #define __SW_BOOT_SD 0x54 28 #define CONFIG_SYS_L2_SIZE (256 << 10) 29 #endif 30 31 #if defined(CONFIG_P1020UTM) 32 #define CONFIG_BOARDNAME "P1020UTM-PC" 33 #define CONFIG_P1020 34 #define __SW_BOOT_MASK 0x03 35 #define __SW_BOOT_NOR 0xe0 36 #define __SW_BOOT_SD 0x50 37 #define CONFIG_SYS_L2_SIZE (256 << 10) 38 #endif 39 40 #if defined(CONFIG_P1020RDB_PC) 41 #define CONFIG_BOARDNAME "P1020RDB-PC" 42 #define CONFIG_NAND_FSL_ELBC 43 #define CONFIG_P1020 44 #define CONFIG_SPI_FLASH 45 #define CONFIG_VSC7385_ENET 46 #define CONFIG_SLIC 47 #define __SW_BOOT_MASK 0x03 48 #define __SW_BOOT_NOR 0x5c 49 #define __SW_BOOT_SPI 0x1c 50 #define __SW_BOOT_SD 0x9c 51 #define __SW_BOOT_NAND 0xec 52 #define __SW_BOOT_PCIE 0x6c 53 #define CONFIG_SYS_L2_SIZE (256 << 10) 54 #endif 55 56 /* 57 * P1020RDB-PD board has user selectable switches for evaluating different 58 * frequency and boot options for the P1020 device. The table that 59 * follow describe the available options. The front six binary number was in 60 * accordance with SW3[1:6]. 61 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 62 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 63 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 64 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 65 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 66 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 67 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 68 */ 69 #if defined(CONFIG_P1020RDB_PD) 70 #define CONFIG_BOARDNAME "P1020RDB-PD" 71 #define CONFIG_NAND_FSL_ELBC 72 #define CONFIG_P1020 73 #define CONFIG_SPI_FLASH 74 #define CONFIG_VSC7385_ENET 75 #define CONFIG_SLIC 76 #define __SW_BOOT_MASK 0x03 77 #define __SW_BOOT_NOR 0x64 78 #define __SW_BOOT_SPI 0x34 79 #define __SW_BOOT_SD 0x24 80 #define __SW_BOOT_NAND 0x44 81 #define __SW_BOOT_PCIE 0x74 82 #define CONFIG_SYS_L2_SIZE (256 << 10) 83 #endif 84 85 #if defined(CONFIG_P1021RDB) 86 #define CONFIG_BOARDNAME "P1021RDB-PC" 87 #define CONFIG_NAND_FSL_ELBC 88 #define CONFIG_P1021 89 #define CONFIG_QE 90 #define CONFIG_SPI_FLASH 91 #define CONFIG_VSC7385_ENET 92 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 93 addresses in the LBC */ 94 #define __SW_BOOT_MASK 0x03 95 #define __SW_BOOT_NOR 0x5c 96 #define __SW_BOOT_SPI 0x1c 97 #define __SW_BOOT_SD 0x9c 98 #define __SW_BOOT_NAND 0xec 99 #define __SW_BOOT_PCIE 0x6c 100 #define CONFIG_SYS_L2_SIZE (256 << 10) 101 #endif 102 103 #if defined(CONFIG_P1024RDB) 104 #define CONFIG_BOARDNAME "P1024RDB" 105 #define CONFIG_NAND_FSL_ELBC 106 #define CONFIG_P1024 107 #define CONFIG_SLIC 108 #define CONFIG_SPI_FLASH 109 #define __SW_BOOT_MASK 0xf3 110 #define __SW_BOOT_NOR 0x00 111 #define __SW_BOOT_SPI 0x08 112 #define __SW_BOOT_SD 0x04 113 #define __SW_BOOT_NAND 0x0c 114 #define CONFIG_SYS_L2_SIZE (256 << 10) 115 #endif 116 117 #if defined(CONFIG_P1025RDB) 118 #define CONFIG_BOARDNAME "P1025RDB" 119 #define CONFIG_NAND_FSL_ELBC 120 #define CONFIG_P1025 121 #define CONFIG_QE 122 #define CONFIG_SLIC 123 #define CONFIG_SPI_FLASH 124 125 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 126 addresses in the LBC */ 127 #define __SW_BOOT_MASK 0xf3 128 #define __SW_BOOT_NOR 0x00 129 #define __SW_BOOT_SPI 0x08 130 #define __SW_BOOT_SD 0x04 131 #define __SW_BOOT_NAND 0x0c 132 #define CONFIG_SYS_L2_SIZE (256 << 10) 133 #endif 134 135 #if defined(CONFIG_P2020RDB) 136 #define CONFIG_BOARDNAME "P2020RDB-PCA" 137 #define CONFIG_NAND_FSL_ELBC 138 #define CONFIG_P2020 139 #define CONFIG_SPI_FLASH 140 #define CONFIG_VSC7385_ENET 141 #define __SW_BOOT_MASK 0x03 142 #define __SW_BOOT_NOR 0xc8 143 #define __SW_BOOT_SPI 0x28 144 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 145 #define __SW_BOOT_NAND 0xe8 146 #define __SW_BOOT_PCIE 0xa8 147 #define CONFIG_SYS_L2_SIZE (512 << 10) 148 #endif 149 150 #ifdef CONFIG_SDCARD 151 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 152 #define CONFIG_SPL_ENV_SUPPORT 153 #define CONFIG_SPL_SERIAL_SUPPORT 154 #define CONFIG_SPL_MMC_SUPPORT 155 #define CONFIG_SPL_MMC_MINIMAL 156 #define CONFIG_SPL_FLUSH_IMAGE 157 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 158 #define CONFIG_SPL_LIBGENERIC_SUPPORT 159 #define CONFIG_SPL_LIBCOMMON_SUPPORT 160 #define CONFIG_SPL_I2C_SUPPORT 161 #define CONFIG_FSL_LAW /* Use common FSL init code */ 162 #define CONFIG_SYS_TEXT_BASE 0x11001000 163 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 164 #define CONFIG_SPL_PAD_TO 0x20000 165 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 166 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 167 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 168 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 169 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 170 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 171 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 172 #define CONFIG_SPL_MMC_BOOT 173 #ifdef CONFIG_SPL_BUILD 174 #define CONFIG_SPL_COMMON_INIT_DDR 175 #endif 176 #endif 177 178 #ifdef CONFIG_SPIFLASH 179 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 180 #define CONFIG_SPL_ENV_SUPPORT 181 #define CONFIG_SPL_SERIAL_SUPPORT 182 #define CONFIG_SPL_SPI_SUPPORT 183 #define CONFIG_SPL_SPI_FLASH_SUPPORT 184 #define CONFIG_SPL_SPI_FLASH_MINIMAL 185 #define CONFIG_SPL_FLUSH_IMAGE 186 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 187 #define CONFIG_SPL_LIBGENERIC_SUPPORT 188 #define CONFIG_SPL_LIBCOMMON_SUPPORT 189 #define CONFIG_SPL_I2C_SUPPORT 190 #define CONFIG_FSL_LAW /* Use common FSL init code */ 191 #define CONFIG_SYS_TEXT_BASE 0x11001000 192 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 193 #define CONFIG_SPL_PAD_TO 0x20000 194 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 195 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 196 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 197 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 198 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 199 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 200 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 201 #define CONFIG_SPL_SPI_BOOT 202 #ifdef CONFIG_SPL_BUILD 203 #define CONFIG_SPL_COMMON_INIT_DDR 204 #endif 205 #endif 206 207 #ifdef CONFIG_NAND 208 #ifdef CONFIG_TPL_BUILD 209 #define CONFIG_SPL_NAND_BOOT 210 #define CONFIG_SPL_FLUSH_IMAGE 211 #define CONFIG_SPL_ENV_SUPPORT 212 #define CONFIG_SPL_NAND_INIT 213 #define CONFIG_SPL_SERIAL_SUPPORT 214 #define CONFIG_SPL_LIBGENERIC_SUPPORT 215 #define CONFIG_SPL_LIBCOMMON_SUPPORT 216 #define CONFIG_SPL_I2C_SUPPORT 217 #define CONFIG_SPL_NAND_SUPPORT 218 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 219 #define CONFIG_SPL_COMMON_INIT_DDR 220 #define CONFIG_SPL_MAX_SIZE (128 << 10) 221 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 222 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 223 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 224 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 225 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 226 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 227 #elif defined(CONFIG_SPL_BUILD) 228 #define CONFIG_SPL_INIT_MINIMAL 229 #define CONFIG_SPL_SERIAL_SUPPORT 230 #define CONFIG_SPL_NAND_SUPPORT 231 #define CONFIG_SPL_FLUSH_IMAGE 232 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 233 #define CONFIG_SPL_TEXT_BASE 0xff800000 234 #define CONFIG_SPL_MAX_SIZE 4096 235 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 236 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 237 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 238 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 239 #endif /* not CONFIG_TPL_BUILD */ 240 241 #define CONFIG_SPL_PAD_TO 0x20000 242 #define CONFIG_TPL_PAD_TO 0x20000 243 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 244 #define CONFIG_SYS_TEXT_BASE 0x11001000 245 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 246 #endif 247 248 #ifndef CONFIG_SYS_TEXT_BASE 249 #define CONFIG_SYS_TEXT_BASE 0xeff40000 250 #endif 251 252 #ifndef CONFIG_RESET_VECTOR_ADDRESS 253 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 254 #endif 255 256 #ifndef CONFIG_SYS_MONITOR_BASE 257 #ifdef CONFIG_SPL_BUILD 258 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 259 #else 260 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 261 #endif 262 #endif 263 264 /* High Level Configuration Options */ 265 #define CONFIG_BOOKE 266 #define CONFIG_E500 267 268 #define CONFIG_MP 269 270 #define CONFIG_FSL_ELBC 271 #define CONFIG_PCI 272 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 273 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 274 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 275 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 276 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 277 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 278 279 #define CONFIG_FSL_LAW 280 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 281 #define CONFIG_ENV_OVERWRITE 282 283 #define CONFIG_CMD_SATA 284 #define CONFIG_SATA_SIL 285 #define CONFIG_SYS_SATA_MAX_DEVICE 2 286 #define CONFIG_LIBATA 287 #define CONFIG_LBA48 288 289 #if defined(CONFIG_P2020RDB) 290 #define CONFIG_SYS_CLK_FREQ 100000000 291 #else 292 #define CONFIG_SYS_CLK_FREQ 66666666 293 #endif 294 #define CONFIG_DDR_CLK_FREQ 66666666 295 296 #define CONFIG_HWCONFIG 297 /* 298 * These can be toggled for performance analysis, otherwise use default. 299 */ 300 #define CONFIG_L2_CACHE 301 #define CONFIG_BTB 302 303 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 304 305 #define CONFIG_ENABLE_36BIT_PHYS 306 307 #ifdef CONFIG_PHYS_64BIT 308 #define CONFIG_ADDR_MAP 1 309 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 310 #endif 311 312 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 313 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 314 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 315 316 #define CONFIG_SYS_CCSRBAR 0xffe00000 317 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 318 319 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 320 SPL code*/ 321 #ifdef CONFIG_SPL_BUILD 322 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 323 #endif 324 325 /* DDR Setup */ 326 #define CONFIG_SYS_FSL_DDR3 327 #define CONFIG_SYS_DDR_RAW_TIMING 328 #define CONFIG_DDR_SPD 329 #define CONFIG_SYS_SPD_BUS_NUM 1 330 #define SPD_EEPROM_ADDRESS 0x52 331 #undef CONFIG_FSL_DDR_INTERACTIVE 332 333 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 334 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 335 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 336 #else 337 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 338 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 339 #endif 340 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 341 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 342 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 343 344 #define CONFIG_NUM_DDR_CONTROLLERS 1 345 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 346 347 /* Default settings for DDR3 */ 348 #ifndef CONFIG_P2020RDB 349 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 350 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 351 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 352 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 353 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 354 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 355 356 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 357 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 358 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 359 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 360 361 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 362 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 363 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 364 #define CONFIG_SYS_DDR_RCW_1 0x00000000 365 #define CONFIG_SYS_DDR_RCW_2 0x00000000 366 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 367 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 368 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 369 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 370 371 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 372 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 373 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 374 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 375 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 376 #define CONFIG_SYS_DDR_MODE_1 0x40461520 377 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 378 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 379 #endif 380 381 #undef CONFIG_CLOCKS_IN_MHZ 382 383 /* 384 * Memory map 385 * 386 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 387 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 388 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 389 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 390 * (early boot only) 391 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 392 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 393 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 394 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 395 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 396 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 397 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 398 */ 399 400 401 /* 402 * Local Bus Definitions 403 */ 404 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 405 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 406 #define CONFIG_SYS_FLASH_BASE 0xec000000 407 #elif defined(CONFIG_P1020UTM) 408 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 409 #define CONFIG_SYS_FLASH_BASE 0xee000000 410 #else 411 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 412 #define CONFIG_SYS_FLASH_BASE 0xef000000 413 #endif 414 415 416 #ifdef CONFIG_PHYS_64BIT 417 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 418 #else 419 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 420 #endif 421 422 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 423 | BR_PS_16 | BR_V) 424 425 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 426 427 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 428 #define CONFIG_SYS_FLASH_QUIET_TEST 429 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 430 431 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 432 433 #undef CONFIG_SYS_FLASH_CHECKSUM 434 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 435 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 436 437 #define CONFIG_FLASH_CFI_DRIVER 438 #define CONFIG_SYS_FLASH_CFI 439 #define CONFIG_SYS_FLASH_EMPTY_INFO 440 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 441 442 /* Nand Flash */ 443 #ifdef CONFIG_NAND_FSL_ELBC 444 #define CONFIG_SYS_NAND_BASE 0xff800000 445 #ifdef CONFIG_PHYS_64BIT 446 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 447 #else 448 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 449 #endif 450 451 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 452 #define CONFIG_SYS_MAX_NAND_DEVICE 1 453 #define CONFIG_MTD_NAND_VERIFY_WRITE 454 #define CONFIG_CMD_NAND 455 #if defined(CONFIG_P1020RDB_PD) 456 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 457 #else 458 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 459 #endif 460 461 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 462 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 463 | BR_PS_8 /* Port Size = 8 bit */ \ 464 | BR_MS_FCM /* MSEL = FCM */ \ 465 | BR_V) /* valid */ 466 #if defined(CONFIG_P1020RDB_PD) 467 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 468 | OR_FCM_PGS /* Large Page*/ \ 469 | OR_FCM_CSCT \ 470 | OR_FCM_CST \ 471 | OR_FCM_CHT \ 472 | OR_FCM_SCY_1 \ 473 | OR_FCM_TRLX \ 474 | OR_FCM_EHTR) 475 #else 476 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 477 | OR_FCM_CSCT \ 478 | OR_FCM_CST \ 479 | OR_FCM_CHT \ 480 | OR_FCM_SCY_1 \ 481 | OR_FCM_TRLX \ 482 | OR_FCM_EHTR) 483 #endif 484 #endif /* CONFIG_NAND_FSL_ELBC */ 485 486 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 487 488 #define CONFIG_SYS_INIT_RAM_LOCK 489 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 490 #ifdef CONFIG_PHYS_64BIT 491 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 492 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 493 /* The assembler doesn't like typecast */ 494 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 495 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 496 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 497 #else 498 /* Initial L1 address */ 499 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 500 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 501 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 502 #endif 503 /* Size of used area in RAM */ 504 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 505 506 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 507 GENERATED_GBL_DATA_SIZE) 508 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 509 510 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 511 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 512 513 #define CONFIG_SYS_CPLD_BASE 0xffa00000 514 #ifdef CONFIG_PHYS_64BIT 515 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 516 #else 517 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 518 #endif 519 /* CPLD config size: 1Mb */ 520 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 521 BR_PS_8 | BR_V) 522 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 523 524 #define CONFIG_SYS_PMC_BASE 0xff980000 525 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 526 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 527 BR_PS_8 | BR_V) 528 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 529 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 530 OR_GPCM_EAD) 531 532 #ifdef CONFIG_NAND 533 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 534 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 535 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 536 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 537 #else 538 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 539 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 540 #ifdef CONFIG_NAND_FSL_ELBC 541 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 542 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 543 #endif 544 #endif 545 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 546 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 547 548 549 /* Vsc7385 switch */ 550 #ifdef CONFIG_VSC7385_ENET 551 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 552 553 #ifdef CONFIG_PHYS_64BIT 554 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 555 #else 556 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 557 #endif 558 559 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 560 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 561 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 562 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 563 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 564 565 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 566 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 567 568 /* The size of the VSC7385 firmware image */ 569 #define CONFIG_VSC7385_IMAGE_SIZE 8192 570 #endif 571 572 /* 573 * Config the L2 Cache as L2 SRAM 574 */ 575 #if defined(CONFIG_SPL_BUILD) 576 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 577 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 578 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 579 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 580 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 581 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 582 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 583 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 584 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 585 #if defined(CONFIG_P2020RDB) 586 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 587 #else 588 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 589 #endif 590 #elif defined(CONFIG_NAND) 591 #ifdef CONFIG_TPL_BUILD 592 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 593 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 594 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 595 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 596 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 597 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 598 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 599 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 600 #else 601 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 602 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 603 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 604 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 605 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 606 #endif /* CONFIG_TPL_BUILD */ 607 #endif 608 #endif 609 610 /* Serial Port - controlled on board with jumper J8 611 * open - index 2 612 * shorted - index 1 613 */ 614 #define CONFIG_CONS_INDEX 1 615 #undef CONFIG_SERIAL_SOFTWARE_FIFO 616 #define CONFIG_SYS_NS16550 617 #define CONFIG_SYS_NS16550_SERIAL 618 #define CONFIG_SYS_NS16550_REG_SIZE 1 619 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 620 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 621 #define CONFIG_NS16550_MIN_FUNCTIONS 622 #endif 623 624 #define CONFIG_SYS_BAUDRATE_TABLE \ 625 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 626 627 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 628 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 629 630 /* Use the HUSH parser */ 631 #define CONFIG_SYS_HUSH_PARSER 632 633 /* 634 * Pass open firmware flat tree 635 */ 636 #define CONFIG_OF_LIBFDT 637 #define CONFIG_OF_BOARD_SETUP 638 #define CONFIG_OF_STDOUT_VIA_ALIAS 639 640 /* new uImage format support */ 641 #define CONFIG_FIT 642 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 643 644 /* I2C */ 645 #define CONFIG_SYS_I2C 646 #define CONFIG_SYS_I2C_FSL 647 #define CONFIG_SYS_FSL_I2C_SPEED 400000 648 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 649 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 650 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 651 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 652 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 653 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 654 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 655 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 656 657 /* 658 * I2C2 EEPROM 659 */ 660 #undef CONFIG_ID_EEPROM 661 662 #define CONFIG_RTC_PT7C4338 663 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 664 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 665 666 /* enable read and write access to EEPROM */ 667 #define CONFIG_CMD_EEPROM 668 #define CONFIG_SYS_I2C_MULTI_EEPROMS 669 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 670 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 671 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 672 673 /* 674 * eSPI - Enhanced SPI 675 */ 676 #define CONFIG_HARD_SPI 677 #define CONFIG_FSL_ESPI 678 679 #if defined(CONFIG_SPI_FLASH) 680 #define CONFIG_SPI_FLASH_SPANSION 681 #define CONFIG_CMD_SF 682 #define CONFIG_SF_DEFAULT_SPEED 10000000 683 #define CONFIG_SF_DEFAULT_MODE 0 684 #endif 685 686 #if defined(CONFIG_PCI) 687 /* 688 * General PCI 689 * Memory space is mapped 1-1, but I/O space must start from 0. 690 */ 691 692 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 693 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 694 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 695 #ifdef CONFIG_PHYS_64BIT 696 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 697 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 698 #else 699 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 700 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 701 #endif 702 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 703 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 704 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 705 #ifdef CONFIG_PHYS_64BIT 706 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 707 #else 708 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 709 #endif 710 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 711 712 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 713 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 714 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 715 #ifdef CONFIG_PHYS_64BIT 716 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 717 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 718 #else 719 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 720 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 721 #endif 722 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 723 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 724 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 725 #ifdef CONFIG_PHYS_64BIT 726 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 727 #else 728 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 729 #endif 730 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 731 732 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 733 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ 734 #define CONFIG_CMD_PCI 735 #define CONFIG_CMD_NET 736 737 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 738 #define CONFIG_DOS_PARTITION 739 #endif /* CONFIG_PCI */ 740 741 #if defined(CONFIG_TSEC_ENET) 742 #define CONFIG_MII /* MII PHY management */ 743 #define CONFIG_TSEC1 744 #define CONFIG_TSEC1_NAME "eTSEC1" 745 #define CONFIG_TSEC2 746 #define CONFIG_TSEC2_NAME "eTSEC2" 747 #define CONFIG_TSEC3 748 #define CONFIG_TSEC3_NAME "eTSEC3" 749 750 #define TSEC1_PHY_ADDR 2 751 #define TSEC2_PHY_ADDR 0 752 #define TSEC3_PHY_ADDR 1 753 754 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 755 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 756 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 757 758 #define TSEC1_PHYIDX 0 759 #define TSEC2_PHYIDX 0 760 #define TSEC3_PHYIDX 0 761 762 #define CONFIG_ETHPRIME "eTSEC1" 763 764 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 765 766 #define CONFIG_HAS_ETH0 767 #define CONFIG_HAS_ETH1 768 #define CONFIG_HAS_ETH2 769 #endif /* CONFIG_TSEC_ENET */ 770 771 #ifdef CONFIG_QE 772 /* QE microcode/firmware address */ 773 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 774 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 775 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 776 #endif /* CONFIG_QE */ 777 778 #ifdef CONFIG_P1025RDB 779 /* 780 * QE UEC ethernet configuration 781 */ 782 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 783 784 #undef CONFIG_UEC_ETH 785 #define CONFIG_PHY_MODE_NEED_CHANGE 786 787 #define CONFIG_UEC_ETH1 /* ETH1 */ 788 #define CONFIG_HAS_ETH0 789 790 #ifdef CONFIG_UEC_ETH1 791 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 792 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 793 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 794 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 795 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 796 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 797 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 798 #endif /* CONFIG_UEC_ETH1 */ 799 800 #define CONFIG_UEC_ETH5 /* ETH5 */ 801 #define CONFIG_HAS_ETH1 802 803 #ifdef CONFIG_UEC_ETH5 804 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 805 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 806 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 807 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 808 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 809 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 810 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 811 #endif /* CONFIG_UEC_ETH5 */ 812 #endif /* CONFIG_P1025RDB */ 813 814 /* 815 * Environment 816 */ 817 #ifdef CONFIG_SPIFLASH 818 #define CONFIG_ENV_IS_IN_SPI_FLASH 819 #define CONFIG_ENV_SPI_BUS 0 820 #define CONFIG_ENV_SPI_CS 0 821 #define CONFIG_ENV_SPI_MAX_HZ 10000000 822 #define CONFIG_ENV_SPI_MODE 0 823 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 824 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 825 #define CONFIG_ENV_SECT_SIZE 0x10000 826 #elif defined(CONFIG_SDCARD) 827 #define CONFIG_ENV_IS_IN_MMC 828 #define CONFIG_FSL_FIXED_MMC_LOCATION 829 #define CONFIG_ENV_SIZE 0x2000 830 #define CONFIG_SYS_MMC_ENV_DEV 0 831 #elif defined(CONFIG_NAND) 832 #ifdef CONFIG_TPL_BUILD 833 #define CONFIG_ENV_SIZE 0x2000 834 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 835 #else 836 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 837 #endif 838 #define CONFIG_ENV_IS_IN_NAND 839 #define CONFIG_ENV_OFFSET (1024 * 1024) 840 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 841 #elif defined(CONFIG_SYS_RAMBOOT) 842 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 843 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 844 #define CONFIG_ENV_SIZE 0x2000 845 #else 846 #define CONFIG_ENV_IS_IN_FLASH 847 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 848 #define CONFIG_ENV_SIZE 0x2000 849 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 850 #endif 851 852 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 853 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 854 855 /* 856 * Command line configuration. 857 */ 858 #include <config_cmd_default.h> 859 860 #define CONFIG_CMD_IRQ 861 #define CONFIG_CMD_PING 862 #define CONFIG_CMD_I2C 863 #define CONFIG_CMD_MII 864 #define CONFIG_CMD_DATE 865 #define CONFIG_CMD_ELF 866 #define CONFIG_CMD_SETEXPR 867 #define CONFIG_CMD_REGINFO 868 869 /* 870 * USB 871 */ 872 #define CONFIG_HAS_FSL_DR_USB 873 874 #if defined(CONFIG_HAS_FSL_DR_USB) 875 #define CONFIG_USB_EHCI 876 877 #ifdef CONFIG_USB_EHCI 878 #define CONFIG_CMD_USB 879 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 880 #define CONFIG_USB_EHCI_FSL 881 #define CONFIG_USB_STORAGE 882 #endif 883 #endif 884 885 #if defined(CONFIG_P1020RDB_PD) 886 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 887 #endif 888 889 #define CONFIG_MMC 890 891 #ifdef CONFIG_MMC 892 #define CONFIG_FSL_ESDHC 893 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 894 #define CONFIG_CMD_MMC 895 #define CONFIG_GENERIC_MMC 896 #endif 897 898 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 899 || defined(CONFIG_FSL_SATA) 900 #define CONFIG_CMD_EXT2 901 #define CONFIG_CMD_FAT 902 #define CONFIG_DOS_PARTITION 903 #endif 904 905 #undef CONFIG_WATCHDOG /* watchdog disabled */ 906 907 /* 908 * Miscellaneous configurable options 909 */ 910 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 911 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 912 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 913 #if defined(CONFIG_CMD_KGDB) 914 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 915 #else 916 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 917 #endif 918 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 919 /* Print Buffer Size */ 920 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 921 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 922 923 /* 924 * For booting Linux, the board info and command line data 925 * have to be in the first 64 MB of memory, since this is 926 * the maximum mapped by the Linux kernel during initialization. 927 */ 928 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 929 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 930 931 #if defined(CONFIG_CMD_KGDB) 932 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 933 #endif 934 935 /* 936 * Environment Configuration 937 */ 938 #define CONFIG_HOSTNAME unknown 939 #define CONFIG_ROOTPATH "/opt/nfsroot" 940 #define CONFIG_BOOTFILE "uImage" 941 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 942 943 /* default location for tftp and bootm */ 944 #define CONFIG_LOADADDR 1000000 945 946 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 947 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 948 949 #define CONFIG_BAUDRATE 115200 950 951 #ifdef __SW_BOOT_NOR 952 #define __NOR_RST_CMD \ 953 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 954 i2c mw 18 3 __SW_BOOT_MASK 1; reset 955 #endif 956 #ifdef __SW_BOOT_SPI 957 #define __SPI_RST_CMD \ 958 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 959 i2c mw 18 3 __SW_BOOT_MASK 1; reset 960 #endif 961 #ifdef __SW_BOOT_SD 962 #define __SD_RST_CMD \ 963 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 964 i2c mw 18 3 __SW_BOOT_MASK 1; reset 965 #endif 966 #ifdef __SW_BOOT_NAND 967 #define __NAND_RST_CMD \ 968 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 969 i2c mw 18 3 __SW_BOOT_MASK 1; reset 970 #endif 971 #ifdef __SW_BOOT_PCIE 972 #define __PCIE_RST_CMD \ 973 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 974 i2c mw 18 3 __SW_BOOT_MASK 1; reset 975 #endif 976 977 #define CONFIG_EXTRA_ENV_SETTINGS \ 978 "netdev=eth0\0" \ 979 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 980 "loadaddr=1000000\0" \ 981 "bootfile=uImage\0" \ 982 "tftpflash=tftpboot $loadaddr $uboot; " \ 983 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 984 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 985 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 986 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 987 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 988 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 989 "consoledev=ttyS0\0" \ 990 "ramdiskaddr=2000000\0" \ 991 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 992 "fdtaddr=c00000\0" \ 993 "bdev=sda1\0" \ 994 "jffs2nor=mtdblock3\0" \ 995 "norbootaddr=ef080000\0" \ 996 "norfdtaddr=ef040000\0" \ 997 "jffs2nand=mtdblock9\0" \ 998 "nandbootaddr=100000\0" \ 999 "nandfdtaddr=80000\0" \ 1000 "ramdisk_size=120000\0" \ 1001 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 1002 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 1003 __stringify(__NOR_RST_CMD)"\0" \ 1004 __stringify(__SPI_RST_CMD)"\0" \ 1005 __stringify(__SD_RST_CMD)"\0" \ 1006 __stringify(__NAND_RST_CMD)"\0" \ 1007 __stringify(__PCIE_RST_CMD)"\0" 1008 1009 #define CONFIG_NFSBOOTCOMMAND \ 1010 "setenv bootargs root=/dev/nfs rw " \ 1011 "nfsroot=$serverip:$rootpath " \ 1012 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 1013 "console=$consoledev,$baudrate $othbootargs;" \ 1014 "tftp $loadaddr $bootfile;" \ 1015 "tftp $fdtaddr $fdtfile;" \ 1016 "bootm $loadaddr - $fdtaddr" 1017 1018 #define CONFIG_HDBOOT \ 1019 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 1020 "console=$consoledev,$baudrate $othbootargs;" \ 1021 "usb start;" \ 1022 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 1023 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 1024 "bootm $loadaddr - $fdtaddr" 1025 1026 #define CONFIG_USB_FAT_BOOT \ 1027 "setenv bootargs root=/dev/ram rw " \ 1028 "console=$consoledev,$baudrate $othbootargs " \ 1029 "ramdisk_size=$ramdisk_size;" \ 1030 "usb start;" \ 1031 "fatload usb 0:2 $loadaddr $bootfile;" \ 1032 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 1033 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 1034 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1035 1036 #define CONFIG_USB_EXT2_BOOT \ 1037 "setenv bootargs root=/dev/ram rw " \ 1038 "console=$consoledev,$baudrate $othbootargs " \ 1039 "ramdisk_size=$ramdisk_size;" \ 1040 "usb start;" \ 1041 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1042 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1043 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1044 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1045 1046 #define CONFIG_NORBOOT \ 1047 "setenv bootargs root=/dev/$jffs2nor rw " \ 1048 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1049 "bootm $norbootaddr - $norfdtaddr" 1050 1051 #define CONFIG_RAMBOOTCOMMAND \ 1052 "setenv bootargs root=/dev/ram rw " \ 1053 "console=$consoledev,$baudrate $othbootargs " \ 1054 "ramdisk_size=$ramdisk_size;" \ 1055 "tftp $ramdiskaddr $ramdiskfile;" \ 1056 "tftp $loadaddr $bootfile;" \ 1057 "tftp $fdtaddr $fdtfile;" \ 1058 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1059 1060 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1061 1062 #endif /* __CONFIG_H */ 1063