1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. 4 * Copyright (C) 2014 Bachmann electronic GmbH 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #include "mx6_common.h" 11 12 /* Size of malloc() pool */ 13 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 14 15 /* UART Configs */ 16 #define CONFIG_MXC_UART 17 #define CONFIG_MXC_UART_BASE UART1_BASE 18 19 /* SF Configs */ 20 #define CONFIG_SF_DEFAULT_BUS 2 21 #define CONFIG_SF_DEFAULT_CS 0 22 #define CONFIG_SF_DEFAULT_SPEED 25000000 23 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 24 25 /* IO expander */ 26 #define CONFIG_PCA953X 27 #define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 28 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } 29 30 /* I2C Configs */ 31 #define CONFIG_SYS_I2C 32 #define CONFIG_SYS_I2C_MXC 33 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 34 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 35 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 36 #define CONFIG_SYS_I2C_SPEED 100000 37 38 /* OCOTP Configs */ 39 #define CONFIG_IMX_OTP 40 #define IMX_OTP_BASE OCOTP_BASE_ADDR 41 #define IMX_OTP_ADDR_MAX 0x7F 42 #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA 43 #define IMX_OTPWRITE_ENABLED 44 45 /* MMC Configs */ 46 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 47 #define CONFIG_SYS_FSL_USDHC_NUM 2 48 49 /* USB Configs */ 50 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 51 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 52 53 /* 54 * SATA Configs 55 */ 56 #ifdef CONFIG_CMD_SATA 57 #define CONFIG_SYS_SATA_MAX_DEVICE 1 58 #define CONFIG_DWC_AHSATA_PORT_ID 0 59 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 60 #define CONFIG_LBA48 61 #endif 62 63 /* SPL */ 64 #ifdef CONFIG_SPL 65 #include "imx6_spl.h" 66 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) 67 #endif 68 69 #define CONFIG_FEC_MXC 70 #define IMX_FEC_BASE ENET_BASE_ADDR 71 #define CONFIG_FEC_XCV_TYPE MII100 72 #define CONFIG_ETHPRIME "FEC" 73 #define CONFIG_FEC_MXC_PHYADDR 0x5 74 #define CONFIG_PHY_SMSC 75 76 #ifndef CONFIG_SPL 77 #define CONFIG_ENV_EEPROM_IS_ON_I2C 78 #define CONFIG_SYS_I2C_EEPROM_BUS 1 79 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 80 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 81 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 82 #endif 83 84 #define CONFIG_PREBOOT "" 85 86 /* Thermal support */ 87 #define CONFIG_IMX_THERMAL 88 89 /* Physical Memory Map */ 90 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 91 92 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 93 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 94 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 95 96 #define CONFIG_SYS_INIT_SP_OFFSET \ 97 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 98 #define CONFIG_SYS_INIT_SP_ADDR \ 99 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 100 101 /* Environment organization */ 102 #define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */ 103 #define CONFIG_ENV_OFFSET (1024 * 1024) 104 /* M25P16 has an erase size of 64 KiB */ 105 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 106 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 107 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 108 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 109 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 110 111 #define CONFIG_BOOTP_SERVERIP 112 #define CONFIG_BOOTP_BOOTFILE 113 114 #endif /* __CONFIG_H */ 115