1 /* 2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. 3 * Copyright (C) 2014 Bachmann electronic GmbH 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 #include "mx6_common.h" 12 13 /* Size of malloc() pool */ 14 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 15 16 #define CONFIG_MISC_INIT_R 17 18 /* UART Configs */ 19 #define CONFIG_MXC_UART 20 #define CONFIG_MXC_UART_BASE UART1_BASE 21 22 /* SF Configs */ 23 #define CONFIG_SPI 24 #define CONFIG_MXC_SPI 25 #define CONFIG_SF_DEFAULT_BUS 2 26 #define CONFIG_SF_DEFAULT_CS 0 27 #define CONFIG_SF_DEFAULT_SPEED 25000000 28 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 29 30 /* IO expander */ 31 #define CONFIG_PCA953X 32 #define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 33 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } 34 35 /* I2C Configs */ 36 #define CONFIG_SYS_I2C 37 #define CONFIG_SYS_I2C_MXC 38 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 39 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 40 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 41 #define CONFIG_SYS_I2C_SPEED 100000 42 43 /* OCOTP Configs */ 44 #define CONFIG_IMX_OTP 45 #define IMX_OTP_BASE OCOTP_BASE_ADDR 46 #define IMX_OTP_ADDR_MAX 0x7F 47 #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA 48 #define IMX_OTPWRITE_ENABLED 49 50 /* MMC Configs */ 51 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 52 #define CONFIG_SYS_FSL_USDHC_NUM 2 53 54 /* USB Configs */ 55 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 56 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 57 58 /* 59 * SATA Configs 60 */ 61 #ifdef CONFIG_CMD_SATA 62 #define CONFIG_DWC_AHSATA 63 #define CONFIG_SYS_SATA_MAX_DEVICE 1 64 #define CONFIG_DWC_AHSATA_PORT_ID 0 65 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 66 #define CONFIG_LBA48 67 #define CONFIG_LIBATA 68 #endif 69 70 /* SPL */ 71 #ifdef CONFIG_SPL 72 #include "imx6_spl.h" 73 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) 74 #define CONFIG_SPL_SPI_LOAD 75 #endif 76 77 #define CONFIG_FEC_MXC 78 #define CONFIG_MII 79 #define IMX_FEC_BASE ENET_BASE_ADDR 80 #define CONFIG_FEC_XCV_TYPE MII100 81 #define CONFIG_ETHPRIME "FEC" 82 #define CONFIG_FEC_MXC_PHYADDR 0x5 83 #define CONFIG_PHY_SMSC 84 85 #ifndef CONFIG_SPL 86 #define CONFIG_ENV_EEPROM_IS_ON_I2C 87 #define CONFIG_SYS_I2C_EEPROM_BUS 1 88 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 89 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 90 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 91 #endif 92 93 #define CONFIG_PREBOOT "" 94 95 /* Thermal support */ 96 #define CONFIG_IMX_THERMAL 97 98 /* Print Buffer Size */ 99 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 100 101 /* Physical Memory Map */ 102 #define CONFIG_NR_DRAM_BANKS 1 103 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 104 105 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 106 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 107 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 108 109 #define CONFIG_SYS_INIT_SP_OFFSET \ 110 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 111 #define CONFIG_SYS_INIT_SP_ADDR \ 112 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 113 114 /* Environment organization */ 115 #define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */ 116 #define CONFIG_ENV_OFFSET (1024 * 1024) 117 /* M25P16 has an erase size of 64 KiB */ 118 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 119 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 120 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 121 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 122 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 123 124 #define CONFIG_BOOTP_SERVERIP 125 #define CONFIG_BOOTP_BOOTFILE 126 127 #endif /* __CONFIG_H */ 128