1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. 4 * Copyright (C) 2014 Bachmann electronic GmbH 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #include "mx6_common.h" 11 12 /* Size of malloc() pool */ 13 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 14 15 #define CONFIG_MISC_INIT_R 16 17 /* UART Configs */ 18 #define CONFIG_MXC_UART 19 #define CONFIG_MXC_UART_BASE UART1_BASE 20 21 /* SF Configs */ 22 #define CONFIG_SF_DEFAULT_BUS 2 23 #define CONFIG_SF_DEFAULT_CS 0 24 #define CONFIG_SF_DEFAULT_SPEED 25000000 25 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 26 27 /* IO expander */ 28 #define CONFIG_PCA953X 29 #define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 30 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } 31 32 /* I2C Configs */ 33 #define CONFIG_SYS_I2C 34 #define CONFIG_SYS_I2C_MXC 35 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 36 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 37 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 38 #define CONFIG_SYS_I2C_SPEED 100000 39 40 /* OCOTP Configs */ 41 #define CONFIG_IMX_OTP 42 #define IMX_OTP_BASE OCOTP_BASE_ADDR 43 #define IMX_OTP_ADDR_MAX 0x7F 44 #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA 45 #define IMX_OTPWRITE_ENABLED 46 47 /* MMC Configs */ 48 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 49 #define CONFIG_SYS_FSL_USDHC_NUM 2 50 51 /* USB Configs */ 52 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 53 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 54 55 /* 56 * SATA Configs 57 */ 58 #ifdef CONFIG_CMD_SATA 59 #define CONFIG_SYS_SATA_MAX_DEVICE 1 60 #define CONFIG_DWC_AHSATA_PORT_ID 0 61 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 62 #define CONFIG_LBA48 63 #endif 64 65 /* SPL */ 66 #ifdef CONFIG_SPL 67 #include "imx6_spl.h" 68 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) 69 #endif 70 71 #define CONFIG_FEC_MXC 72 #define CONFIG_MII 73 #define IMX_FEC_BASE ENET_BASE_ADDR 74 #define CONFIG_FEC_XCV_TYPE MII100 75 #define CONFIG_ETHPRIME "FEC" 76 #define CONFIG_FEC_MXC_PHYADDR 0x5 77 #define CONFIG_PHY_SMSC 78 79 #ifndef CONFIG_SPL 80 #define CONFIG_ENV_EEPROM_IS_ON_I2C 81 #define CONFIG_SYS_I2C_EEPROM_BUS 1 82 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 83 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 84 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 85 #endif 86 87 #define CONFIG_PREBOOT "" 88 89 /* Thermal support */ 90 #define CONFIG_IMX_THERMAL 91 92 /* Physical Memory Map */ 93 #define CONFIG_NR_DRAM_BANKS 1 94 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 95 96 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 97 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 98 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 99 100 #define CONFIG_SYS_INIT_SP_OFFSET \ 101 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 102 #define CONFIG_SYS_INIT_SP_ADDR \ 103 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 104 105 /* Environment organization */ 106 #define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */ 107 #define CONFIG_ENV_OFFSET (1024 * 1024) 108 /* M25P16 has an erase size of 64 KiB */ 109 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 110 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 111 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 112 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 113 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 114 115 #define CONFIG_BOOTP_SERVERIP 116 #define CONFIG_BOOTP_BOOTFILE 117 118 #endif /* __CONFIG_H */ 119