1b9a1ef21SChander Kashyap /* 2b9a1ef21SChander Kashyap * Copyright (C) 2011 Samsung Electronics 3b9a1ef21SChander Kashyap * 4393cb361SChander Kashyap * Configuration settings for the SAMSUNG ORIGEN (EXYNOS4210) board. 5b9a1ef21SChander Kashyap * 6*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 7b9a1ef21SChander Kashyap */ 8b9a1ef21SChander Kashyap 9b9a1ef21SChander Kashyap #ifndef __CONFIG_H 10b9a1ef21SChander Kashyap #define __CONFIG_H 11b9a1ef21SChander Kashyap 12b9a1ef21SChander Kashyap /* High Level Configuration Options */ 13b9a1ef21SChander Kashyap #define CONFIG_SAMSUNG 1 /* SAMSUNG core */ 14b9a1ef21SChander Kashyap #define CONFIG_S5P 1 /* S5P Family */ 15393cb361SChander Kashyap #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ 16b9a1ef21SChander Kashyap #define CONFIG_ORIGEN 1 /* working with ORIGEN*/ 17b9a1ef21SChander Kashyap 18b9a1ef21SChander Kashyap #include <asm/arch/cpu.h> /* get chip and board defs */ 19b9a1ef21SChander Kashyap 20b9a1ef21SChander Kashyap #define CONFIG_ARCH_CPU_INIT 21b9a1ef21SChander Kashyap #define CONFIG_DISPLAY_CPUINFO 22b9a1ef21SChander Kashyap #define CONFIG_DISPLAY_BOARDINFO 23198a40b9SRajeshwari Shinde #define CONFIG_BOARD_EARLY_INIT_F 24b9a1ef21SChander Kashyap 25b9a1ef21SChander Kashyap /* Keep L2 Cache Disabled */ 26b9a1ef21SChander Kashyap #define CONFIG_L2_OFF 1 27b9a1ef21SChander Kashyap #define CONFIG_SYS_DCACHE_OFF 1 28b9a1ef21SChander Kashyap 29b9a1ef21SChander Kashyap #define CONFIG_SYS_SDRAM_BASE 0x40000000 30b9a1ef21SChander Kashyap #define CONFIG_SYS_TEXT_BASE 0x43E00000 31b9a1ef21SChander Kashyap 32b9a1ef21SChander Kashyap /* input clock of PLL: ORIGEN has 24MHz input clock */ 33b9a1ef21SChander Kashyap #define CONFIG_SYS_CLK_FREQ 24000000 34b9a1ef21SChander Kashyap 35b9a1ef21SChander Kashyap #define CONFIG_SETUP_MEMORY_TAGS 36b9a1ef21SChander Kashyap #define CONFIG_CMDLINE_TAG 37b9a1ef21SChander Kashyap #define CONFIG_INITRD_TAG 38b9a1ef21SChander Kashyap #define CONFIG_CMDLINE_EDITING 39b9a1ef21SChander Kashyap 40b9a1ef21SChander Kashyap #define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN 41b9a1ef21SChander Kashyap 42b9a1ef21SChander Kashyap /* Power Down Modes */ 43b9a1ef21SChander Kashyap #define S5P_CHECK_SLEEP 0x00000BAD 44b9a1ef21SChander Kashyap #define S5P_CHECK_DIDLE 0xBAD00000 45b9a1ef21SChander Kashyap #define S5P_CHECK_LPA 0xABAD0000 46b9a1ef21SChander Kashyap 47b9a1ef21SChander Kashyap /* Size of malloc() pool */ 48b9a1ef21SChander Kashyap #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) 49b9a1ef21SChander Kashyap 50b9a1ef21SChander Kashyap /* select serial console configuration */ 51b9a1ef21SChander Kashyap #define CONFIG_SERIAL2 1 /* use SERIAL 2 */ 52b9a1ef21SChander Kashyap #define CONFIG_BAUDRATE 115200 53393cb361SChander Kashyap #define EXYNOS4_DEFAULT_UART_OFFSET 0x020000 54b9a1ef21SChander Kashyap 55643be9c0SRajeshwari Shinde #define CONFIG_SKIP_LOWLEVEL_INIT 56643be9c0SRajeshwari Shinde 57b9a1ef21SChander Kashyap /* SD/MMC configuration */ 587d2d58b4SJaehoon Chung #define CONFIG_GENERIC_MMC 597d2d58b4SJaehoon Chung #define CONFIG_MMC 607d2d58b4SJaehoon Chung #define CONFIG_SDHCI 617d2d58b4SJaehoon Chung #define CONFIG_S5P_SDHCI 62b9a1ef21SChander Kashyap 63b9a1ef21SChander Kashyap /* PWM */ 64b9a1ef21SChander Kashyap #define CONFIG_PWM 1 65b9a1ef21SChander Kashyap 66b9a1ef21SChander Kashyap /* allow to overwrite serial and ethaddr */ 67b9a1ef21SChander Kashyap #define CONFIG_ENV_OVERWRITE 68b9a1ef21SChander Kashyap 69b9a1ef21SChander Kashyap /* Command definition*/ 70b9a1ef21SChander Kashyap #include <config_cmd_default.h> 71b9a1ef21SChander Kashyap 7280615006SJoe Hershberger #undef CONFIG_CMD_PING 73b9a1ef21SChander Kashyap #define CONFIG_CMD_ELF 74b9a1ef21SChander Kashyap #define CONFIG_CMD_DHCP 75b9a1ef21SChander Kashyap #define CONFIG_CMD_MMC 76b9a1ef21SChander Kashyap #define CONFIG_CMD_FAT 77b9a1ef21SChander Kashyap #undef CONFIG_CMD_NET 78b9a1ef21SChander Kashyap #undef CONFIG_CMD_NFS 79b9a1ef21SChander Kashyap 80b9a1ef21SChander Kashyap #define CONFIG_BOOTDELAY 3 81b9a1ef21SChander Kashyap #define CONFIG_ZERO_BOOTDELAY_CHECK 8298a48c5dSChander Kashyap /* MMC SPL */ 8398a48c5dSChander Kashyap #define CONFIG_SPL 8498a48c5dSChander Kashyap #define COPY_BL2_FNPTR_ADDR 0x02020030 85b9a1ef21SChander Kashyap 868a00061eSInderpal Singh #define CONFIG_SPL_TEXT_BASE 0x02021410 878a00061eSInderpal Singh 88b9a1ef21SChander Kashyap #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" 89b9a1ef21SChander Kashyap 90b9a1ef21SChander Kashyap /* Miscellaneous configurable options */ 91b9a1ef21SChander Kashyap #define CONFIG_SYS_LONGHELP /* undef to save memory */ 92b9a1ef21SChander Kashyap #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 93b9a1ef21SChander Kashyap #define CONFIG_SYS_PROMPT "ORIGEN # " 94b9a1ef21SChander Kashyap #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/ 95b9a1ef21SChander Kashyap #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ 96b9a1ef21SChander Kashyap #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 97b9a1ef21SChander Kashyap #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" 98b9a1ef21SChander Kashyap /* Boot Argument Buffer Size */ 99b9a1ef21SChander Kashyap #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 100b9a1ef21SChander Kashyap /* memtest works on */ 101b9a1ef21SChander Kashyap #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 102b9a1ef21SChander Kashyap #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) 103b9a1ef21SChander Kashyap #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) 104b9a1ef21SChander Kashyap 105b9a1ef21SChander Kashyap #define CONFIG_SYS_HZ 1000 106b9a1ef21SChander Kashyap 107b9a1ef21SChander Kashyap /* ORIGEN has 4 bank of DRAM */ 108b9a1ef21SChander Kashyap #define CONFIG_NR_DRAM_BANKS 4 109b9a1ef21SChander Kashyap #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ 110b9a1ef21SChander Kashyap #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 111b9a1ef21SChander Kashyap #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE 112b9a1ef21SChander Kashyap #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) 113b9a1ef21SChander Kashyap #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE 114b9a1ef21SChander Kashyap #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) 115b9a1ef21SChander Kashyap #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE 116b9a1ef21SChander Kashyap #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) 117b9a1ef21SChander Kashyap #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE 118b9a1ef21SChander Kashyap 119b9a1ef21SChander Kashyap /* FLASH and environment organization */ 120b9a1ef21SChander Kashyap #define CONFIG_SYS_NO_FLASH 1 121b9a1ef21SChander Kashyap #undef CONFIG_CMD_IMLS 122b9a1ef21SChander Kashyap #define CONFIG_IDENT_STRING " for ORIGEN" 123b9a1ef21SChander Kashyap 124b9a1ef21SChander Kashyap #define CONFIG_CLK_1000_400_200 125b9a1ef21SChander Kashyap 126b9a1ef21SChander Kashyap /* MIU (Memory Interleaving Unit) */ 127b9a1ef21SChander Kashyap #define CONFIG_MIU_2BIT_21_7_INTERLEAVED 128b9a1ef21SChander Kashyap 129b9a1ef21SChander Kashyap #define CONFIG_ENV_IS_IN_MMC 1 130b9a1ef21SChander Kashyap #define CONFIG_SYS_MMC_ENV_DEV 0 131b9a1ef21SChander Kashyap #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ 132b9a1ef21SChander Kashyap #define RESERVE_BLOCK_SIZE (512) 133b9a1ef21SChander Kashyap #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ 134b9a1ef21SChander Kashyap #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) 135b9a1ef21SChander Kashyap #define CONFIG_DOS_PARTITION 1 136b9a1ef21SChander Kashyap 137643be9c0SRajeshwari Shinde #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" 138643be9c0SRajeshwari Shinde #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) 139643be9c0SRajeshwari Shinde 140643be9c0SRajeshwari Shinde #define CONFIG_SYS_INIT_SP_ADDR 0x02040000 14198a48c5dSChander Kashyap 14298a48c5dSChander Kashyap /* U-boot copy size from boot Media to DRAM.*/ 14398a48c5dSChander Kashyap #define COPY_BL2_SIZE 0x80000 14498a48c5dSChander Kashyap #define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) 14598a48c5dSChander Kashyap #define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) 146099e884aSAngus Ainslie 147099e884aSAngus Ainslie /* Enable devicetree support */ 148099e884aSAngus Ainslie #define CONFIG_OF_LIBFDT 149643be9c0SRajeshwari Shinde 150b9a1ef21SChander Kashyap #endif /* __CONFIG_H */ 151