1b9a1ef21SChander Kashyap /* 2b9a1ef21SChander Kashyap * Copyright (C) 2011 Samsung Electronics 3b9a1ef21SChander Kashyap * 4393cb361SChander Kashyap * Configuration settings for the SAMSUNG ORIGEN (EXYNOS4210) board. 5b9a1ef21SChander Kashyap * 6b9a1ef21SChander Kashyap * See file CREDITS for list of people who contributed to this 7b9a1ef21SChander Kashyap * project. 8b9a1ef21SChander Kashyap * 9b9a1ef21SChander Kashyap * This program is free software; you can redistribute it and/or 10b9a1ef21SChander Kashyap * modify it under the terms of the GNU General Public License as 11b9a1ef21SChander Kashyap * published by the Free Software Foundation; either version 2 of 12b9a1ef21SChander Kashyap * the License, or (at your option) any later version. 13b9a1ef21SChander Kashyap * 14b9a1ef21SChander Kashyap * This program is distributed in the hope that it will be useful, 15b9a1ef21SChander Kashyap * but WITHOUT ANY WARRANTY; without even the implied warranty of 16b9a1ef21SChander Kashyap * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17b9a1ef21SChander Kashyap * GNU General Public License for more details. 18b9a1ef21SChander Kashyap * 19b9a1ef21SChander Kashyap * You should have received a copy of the GNU General Public License 20b9a1ef21SChander Kashyap * along with this program; if not, write to the Free Software 21b9a1ef21SChander Kashyap * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22b9a1ef21SChander Kashyap * MA 02111-1307 USA 23b9a1ef21SChander Kashyap */ 24b9a1ef21SChander Kashyap 25b9a1ef21SChander Kashyap #ifndef __CONFIG_H 26b9a1ef21SChander Kashyap #define __CONFIG_H 27b9a1ef21SChander Kashyap 28b9a1ef21SChander Kashyap /* High Level Configuration Options */ 29b9a1ef21SChander Kashyap #define CONFIG_SAMSUNG 1 /* SAMSUNG core */ 30b9a1ef21SChander Kashyap #define CONFIG_S5P 1 /* S5P Family */ 31393cb361SChander Kashyap #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ 32b9a1ef21SChander Kashyap #define CONFIG_ORIGEN 1 /* working with ORIGEN*/ 33b9a1ef21SChander Kashyap 34b9a1ef21SChander Kashyap #include <asm/arch/cpu.h> /* get chip and board defs */ 35b9a1ef21SChander Kashyap 36b9a1ef21SChander Kashyap #define CONFIG_ARCH_CPU_INIT 37b9a1ef21SChander Kashyap #define CONFIG_DISPLAY_CPUINFO 38b9a1ef21SChander Kashyap #define CONFIG_DISPLAY_BOARDINFO 39*198a40b9SRajeshwari Shinde #define CONFIG_BOARD_EARLY_INIT_F 40b9a1ef21SChander Kashyap 41b9a1ef21SChander Kashyap /* Keep L2 Cache Disabled */ 42b9a1ef21SChander Kashyap #define CONFIG_L2_OFF 1 43b9a1ef21SChander Kashyap #define CONFIG_SYS_DCACHE_OFF 1 44b9a1ef21SChander Kashyap 45b9a1ef21SChander Kashyap #define CONFIG_SYS_SDRAM_BASE 0x40000000 46b9a1ef21SChander Kashyap #define CONFIG_SYS_TEXT_BASE 0x43E00000 47b9a1ef21SChander Kashyap 48b9a1ef21SChander Kashyap /* input clock of PLL: ORIGEN has 24MHz input clock */ 49b9a1ef21SChander Kashyap #define CONFIG_SYS_CLK_FREQ 24000000 50b9a1ef21SChander Kashyap 51b9a1ef21SChander Kashyap #define CONFIG_SETUP_MEMORY_TAGS 52b9a1ef21SChander Kashyap #define CONFIG_CMDLINE_TAG 53b9a1ef21SChander Kashyap #define CONFIG_INITRD_TAG 54b9a1ef21SChander Kashyap #define CONFIG_CMDLINE_EDITING 55b9a1ef21SChander Kashyap 56b9a1ef21SChander Kashyap #define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN 57b9a1ef21SChander Kashyap 58b9a1ef21SChander Kashyap /* Power Down Modes */ 59b9a1ef21SChander Kashyap #define S5P_CHECK_SLEEP 0x00000BAD 60b9a1ef21SChander Kashyap #define S5P_CHECK_DIDLE 0xBAD00000 61b9a1ef21SChander Kashyap #define S5P_CHECK_LPA 0xABAD0000 62b9a1ef21SChander Kashyap 63b9a1ef21SChander Kashyap /* Size of malloc() pool */ 64b9a1ef21SChander Kashyap #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) 65b9a1ef21SChander Kashyap 66b9a1ef21SChander Kashyap /* select serial console configuration */ 67b9a1ef21SChander Kashyap #define CONFIG_SERIAL2 1 /* use SERIAL 2 */ 68b9a1ef21SChander Kashyap #define CONFIG_BAUDRATE 115200 69393cb361SChander Kashyap #define EXYNOS4_DEFAULT_UART_OFFSET 0x020000 70b9a1ef21SChander Kashyap 71b9a1ef21SChander Kashyap /* SD/MMC configuration */ 727d2d58b4SJaehoon Chung #define CONFIG_GENERIC_MMC 737d2d58b4SJaehoon Chung #define CONFIG_MMC 747d2d58b4SJaehoon Chung #define CONFIG_SDHCI 757d2d58b4SJaehoon Chung #define CONFIG_S5P_SDHCI 76b9a1ef21SChander Kashyap 77b9a1ef21SChander Kashyap /* PWM */ 78b9a1ef21SChander Kashyap #define CONFIG_PWM 1 79b9a1ef21SChander Kashyap 80b9a1ef21SChander Kashyap /* allow to overwrite serial and ethaddr */ 81b9a1ef21SChander Kashyap #define CONFIG_ENV_OVERWRITE 82b9a1ef21SChander Kashyap 83b9a1ef21SChander Kashyap /* Command definition*/ 84b9a1ef21SChander Kashyap #include <config_cmd_default.h> 85b9a1ef21SChander Kashyap 8680615006SJoe Hershberger #undef CONFIG_CMD_PING 87b9a1ef21SChander Kashyap #define CONFIG_CMD_ELF 88b9a1ef21SChander Kashyap #define CONFIG_CMD_DHCP 89b9a1ef21SChander Kashyap #define CONFIG_CMD_MMC 90b9a1ef21SChander Kashyap #define CONFIG_CMD_FAT 91b9a1ef21SChander Kashyap #undef CONFIG_CMD_NET 92b9a1ef21SChander Kashyap #undef CONFIG_CMD_NFS 93b9a1ef21SChander Kashyap 94b9a1ef21SChander Kashyap #define CONFIG_BOOTDELAY 3 95b9a1ef21SChander Kashyap #define CONFIG_ZERO_BOOTDELAY_CHECK 9698a48c5dSChander Kashyap /* MMC SPL */ 9798a48c5dSChander Kashyap #define CONFIG_SPL 9898a48c5dSChander Kashyap #define COPY_BL2_FNPTR_ADDR 0x02020030 99b9a1ef21SChander Kashyap 1008a00061eSInderpal Singh #define CONFIG_SPL_TEXT_BASE 0x02021410 1018a00061eSInderpal Singh 102b9a1ef21SChander Kashyap #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" 103b9a1ef21SChander Kashyap 104b9a1ef21SChander Kashyap /* Miscellaneous configurable options */ 105b9a1ef21SChander Kashyap #define CONFIG_SYS_LONGHELP /* undef to save memory */ 106b9a1ef21SChander Kashyap #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 107b9a1ef21SChander Kashyap #define CONFIG_SYS_PROMPT "ORIGEN # " 108b9a1ef21SChander Kashyap #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/ 109b9a1ef21SChander Kashyap #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ 110b9a1ef21SChander Kashyap #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 111b9a1ef21SChander Kashyap #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" 112b9a1ef21SChander Kashyap /* Boot Argument Buffer Size */ 113b9a1ef21SChander Kashyap #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 114b9a1ef21SChander Kashyap /* memtest works on */ 115b9a1ef21SChander Kashyap #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 116b9a1ef21SChander Kashyap #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) 117b9a1ef21SChander Kashyap #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) 118b9a1ef21SChander Kashyap 119b9a1ef21SChander Kashyap #define CONFIG_SYS_HZ 1000 120b9a1ef21SChander Kashyap 121b9a1ef21SChander Kashyap /* ORIGEN has 4 bank of DRAM */ 122b9a1ef21SChander Kashyap #define CONFIG_NR_DRAM_BANKS 4 123b9a1ef21SChander Kashyap #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ 124b9a1ef21SChander Kashyap #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 125b9a1ef21SChander Kashyap #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE 126b9a1ef21SChander Kashyap #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) 127b9a1ef21SChander Kashyap #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE 128b9a1ef21SChander Kashyap #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) 129b9a1ef21SChander Kashyap #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE 130b9a1ef21SChander Kashyap #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) 131b9a1ef21SChander Kashyap #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE 132b9a1ef21SChander Kashyap 133b9a1ef21SChander Kashyap /* FLASH and environment organization */ 134b9a1ef21SChander Kashyap #define CONFIG_SYS_NO_FLASH 1 135b9a1ef21SChander Kashyap #undef CONFIG_CMD_IMLS 136b9a1ef21SChander Kashyap #define CONFIG_IDENT_STRING " for ORIGEN" 137b9a1ef21SChander Kashyap 138b9a1ef21SChander Kashyap #define CONFIG_CLK_1000_400_200 139b9a1ef21SChander Kashyap 140b9a1ef21SChander Kashyap /* MIU (Memory Interleaving Unit) */ 141b9a1ef21SChander Kashyap #define CONFIG_MIU_2BIT_21_7_INTERLEAVED 142b9a1ef21SChander Kashyap 143b9a1ef21SChander Kashyap #define CONFIG_ENV_IS_IN_MMC 1 144b9a1ef21SChander Kashyap #define CONFIG_SYS_MMC_ENV_DEV 0 145b9a1ef21SChander Kashyap #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ 146b9a1ef21SChander Kashyap #define RESERVE_BLOCK_SIZE (512) 147b9a1ef21SChander Kashyap #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ 148b9a1ef21SChander Kashyap #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) 149b9a1ef21SChander Kashyap #define CONFIG_DOS_PARTITION 1 150b9a1ef21SChander Kashyap 151b9a1ef21SChander Kashyap #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) 15298a48c5dSChander Kashyap 15398a48c5dSChander Kashyap /* U-boot copy size from boot Media to DRAM.*/ 15498a48c5dSChander Kashyap #define COPY_BL2_SIZE 0x80000 15598a48c5dSChander Kashyap #define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) 15698a48c5dSChander Kashyap #define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) 157099e884aSAngus Ainslie 158099e884aSAngus Ainslie /* Enable devicetree support */ 159099e884aSAngus Ainslie #define CONFIG_OF_LIBFDT 160b9a1ef21SChander Kashyap #endif /* __CONFIG_H */ 161