1 /*
2  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  * Based on davinci_dvevm.h. Original Copyrights follow:
5  *
6  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
7  *
8  * SPDX-License-Identifier:	GPL-2.0
9  */
10 
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /*
15  * Board
16  */
17 #define CONFIG_DRIVER_TI_EMAC
18 #undef CONFIG_USE_SPIFLASH
19 #undef	CONFIG_SYS_USE_NOR
20 #define	CONFIG_USE_NAND
21 
22 /*
23  * SoC Configuration
24  */
25 #define CONFIG_MACH_OMAPL138_LCDK
26 #define CONFIG_ARM926EJS		/* arm926ejs CPU core */
27 #define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
28 #define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
29 #define CONFIG_SYS_OSCIN_FREQ		24000000
30 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
31 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
32 #define CONFIG_SYS_HZ			1000
33 #define CONFIG_SKIP_LOWLEVEL_INIT
34 #define CONFIG_SYS_TEXT_BASE		0xc1080000
35 
36 /*
37  * Memory Info
38  */
39 #define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
40 #define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
41 #define PHYS_SDRAM_1_SIZE	(128 << 20) /* SDRAM size 128MB */
42 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
43 
44 /* memtest start addr */
45 #define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
46 
47 /* memtest will be run on 16MB */
48 #define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
49 
50 #define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
51 
52 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
53 	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
54 	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
55 	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
56 	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
57 	DAVINCI_SYSCFG_SUSPSRC_I2C)
58 
59 /*
60  * PLL configuration
61  */
62 #define CONFIG_SYS_DV_CLKMODE          0
63 #define CONFIG_SYS_DA850_PLL0_POSTDIV  1
64 #define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
65 #define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
66 #define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
67 #define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
68 #define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
69 #define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
70 #define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
71 
72 #define CONFIG_SYS_DA850_PLL1_POSTDIV  1
73 #define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
74 #define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
75 #define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8003
76 
77 #define CONFIG_SYS_DA850_PLL0_PLLM     37
78 #define CONFIG_SYS_DA850_PLL1_PLLM     21
79 
80 /*
81  * DDR2 memory configuration
82  */
83 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
84 					DV_DDR_PHY_EXT_STRBEN | \
85 					(0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
86 
87 #define CONFIG_SYS_DA850_DDR2_SDBCR (		  \
88 	(1 << DV_DDR_SDCR_DDR2EN_SHIFT)		| \
89 	(1 << DV_DDR_SDCR_DDREN_SHIFT)		| \
90 	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT)	| \
91 	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)	| \
92 	(4 << DV_DDR_SDCR_CL_SHIFT)		| \
93 	(3 << DV_DDR_SDCR_IBANK_SHIFT)		| \
94 	(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
95 
96 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
97 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
98 
99 #define CONFIG_SYS_DA850_DDR2_SDTIMR (		  \
100 	(19 << DV_DDR_SDTMR1_RFC_SHIFT)		| \
101 	(1 << DV_DDR_SDTMR1_RP_SHIFT)		| \
102 	(1 << DV_DDR_SDTMR1_RCD_SHIFT)		| \
103 	(2 << DV_DDR_SDTMR1_WR_SHIFT)		| \
104 	(6 << DV_DDR_SDTMR1_RAS_SHIFT)		| \
105 	(8 << DV_DDR_SDTMR1_RC_SHIFT)		| \
106 	(1 << DV_DDR_SDTMR1_RRD_SHIFT)		| \
107 	(1 << DV_DDR_SDTMR1_WTR_SHIFT))
108 
109 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		  \
110 	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT)	| \
111 	(2 << DV_DDR_SDTMR2_XP_SHIFT)		| \
112 	(0 << DV_DDR_SDTMR2_ODT_SHIFT)		| \
113 	(20 << DV_DDR_SDTMR2_XSNR_SHIFT)	| \
114 	(199 << DV_DDR_SDTMR2_XSRD_SHIFT)	| \
115 	(1 << DV_DDR_SDTMR2_RTP_SHIFT)		| \
116 	(2 << DV_DDR_SDTMR2_CKE_SHIFT))
117 
118 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000492
119 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
120 
121 /*
122  * Serial Driver info
123  */
124 #define CONFIG_SYS_NS16550_SERIAL
125 #define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
126 #define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
127 #define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
128 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
129 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
130 
131 #define CONFIG_SPI
132 #define CONFIG_DAVINCI_SPI
133 #define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
134 #define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
135 #define CONFIG_SF_DEFAULT_SPEED		30000000
136 #define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
137 
138 #ifdef CONFIG_USE_SPIFLASH
139 #define CONFIG_SPL_SPI_LOAD
140 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
141 #define CONFIG_SYS_SPI_U_BOOT_SIZE	0x30000
142 #endif
143 
144 /*
145  * I2C Configuration
146  */
147 #define CONFIG_SYS_I2C
148 #define CONFIG_SYS_I2C_DAVINCI
149 #define CONFIG_SYS_DAVINCI_I2C_SPEED	25000
150 #define CONFIG_SYS_DAVINCI_I2C_SLAVE	10 /* Bogus, master-only in U-Boot */
151 #define CONFIG_SYS_I2C_EXPANDER_ADDR	0x20
152 
153 /*
154  * Flash & Environment
155  */
156 #ifdef CONFIG_USE_NAND
157 #define CONFIG_NAND_DAVINCI
158 #define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
159 #define CONFIG_ENV_SIZE			(128 << 9)
160 #define	CONFIG_SYS_NAND_USE_FLASH_BBT
161 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
162 #define	CONFIG_SYS_NAND_PAGE_2K
163 #define	CONFIG_SYS_NAND_BUSWIDTH_16BIT
164 #define CONFIG_SYS_NAND_CS		3
165 #define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
166 #define CONFIG_SYS_NAND_MASK_CLE	0x10
167 #define CONFIG_SYS_NAND_MASK_ALE	0x8
168 #undef CONFIG_SYS_NAND_HW_ECC
169 #define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
170 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
171 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
172 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
173 #define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
174 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
175 #define CONFIG_SYS_NAND_U_BOOT_SIZE	SZ_512K
176 #define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
177 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
178 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
179 					CONFIG_SYS_NAND_U_BOOT_SIZE - \
180 					CONFIG_SYS_MALLOC_LEN -       \
181 					GENERATED_GBL_DATA_SIZE)
182 #define CONFIG_SYS_NAND_ECCPOS		{				\
183 				6, 7, 8, 9, 10, 11, 12, 13, 14, 15,	\
184 				22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
185 				38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
186 				54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
187 #define CONFIG_SYS_NAND_PAGE_COUNT	64
188 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
189 #define CONFIG_SYS_NAND_ECCSIZE		512
190 #define CONFIG_SYS_NAND_ECCBYTES	10
191 #define CONFIG_SYS_NAND_OOBSIZE		64
192 #define CONFIG_SPL_NAND_BASE
193 #define CONFIG_SPL_NAND_DRIVERS
194 #define CONFIG_SPL_NAND_ECC
195 #define CONFIG_SPL_NAND_SIMPLE
196 #define CONFIG_SPL_NAND_LOAD
197 #endif
198 
199 #ifdef CONFIG_SYS_USE_NOR
200 #define CONFIG_FLASH_CFI_DRIVER
201 #define CONFIG_SYS_FLASH_CFI
202 #define CONFIG_SYS_FLASH_PROTECTION
203 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* max number of flash banks */
204 #define CONFIG_SYS_FLASH_SECT_SZ	(128 << 10) /* 128KB */
205 #define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ * 3)
206 #define CONFIG_ENV_SIZE			(128 << 10)
207 #define CONFIG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
208 #define PHYS_FLASH_SIZE			(8 << 20) /* Flash size 8MB */
209 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
210 	       + 3)
211 #define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_FLASH_SECT_SZ
212 #endif
213 
214 #ifdef CONFIG_USE_SPIFLASH
215 #define CONFIG_ENV_SIZE			(64 << 10)
216 #define CONFIG_ENV_OFFSET		(256 << 10)
217 #define CONFIG_ENV_SECT_SIZE		(64 << 10)
218 #endif
219 
220 /*
221  * Network & Ethernet Configuration
222  */
223 #ifdef CONFIG_DRIVER_TI_EMAC
224 #define CONFIG_MII
225 #undef	CONFIG_DRIVER_TI_EMAC_USE_RMII
226 #define CONFIG_BOOTP_DEFAULT
227 #define CONFIG_BOOTP_DNS
228 #define CONFIG_BOOTP_DNS2
229 #define CONFIG_BOOTP_SEND_HOSTNAME
230 #define CONFIG_NET_RETRY_COUNT	10
231 #endif
232 
233 /*
234  * U-Boot general configuration
235  */
236 #define CONFIG_MISC_INIT_R
237 #define CONFIG_BOOTFILE		"zImage" /* Boot file name */
238 #define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
239 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
240 #define CONFIG_SYS_MAXARGS	16 /* max number of command args */
241 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
242 #define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
243 #define CONFIG_AUTO_COMPLETE
244 #define CONFIG_CMDLINE_EDITING
245 #define CONFIG_SYS_LONGHELP
246 #define CONFIG_MX_CYCLIC
247 
248 /*
249  * Linux Information
250  */
251 #define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
252 #define CONFIG_CMDLINE_TAG
253 #define CONFIG_REVISION_TAG
254 #define CONFIG_SETUP_MEMORY_TAGS
255 #define CONFIG_BOOTCOMMAND \
256 		"run envboot; " \
257 		"run mmcboot; "
258 
259 #define DEFAULT_LINUX_BOOT_ENV \
260 	"loadaddr=0xc0700000\0" \
261 	"fdtaddr=0xc0600000\0" \
262 	"scriptaddr=0xc0600000\0"
263 
264 #include <environment/ti/mmc.h>
265 
266 #define CONFIG_EXTRA_ENV_SETTINGS \
267 	DEFAULT_LINUX_BOOT_ENV \
268 	DEFAULT_MMC_TI_ARGS \
269 	"bootpart=0:2\0" \
270 	"bootdir=/boot\0" \
271 	"bootfile=zImage\0" \
272 	"fdtfile=da850-lcdk.dtb\0" \
273 	"boot_fdt=yes\0" \
274 	"boot_fit=0\0" \
275 	"console=ttyS2,115200n8\0"
276 
277 #ifdef CONFIG_CMD_BDI
278 #define CONFIG_CLOCKS
279 #endif
280 
281 #ifndef CONFIG_DRIVER_TI_EMAC
282 #endif
283 
284 #ifdef CONFIG_USE_NAND
285 #define CONFIG_MTD_DEVICE
286 #define CONFIG_MTD_PARTITIONS
287 #endif
288 
289 #if !defined(CONFIG_USE_NAND) && \
290 	!defined(CONFIG_SYS_USE_NOR) && \
291 	!defined(CONFIG_USE_SPIFLASH)
292 #define CONFIG_ENV_SIZE		(16 << 10)
293 #endif
294 
295 /* SD/MMC */
296 
297 #ifdef CONFIG_ENV_IS_IN_MMC
298 #undef CONFIG_ENV_SIZE
299 #undef CONFIG_ENV_OFFSET
300 #define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
301 #define CONFIG_ENV_OFFSET	(51 << 9)	/* Sector 51 */
302 #endif
303 
304 #ifndef CONFIG_DIRECT_NOR_BOOT
305 /* defines for SPL */
306 #define CONFIG_SPL_FRAMEWORK
307 #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
308 						CONFIG_SYS_MALLOC_LEN)
309 #define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
310 #define CONFIG_SPL_STACK	0x8001ff00
311 #define CONFIG_SPL_TEXT_BASE	0x80000000
312 #define CONFIG_SPL_MAX_FOOTPRINT	32768
313 #define CONFIG_SPL_PAD_TO	32768
314 #endif
315 
316 /* additions for new relocation code, must added to all boards */
317 #define CONFIG_SYS_SDRAM_BASE		0xc0000000
318 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
319 					GENERATED_GBL_DATA_SIZE)
320 
321 #include <asm/arch/hardware.h>
322 
323 #endif /* __CONFIG_H */
324