1 /*
2  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  * Based on davinci_dvevm.h. Original Copyrights follow:
5  *
6  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  */
22 
23 #ifndef __CONFIG_H
24 #define __CONFIG_H
25 
26 /*
27  * Board
28  */
29 #define CONFIG_DRIVER_TI_EMAC
30 #undef CONFIG_USE_SPIFLASH
31 #undef	CONFIG_SYS_USE_NOR
32 #define	CONFIG_USE_NAND
33 
34 /*
35  * SoC Configuration
36  */
37 #define CONFIG_MACH_OMAPL138_LCDK
38 #define CONFIG_ARM926EJS		/* arm926ejs CPU core */
39 #define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
40 #define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
41 #define CONFIG_SYS_OSCIN_FREQ		24000000
42 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
43 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
44 #define CONFIG_SYS_HZ			1000
45 #define CONFIG_SKIP_LOWLEVEL_INIT
46 #define CONFIG_SYS_TEXT_BASE		0xc1080000
47 
48 /*
49  * Memory Info
50  */
51 #define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
52 #define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
53 #define PHYS_SDRAM_1_SIZE	(128 << 20) /* SDRAM size 128MB */
54 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
55 
56 /* memtest start addr */
57 #define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
58 
59 /* memtest will be run on 16MB */
60 #define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
61 
62 #define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
63 #define CONFIG_STACKSIZE	(256*1024) /* regular stack */
64 
65 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
66 	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
67 	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
68 	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
69 	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
70 	DAVINCI_SYSCFG_SUSPSRC_I2C)
71 
72 /*
73  * PLL configuration
74  */
75 #define CONFIG_SYS_DV_CLKMODE          0
76 #define CONFIG_SYS_DA850_PLL0_POSTDIV  1
77 #define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
78 #define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
79 #define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
80 #define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
81 #define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
82 #define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
83 #define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
84 
85 #define CONFIG_SYS_DA850_PLL1_POSTDIV  1
86 #define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
87 #define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
88 #define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8003
89 
90 #define CONFIG_SYS_DA850_PLL0_PLLM     24
91 #define CONFIG_SYS_DA850_PLL1_PLLM     21
92 
93 /*
94  * Serial Driver info
95  */
96 #define CONFIG_SYS_NS16550
97 #define CONFIG_SYS_NS16550_SERIAL
98 #define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
99 #define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
100 #define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
101 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
102 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
103 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
104 
105 #define CONFIG_SPI
106 #define CONFIG_SPI_FLASH_STMICRO
107 #define CONFIG_SPI_FLASH_WINBOND
108 #define CONFIG_DAVINCI_SPI
109 #define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
110 #define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
111 #define CONFIG_SF_DEFAULT_SPEED		30000000
112 #define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
113 
114 #ifdef CONFIG_USE_SPIFLASH
115 #define CONFIG_SPL_SPI_SUPPORT
116 #define CONFIG_SPL_SPI_FLASH_SUPPORT
117 #define CONFIG_SPL_SPI_LOAD
118 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
119 #define CONFIG_SYS_SPI_U_BOOT_SIZE	0x30000
120 #endif
121 
122 /*
123  * I2C Configuration
124  */
125 #define CONFIG_SYS_I2C
126 #define CONFIG_SYS_I2C_DAVINCI
127 #define CONFIG_SYS_DAVINCI_I2C_SPEED	25000
128 #define CONFIG_SYS_DAVINCI_I2C_SLAVE	10 /* Bogus, master-only in U-Boot */
129 #define CONFIG_SYS_I2C_EXPANDER_ADDR	0x20
130 
131 /*
132  * Flash & Environment
133  */
134 #ifdef CONFIG_USE_NAND
135 #undef CONFIG_ENV_IS_IN_FLASH
136 #define CONFIG_NAND_DAVINCI
137 #define CONFIG_SYS_NO_FLASH
138 #define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
139 #define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
140 #define CONFIG_ENV_SIZE			(128 << 9)
141 #define	CONFIG_SYS_NAND_USE_FLASH_BBT
142 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
143 #define	CONFIG_SYS_NAND_PAGE_2K
144 #define	CONFIG_SYS_NAND_BUSWIDTH_16_BIT
145 #define CONFIG_SYS_NAND_CS		3
146 #define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
147 #define CONFIG_SYS_CLE_MASK		0x10
148 #define CONFIG_SYS_ALE_MASK		0x8
149 #undef CONFIG_SYS_NAND_HW_ECC
150 #define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
151 #define NAND_MAX_CHIPS			1
152 #endif
153 
154 #ifdef CONFIG_SYS_USE_NOR
155 #define CONFIG_ENV_IS_IN_FLASH
156 #undef CONFIG_SYS_NO_FLASH
157 #define CONFIG_FLASH_CFI_DRIVER
158 #define CONFIG_SYS_FLASH_CFI
159 #define CONFIG_SYS_FLASH_PROTECTION
160 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* max number of flash banks */
161 #define CONFIG_SYS_FLASH_SECT_SZ	(128 << 10) /* 128KB */
162 #define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ * 3)
163 #define CONFIG_ENV_SIZE			(128 << 10)
164 #define CONFIG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
165 #define PHYS_FLASH_SIZE			(8 << 20) /* Flash size 8MB */
166 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
167 	       + 3)
168 #define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_FLASH_SECT_SZ
169 #endif
170 
171 #ifdef CONFIG_USE_SPIFLASH
172 #undef CONFIG_ENV_IS_IN_FLASH
173 #undef CONFIG_ENV_IS_IN_NAND
174 #define CONFIG_ENV_IS_IN_SPI_FLASH
175 #define CONFIG_ENV_SIZE			(64 << 10)
176 #define CONFIG_ENV_OFFSET		(256 << 10)
177 #define CONFIG_ENV_SECT_SIZE		(64 << 10)
178 #define CONFIG_SYS_NO_FLASH
179 #endif
180 
181 /*
182  * Network & Ethernet Configuration
183  */
184 #ifdef CONFIG_DRIVER_TI_EMAC
185 #define CONFIG_EMAC_MDIO_PHY_NUM	7
186 #define CONFIG_MII
187 #undef	CONFIG_DRIVER_TI_EMAC_USE_RMII
188 #define CONFIG_BOOTP_DEFAULT
189 #define CONFIG_BOOTP_DNS
190 #define CONFIG_BOOTP_DNS2
191 #define CONFIG_BOOTP_SEND_HOSTNAME
192 #define CONFIG_NET_RETRY_COUNT	10
193 #endif
194 
195 /*
196  * U-Boot general configuration
197  */
198 #define CONFIG_MISC_INIT_R
199 #define CONFIG_BOARD_EARLY_INIT_F
200 #define CONFIG_BOOTFILE		"uImage" /* Boot file name */
201 #define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
202 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
203 #define CONFIG_SYS_MAXARGS	16 /* max number of command args */
204 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
205 #define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
206 #define CONFIG_VERSION_VARIABLE
207 #define CONFIG_AUTO_COMPLETE
208 #define CONFIG_SYS_HUSH_PARSER
209 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
210 #define CONFIG_CMDLINE_EDITING
211 #define CONFIG_SYS_LONGHELP
212 #define CONFIG_CRC32_VERIFY
213 #define CONFIG_MX_CYCLIC
214 #define CONFIG_OF_LIBFDT
215 
216 /*
217  * Linux Information
218  */
219 #define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
220 #define CONFIG_CMDLINE_TAG
221 #define CONFIG_REVISION_TAG
222 #define CONFIG_SETUP_MEMORY_TAGS
223 #define CONFIG_BOOTARGS		"console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off"
224 #define CONFIG_BOOTCOMMAND	"if mmc rescan 0; then if fatload mmc 0 0xc0600000 boot.scr; then source 0xc0600000; else fatload mmc 0 0xc0700000 uImage; bootm c0700000; fi; else sf probe 0; sf read 0xc0700000 0x80000 0x220000; bootm 0xc0700000; fi"
225 #define CONFIG_BOOTDELAY	3
226 
227 /*
228  * U-Boot commands
229  */
230 #define CONFIG_CMD_ENV
231 #define CONFIG_CMD_ASKENV
232 #define CONFIG_CMD_DHCP
233 #define CONFIG_CMD_DIAG
234 #define CONFIG_CMD_MII
235 #define CONFIG_CMD_PING
236 #define CONFIG_CMD_SAVES
237 #ifdef CONFIG_CMD_BDI
238 #define CONFIG_CLOCKS
239 #endif
240 
241 #ifndef CONFIG_DRIVER_TI_EMAC
242 #undef CONFIG_CMD_DHCP
243 #undef CONFIG_CMD_MII
244 #undef CONFIG_CMD_PING
245 #endif
246 
247 #ifdef CONFIG_USE_NAND
248 #define CONFIG_CMD_NAND
249 
250 #define CONFIG_CMD_MTDPARTS
251 #define CONFIG_MTD_DEVICE
252 #define CONFIG_MTD_PARTITIONS
253 #define CONFIG_LZO
254 #define CONFIG_RBTREE
255 #define CONFIG_CMD_UBI
256 #define CONFIG_CMD_UBIFS
257 #endif
258 
259 #ifdef CONFIG_USE_SPIFLASH
260 #define CONFIG_CMD_SPI
261 #define CONFIG_CMD_SF
262 #endif
263 
264 #if !defined(CONFIG_USE_NAND) && \
265 	!defined(CONFIG_SYS_USE_NOR) && \
266 	!defined(CONFIG_USE_SPIFLASH)
267 #define CONFIG_ENV_IS_NOWHERE
268 #define CONFIG_SYS_NO_FLASH
269 #define CONFIG_ENV_SIZE		(16 << 10)
270 #undef CONFIG_CMD_ENV
271 #endif
272 
273 /* SD/MMC */
274 #define CONFIG_MMC
275 #define CONFIG_GENERIC_MMC
276 #define CONFIG_DAVINCI_MMC
277 
278 #ifdef CONFIG_MMC
279 #define CONFIG_DOS_PARTITION
280 #define CONFIG_CMD_EXT2
281 #define CONFIG_CMD_FAT
282 #define CONFIG_CMD_MMC
283 #undef CONFIG_ENV_IS_IN_MMC
284 #endif
285 
286 #ifdef CONFIG_ENV_IS_IN_MMC
287 #undef CONFIG_ENV_SIZE
288 #undef CONFIG_ENV_OFFSET
289 #define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
290 #define CONFIG_ENV_OFFSET	(51 << 9)	/* Sector 51 */
291 #undef CONFIG_ENV_IS_IN_FLASH
292 #undef CONFIG_ENV_IS_IN_NAND
293 #undef CONFIG_ENV_IS_IN_SPI_FLASH
294 #endif
295 
296 #ifndef CONFIG_DIRECT_NOR_BOOT
297 /* defines for SPL */
298 #define CONFIG_SPL_FRAMEWORK
299 #define CONFIG_SPL_BOARD_INIT
300 #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
301 						CONFIG_SYS_MALLOC_LEN)
302 #define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
303 #define CONFIG_SPL_SERIAL_SUPPORT
304 #define CONFIG_SPL_LIBCOMMON_SUPPORT
305 #define CONFIG_SPL_LIBGENERIC_SUPPORT
306 #define CONFIG_SPL_LDSCRIPT	"board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
307 #define CONFIG_SPL_STACK	0x8001ff00
308 #define CONFIG_SPL_TEXT_BASE	0x80000000
309 #define CONFIG_SPL_MAX_FOOTPRINT	32768
310 #define CONFIG_SPL_PAD_TO	32768
311 #endif
312 
313 /* additions for new relocation code, must added to all boards */
314 #define CONFIG_SYS_SDRAM_BASE		0xc0000000
315 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
316 					GENERATED_GBL_DATA_SIZE)
317 #endif /* __CONFIG_H */
318