1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on davinci_dvevm.h. Original Copyrights follow: 5 * 6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * Board 16 */ 17 #define CONFIG_DRIVER_TI_EMAC 18 #undef CONFIG_USE_SPIFLASH 19 #undef CONFIG_SYS_USE_NOR 20 #define CONFIG_USE_NAND 21 22 /* 23 * SoC Configuration 24 */ 25 #define CONFIG_MACH_OMAPL138_LCDK 26 #define CONFIG_ARM926EJS /* arm926ejs CPU core */ 27 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 28 #define CONFIG_SYS_OSCIN_FREQ 24000000 29 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 30 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 31 #define CONFIG_SYS_HZ 1000 32 #define CONFIG_SKIP_LOWLEVEL_INIT 33 34 /* 35 * Memory Info 36 */ 37 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 38 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 39 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ 40 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 41 42 /* memtest start addr */ 43 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 44 45 /* memtest will be run on 16MB */ 46 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 47 48 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 49 50 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 51 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 52 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 53 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 54 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 55 DAVINCI_SYSCFG_SUSPSRC_I2C) 56 57 /* 58 * PLL configuration 59 */ 60 61 #define CONFIG_SYS_DA850_PLL0_PLLM 37 62 #define CONFIG_SYS_DA850_PLL1_PLLM 21 63 64 /* 65 * DDR2 memory configuration 66 */ 67 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 68 DV_DDR_PHY_EXT_STRBEN | \ 69 (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 70 71 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 72 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ 73 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 74 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 75 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 76 (4 << DV_DDR_SDCR_CL_SHIFT) | \ 77 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ 78 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 79 80 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 81 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 82 83 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 84 (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 85 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ 86 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 87 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ 88 (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 89 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 90 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 91 (1 << DV_DDR_SDTMR1_WTR_SHIFT)) 92 93 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 94 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 95 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ 96 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 97 (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 98 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 99 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 100 (2 << DV_DDR_SDTMR2_CKE_SHIFT)) 101 102 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492 103 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 104 105 /* 106 * Serial Driver info 107 */ 108 #define CONFIG_SYS_NS16550_SERIAL 109 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 110 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 111 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 112 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 113 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 114 115 #define CONFIG_SPI 116 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE 117 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) 118 #define CONFIG_SF_DEFAULT_SPEED 30000000 119 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 120 121 #ifdef CONFIG_USE_SPIFLASH 122 #define CONFIG_SPL_SPI_LOAD 123 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 124 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 125 #endif 126 127 /* 128 * I2C Configuration 129 */ 130 #define CONFIG_SYS_I2C 131 #define CONFIG_SYS_I2C_DAVINCI 132 #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 133 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ 134 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 135 136 /* 137 * Flash & Environment 138 */ 139 #ifdef CONFIG_USE_NAND 140 #define CONFIG_NAND_DAVINCI 141 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 142 #define CONFIG_ENV_SIZE (128 << 9) 143 #define CONFIG_SYS_NAND_USE_FLASH_BBT 144 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 145 #define CONFIG_SYS_NAND_PAGE_2K 146 #define CONFIG_SYS_NAND_CS 3 147 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 148 #define CONFIG_SYS_NAND_MASK_CLE 0x10 149 #define CONFIG_SYS_NAND_MASK_ALE 0x8 150 #undef CONFIG_SYS_NAND_HW_ECC 151 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 152 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 153 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC 154 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 155 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) 156 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 157 #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K 158 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 159 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 160 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 161 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 162 CONFIG_SYS_MALLOC_LEN - \ 163 GENERATED_GBL_DATA_SIZE) 164 #define CONFIG_SYS_NAND_ECCPOS { \ 165 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 166 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 167 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 168 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 } 169 #define CONFIG_SYS_NAND_PAGE_COUNT 64 170 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 171 #define CONFIG_SYS_NAND_ECCSIZE 512 172 #define CONFIG_SYS_NAND_ECCBYTES 10 173 #define CONFIG_SYS_NAND_OOBSIZE 64 174 #define CONFIG_SPL_NAND_BASE 175 #define CONFIG_SPL_NAND_DRIVERS 176 #define CONFIG_SPL_NAND_ECC 177 #define CONFIG_SPL_NAND_LOAD 178 #endif 179 180 #ifdef CONFIG_SYS_USE_NOR 181 #define CONFIG_FLASH_CFI_DRIVER 182 #define CONFIG_SYS_FLASH_CFI 183 #define CONFIG_SYS_FLASH_PROTECTION 184 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 185 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 186 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) 187 #define CONFIG_ENV_SIZE (128 << 10) 188 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 189 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ 190 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ 191 + 3) 192 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 193 #endif 194 195 #ifdef CONFIG_USE_SPIFLASH 196 #define CONFIG_ENV_SIZE (64 << 10) 197 #define CONFIG_ENV_OFFSET (256 << 10) 198 #define CONFIG_ENV_SECT_SIZE (64 << 10) 199 #endif 200 201 /* 202 * Network & Ethernet Configuration 203 */ 204 #ifdef CONFIG_DRIVER_TI_EMAC 205 #define CONFIG_MII 206 #undef CONFIG_DRIVER_TI_EMAC_USE_RMII 207 #define CONFIG_BOOTP_DEFAULT 208 #define CONFIG_BOOTP_DNS 209 #define CONFIG_BOOTP_DNS2 210 #define CONFIG_BOOTP_SEND_HOSTNAME 211 #define CONFIG_NET_RETRY_COUNT 10 212 #endif 213 214 /* 215 * U-Boot general configuration 216 */ 217 #define CONFIG_MISC_INIT_R 218 #define CONFIG_BOOTFILE "zImage" /* Boot file name */ 219 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 220 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 221 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 222 #define CONFIG_AUTO_COMPLETE 223 #define CONFIG_CMDLINE_EDITING 224 #define CONFIG_SYS_LONGHELP 225 #define CONFIG_MX_CYCLIC 226 227 /* 228 * Linux Information 229 */ 230 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 231 #define CONFIG_CMDLINE_TAG 232 #define CONFIG_REVISION_TAG 233 #define CONFIG_SETUP_MEMORY_TAGS 234 #define CONFIG_BOOTCOMMAND \ 235 "run envboot; " \ 236 "run mmcboot; " 237 238 #define DEFAULT_LINUX_BOOT_ENV \ 239 "loadaddr=0xc0700000\0" \ 240 "fdtaddr=0xc0600000\0" \ 241 "scriptaddr=0xc0600000\0" 242 243 #include <environment/ti/mmc.h> 244 245 #define CONFIG_EXTRA_ENV_SETTINGS \ 246 DEFAULT_LINUX_BOOT_ENV \ 247 DEFAULT_MMC_TI_ARGS \ 248 "bootpart=0:2\0" \ 249 "bootdir=/boot\0" \ 250 "bootfile=zImage\0" \ 251 "fdtfile=da850-lcdk.dtb\0" \ 252 "boot_fdt=yes\0" \ 253 "boot_fit=0\0" \ 254 "console=ttyS2,115200n8\0" 255 256 #ifdef CONFIG_CMD_BDI 257 #define CONFIG_CLOCKS 258 #endif 259 260 #ifndef CONFIG_DRIVER_TI_EMAC 261 #endif 262 263 #ifdef CONFIG_USE_NAND 264 #define CONFIG_MTD_DEVICE 265 #define CONFIG_MTD_PARTITIONS 266 #endif 267 268 #if !defined(CONFIG_USE_NAND) && \ 269 !defined(CONFIG_SYS_USE_NOR) && \ 270 !defined(CONFIG_USE_SPIFLASH) 271 #define CONFIG_ENV_SIZE (16 << 10) 272 #endif 273 274 /* SD/MMC */ 275 276 #ifdef CONFIG_ENV_IS_IN_MMC 277 #undef CONFIG_ENV_SIZE 278 #undef CONFIG_ENV_OFFSET 279 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 280 #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ 281 #endif 282 283 #ifndef CONFIG_DIRECT_NOR_BOOT 284 /* defines for SPL */ 285 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 286 CONFIG_SYS_MALLOC_LEN) 287 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 288 #define CONFIG_SPL_STACK 0x8001ff00 289 #define CONFIG_SPL_TEXT_BASE 0x80000000 290 #define CONFIG_SPL_MAX_FOOTPRINT 32768 291 #define CONFIG_SPL_PAD_TO 32768 292 #endif 293 294 /* additions for new relocation code, must added to all boards */ 295 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 296 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 297 GENERATED_GBL_DATA_SIZE) 298 299 #include <asm/arch/hardware.h> 300 301 #endif /* __CONFIG_H */ 302