1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on davinci_dvevm.h. Original Copyrights follow: 5 * 6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * Board 28 */ 29 #define CONFIG_DRIVER_TI_EMAC 30 #undef CONFIG_USE_SPIFLASH 31 #undef CONFIG_SYS_USE_NOR 32 #define CONFIG_USE_NAND 33 34 /* 35 * SoC Configuration 36 */ 37 #define CONFIG_MACH_OMAPL138_LCDK 38 #define CONFIG_ARM926EJS /* arm926ejs CPU core */ 39 #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ 40 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 41 #define CONFIG_SYS_OSCIN_FREQ 24000000 42 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 43 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 44 #define CONFIG_SYS_HZ 1000 45 #define CONFIG_SKIP_LOWLEVEL_INIT 46 #define CONFIG_SYS_TEXT_BASE 0xc1080000 47 48 /* 49 * Memory Info 50 */ 51 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 52 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 53 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ 54 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 55 56 /* memtest start addr */ 57 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 58 59 /* memtest will be run on 16MB */ 60 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 61 62 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 63 #define CONFIG_STACKSIZE (256*1024) /* regular stack */ 64 65 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 66 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 67 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 68 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 69 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 70 DAVINCI_SYSCFG_SUSPSRC_I2C) 71 72 /* 73 * PLL configuration 74 */ 75 #define CONFIG_SYS_DV_CLKMODE 0 76 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 77 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 78 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 79 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 80 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 81 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 82 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 83 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 84 85 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 86 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 87 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 88 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003 89 90 #define CONFIG_SYS_DA850_PLL0_PLLM 24 91 #define CONFIG_SYS_DA850_PLL1_PLLM 21 92 93 /* 94 * Serial Driver info 95 */ 96 #define CONFIG_SYS_NS16550 97 #define CONFIG_SYS_NS16550_SERIAL 98 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 99 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 100 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 101 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 102 #define CONFIG_BAUDRATE 115200 /* Default baud rate */ 103 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 104 105 #define CONFIG_SPI 106 #define CONFIG_SPI_FLASH 107 #define CONFIG_SPI_FLASH_STMICRO 108 #define CONFIG_SPI_FLASH_WINBOND 109 #define CONFIG_DAVINCI_SPI 110 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE 111 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) 112 #define CONFIG_SF_DEFAULT_SPEED 30000000 113 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 114 115 #ifdef CONFIG_USE_SPIFLASH 116 #define CONFIG_SPL_SPI_SUPPORT 117 #define CONFIG_SPL_SPI_FLASH_SUPPORT 118 #define CONFIG_SPL_SPI_LOAD 119 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 120 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 121 #endif 122 123 /* 124 * I2C Configuration 125 */ 126 #define CONFIG_SYS_I2C 127 #define CONFIG_SYS_I2C_DAVINCI 128 #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 129 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ 130 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 131 132 /* 133 * Flash & Environment 134 */ 135 #ifdef CONFIG_USE_NAND 136 #undef CONFIG_ENV_IS_IN_FLASH 137 #define CONFIG_NAND_DAVINCI 138 #define CONFIG_SYS_NO_FLASH 139 #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ 140 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 141 #define CONFIG_ENV_SIZE (128 << 9) 142 #define CONFIG_SYS_NAND_USE_FLASH_BBT 143 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 144 #define CONFIG_SYS_NAND_PAGE_2K 145 #define CONFIG_SYS_NAND_BUSWIDTH_16_BIT 146 #define CONFIG_SYS_NAND_CS 3 147 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 148 #define CONFIG_SYS_CLE_MASK 0x10 149 #define CONFIG_SYS_ALE_MASK 0x8 150 #undef CONFIG_SYS_NAND_HW_ECC 151 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 152 #define NAND_MAX_CHIPS 1 153 #endif 154 155 #ifdef CONFIG_SYS_USE_NOR 156 #define CONFIG_ENV_IS_IN_FLASH 157 #undef CONFIG_SYS_NO_FLASH 158 #define CONFIG_FLASH_CFI_DRIVER 159 #define CONFIG_SYS_FLASH_CFI 160 #define CONFIG_SYS_FLASH_PROTECTION 161 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 162 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 163 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) 164 #define CONFIG_ENV_SIZE (128 << 10) 165 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 166 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ 167 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ 168 + 3) 169 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 170 #endif 171 172 #ifdef CONFIG_USE_SPIFLASH 173 #undef CONFIG_ENV_IS_IN_FLASH 174 #undef CONFIG_ENV_IS_IN_NAND 175 #define CONFIG_ENV_IS_IN_SPI_FLASH 176 #define CONFIG_ENV_SIZE (64 << 10) 177 #define CONFIG_ENV_OFFSET (256 << 10) 178 #define CONFIG_ENV_SECT_SIZE (64 << 10) 179 #define CONFIG_SYS_NO_FLASH 180 #endif 181 182 /* 183 * Network & Ethernet Configuration 184 */ 185 #ifdef CONFIG_DRIVER_TI_EMAC 186 #define CONFIG_EMAC_MDIO_PHY_NUM 7 187 #define CONFIG_MII 188 #undef CONFIG_DRIVER_TI_EMAC_USE_RMII 189 #define CONFIG_BOOTP_DEFAULT 190 #define CONFIG_BOOTP_DNS 191 #define CONFIG_BOOTP_DNS2 192 #define CONFIG_BOOTP_SEND_HOSTNAME 193 #define CONFIG_NET_RETRY_COUNT 10 194 #define CONFIG_NET_MULTI 195 #endif 196 197 /* 198 * U-Boot general configuration 199 */ 200 #define CONFIG_SYS_GENERIC_BOARD 201 #define CONFIG_MISC_INIT_R 202 #define CONFIG_BOARD_EARLY_INIT_F 203 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 204 #define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */ 205 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 206 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 207 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 208 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 209 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 210 #define CONFIG_VERSION_VARIABLE 211 #define CONFIG_AUTO_COMPLETE 212 #define CONFIG_SYS_HUSH_PARSER 213 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 214 #define CONFIG_CMDLINE_EDITING 215 #define CONFIG_SYS_LONGHELP 216 #define CONFIG_CRC32_VERIFY 217 #define CONFIG_MX_CYCLIC 218 #define CONFIG_OF_LIBFDT 219 220 /* 221 * Linux Information 222 */ 223 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 224 #define CONFIG_CMDLINE_TAG 225 #define CONFIG_REVISION_TAG 226 #define CONFIG_SETUP_MEMORY_TAGS 227 #define CONFIG_BOOTARGS "console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off" 228 #define CONFIG_BOOTCOMMAND "if mmc rescan 0; then if fatload mmc 0 0xc0600000 boot.scr; then source 0xc0600000; else fatload mmc 0 0xc0700000 uImage; bootm c0700000; fi; else sf probe 0; sf read 0xc0700000 0x80000 0x220000; bootm 0xc0700000; fi" 229 #define CONFIG_BOOTDELAY 3 230 231 /* 232 * U-Boot commands 233 */ 234 #include <config_cmd_default.h> 235 #define CONFIG_CMD_ENV 236 #define CONFIG_CMD_ASKENV 237 #define CONFIG_CMD_DHCP 238 #define CONFIG_CMD_DIAG 239 #define CONFIG_CMD_MII 240 #define CONFIG_CMD_PING 241 #define CONFIG_CMD_SAVES 242 #define CONFIG_CMD_MEMORY 243 #ifdef CONFIG_CMD_BDI 244 #define CONFIG_CLOCKS 245 #endif 246 247 #ifndef CONFIG_DRIVER_TI_EMAC 248 #undef CONFIG_CMD_NET 249 #undef CONFIG_CMD_DHCP 250 #undef CONFIG_CMD_MII 251 #undef CONFIG_CMD_PING 252 #endif 253 254 #ifdef CONFIG_USE_NAND 255 #undef CONFIG_CMD_FLASH 256 #undef CONFIG_CMD_IMLS 257 #define CONFIG_CMD_NAND 258 259 #define CONFIG_CMD_MTDPARTS 260 #define CONFIG_MTD_DEVICE 261 #define CONFIG_MTD_PARTITIONS 262 #define CONFIG_LZO 263 #define CONFIG_RBTREE 264 #define CONFIG_CMD_UBI 265 #define CONFIG_CMD_UBIFS 266 #endif 267 268 #ifdef CONFIG_USE_SPIFLASH 269 #undef CONFIG_CMD_IMLS 270 #undef CONFIG_CMD_FLASH 271 #define CONFIG_CMD_SPI 272 #define CONFIG_CMD_SF 273 #define CONFIG_CMD_SAVEENV 274 #endif 275 276 #if !defined(CONFIG_USE_NAND) && \ 277 !defined(CONFIG_SYS_USE_NOR) && \ 278 !defined(CONFIG_USE_SPIFLASH) 279 #define CONFIG_ENV_IS_NOWHERE 280 #define CONFIG_SYS_NO_FLASH 281 #define CONFIG_ENV_SIZE (16 << 10) 282 #undef CONFIG_CMD_IMLS 283 #undef CONFIG_CMD_ENV 284 #endif 285 286 /* SD/MMC */ 287 #define CONFIG_MMC 288 #define CONFIG_GENERIC_MMC 289 #define CONFIG_DAVINCI_MMC 290 291 #ifdef CONFIG_MMC 292 #define CONFIG_DOS_PARTITION 293 #define CONFIG_CMD_EXT2 294 #define CONFIG_CMD_FAT 295 #define CONFIG_CMD_MMC 296 #undef CONFIG_ENV_IS_IN_MMC 297 #endif 298 299 #ifdef CONFIG_ENV_IS_IN_MMC 300 #undef CONFIG_ENV_SIZE 301 #undef CONFIG_ENV_OFFSET 302 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 303 #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ 304 #undef CONFIG_ENV_IS_IN_FLASH 305 #undef CONFIG_ENV_IS_IN_NAND 306 #undef CONFIG_ENV_IS_IN_SPI_FLASH 307 #endif 308 309 #ifndef CONFIG_DIRECT_NOR_BOOT 310 /* defines for SPL */ 311 #define CONFIG_SPL_FRAMEWORK 312 #define CONFIG_SPL_BOARD_INIT 313 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 314 CONFIG_SYS_MALLOC_LEN) 315 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 316 #define CONFIG_SPL_SERIAL_SUPPORT 317 #define CONFIG_SPL_LIBCOMMON_SUPPORT 318 #define CONFIG_SPL_LIBGENERIC_SUPPORT 319 #define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds" 320 #define CONFIG_SPL_STACK 0x8001ff00 321 #define CONFIG_SPL_TEXT_BASE 0x80000000 322 #define CONFIG_SPL_MAX_FOOTPRINT 32768 323 #define CONFIG_SPL_PAD_TO 32768 324 #endif 325 326 /* additions for new relocation code, must added to all boards */ 327 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 328 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 329 GENERATED_GBL_DATA_SIZE) 330 #endif /* __CONFIG_H */ 331