1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on davinci_dvevm.h. Original Copyrights follow: 5 * 6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * Board 16 */ 17 #define CONFIG_DRIVER_TI_EMAC 18 #undef CONFIG_USE_SPIFLASH 19 #undef CONFIG_SYS_USE_NOR 20 #define CONFIG_USE_NAND 21 22 /* 23 * SoC Configuration 24 */ 25 #define CONFIG_MACH_OMAPL138_LCDK 26 #define CONFIG_ARM926EJS /* arm926ejs CPU core */ 27 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 28 #define CONFIG_SYS_OSCIN_FREQ 24000000 29 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 30 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 31 #define CONFIG_SYS_HZ 1000 32 #define CONFIG_SKIP_LOWLEVEL_INIT 33 #define CONFIG_SYS_TEXT_BASE 0xc1080000 34 35 /* 36 * Memory Info 37 */ 38 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 39 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 40 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ 41 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 42 43 /* memtest start addr */ 44 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 45 46 /* memtest will be run on 16MB */ 47 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 48 49 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 50 51 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 52 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 53 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 54 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 55 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 56 DAVINCI_SYSCFG_SUSPSRC_I2C) 57 58 /* 59 * PLL configuration 60 */ 61 #define CONFIG_SYS_DV_CLKMODE 0 62 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 63 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 64 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 65 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 66 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 67 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 68 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 69 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 70 71 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 72 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 73 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 74 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003 75 76 #define CONFIG_SYS_DA850_PLL0_PLLM 37 77 #define CONFIG_SYS_DA850_PLL1_PLLM 21 78 79 /* 80 * DDR2 memory configuration 81 */ 82 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 83 DV_DDR_PHY_EXT_STRBEN | \ 84 (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 85 86 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 87 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ 88 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 89 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 90 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 91 (4 << DV_DDR_SDCR_CL_SHIFT) | \ 92 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ 93 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 94 95 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 96 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 97 98 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 99 (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 100 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ 101 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 102 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ 103 (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 104 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 105 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 106 (1 << DV_DDR_SDTMR1_WTR_SHIFT)) 107 108 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 109 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 110 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ 111 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 112 (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 113 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 114 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 115 (2 << DV_DDR_SDTMR2_CKE_SHIFT)) 116 117 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492 118 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 119 120 /* 121 * Serial Driver info 122 */ 123 #define CONFIG_SYS_NS16550_SERIAL 124 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 125 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 126 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 127 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 128 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 129 130 #define CONFIG_SPI 131 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE 132 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) 133 #define CONFIG_SF_DEFAULT_SPEED 30000000 134 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 135 136 #ifdef CONFIG_USE_SPIFLASH 137 #define CONFIG_SPL_SPI_LOAD 138 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 139 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 140 #endif 141 142 /* 143 * I2C Configuration 144 */ 145 #define CONFIG_SYS_I2C 146 #define CONFIG_SYS_I2C_DAVINCI 147 #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 148 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ 149 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 150 151 /* 152 * Flash & Environment 153 */ 154 #ifdef CONFIG_USE_NAND 155 #define CONFIG_NAND_DAVINCI 156 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 157 #define CONFIG_ENV_SIZE (128 << 9) 158 #define CONFIG_SYS_NAND_USE_FLASH_BBT 159 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 160 #define CONFIG_SYS_NAND_PAGE_2K 161 #define CONFIG_SYS_NAND_CS 3 162 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 163 #define CONFIG_SYS_NAND_MASK_CLE 0x10 164 #define CONFIG_SYS_NAND_MASK_ALE 0x8 165 #undef CONFIG_SYS_NAND_HW_ECC 166 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 167 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 168 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC 169 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 170 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) 171 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 172 #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K 173 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 174 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 175 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 176 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 177 CONFIG_SYS_MALLOC_LEN - \ 178 GENERATED_GBL_DATA_SIZE) 179 #define CONFIG_SYS_NAND_ECCPOS { \ 180 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 181 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 182 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 183 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 } 184 #define CONFIG_SYS_NAND_PAGE_COUNT 64 185 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 186 #define CONFIG_SYS_NAND_ECCSIZE 512 187 #define CONFIG_SYS_NAND_ECCBYTES 10 188 #define CONFIG_SYS_NAND_OOBSIZE 64 189 #define CONFIG_SPL_NAND_BASE 190 #define CONFIG_SPL_NAND_DRIVERS 191 #define CONFIG_SPL_NAND_ECC 192 #define CONFIG_SPL_NAND_LOAD 193 #endif 194 195 #ifdef CONFIG_SYS_USE_NOR 196 #define CONFIG_FLASH_CFI_DRIVER 197 #define CONFIG_SYS_FLASH_CFI 198 #define CONFIG_SYS_FLASH_PROTECTION 199 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 200 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 201 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) 202 #define CONFIG_ENV_SIZE (128 << 10) 203 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 204 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ 205 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ 206 + 3) 207 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 208 #endif 209 210 #ifdef CONFIG_USE_SPIFLASH 211 #define CONFIG_ENV_SIZE (64 << 10) 212 #define CONFIG_ENV_OFFSET (256 << 10) 213 #define CONFIG_ENV_SECT_SIZE (64 << 10) 214 #endif 215 216 /* 217 * Network & Ethernet Configuration 218 */ 219 #ifdef CONFIG_DRIVER_TI_EMAC 220 #define CONFIG_MII 221 #undef CONFIG_DRIVER_TI_EMAC_USE_RMII 222 #define CONFIG_BOOTP_DEFAULT 223 #define CONFIG_BOOTP_DNS 224 #define CONFIG_BOOTP_DNS2 225 #define CONFIG_BOOTP_SEND_HOSTNAME 226 #define CONFIG_NET_RETRY_COUNT 10 227 #endif 228 229 /* 230 * U-Boot general configuration 231 */ 232 #define CONFIG_MISC_INIT_R 233 #define CONFIG_BOOTFILE "zImage" /* Boot file name */ 234 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 235 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 236 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 237 #define CONFIG_AUTO_COMPLETE 238 #define CONFIG_CMDLINE_EDITING 239 #define CONFIG_SYS_LONGHELP 240 #define CONFIG_MX_CYCLIC 241 242 /* 243 * Linux Information 244 */ 245 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 246 #define CONFIG_CMDLINE_TAG 247 #define CONFIG_REVISION_TAG 248 #define CONFIG_SETUP_MEMORY_TAGS 249 #define CONFIG_BOOTCOMMAND \ 250 "run envboot; " \ 251 "run mmcboot; " 252 253 #define DEFAULT_LINUX_BOOT_ENV \ 254 "loadaddr=0xc0700000\0" \ 255 "fdtaddr=0xc0600000\0" \ 256 "scriptaddr=0xc0600000\0" 257 258 #include <environment/ti/mmc.h> 259 260 #define CONFIG_EXTRA_ENV_SETTINGS \ 261 DEFAULT_LINUX_BOOT_ENV \ 262 DEFAULT_MMC_TI_ARGS \ 263 "bootpart=0:2\0" \ 264 "bootdir=/boot\0" \ 265 "bootfile=zImage\0" \ 266 "fdtfile=da850-lcdk.dtb\0" \ 267 "boot_fdt=yes\0" \ 268 "boot_fit=0\0" \ 269 "console=ttyS2,115200n8\0" 270 271 #ifdef CONFIG_CMD_BDI 272 #define CONFIG_CLOCKS 273 #endif 274 275 #ifndef CONFIG_DRIVER_TI_EMAC 276 #endif 277 278 #ifdef CONFIG_USE_NAND 279 #define CONFIG_MTD_DEVICE 280 #define CONFIG_MTD_PARTITIONS 281 #endif 282 283 #if !defined(CONFIG_USE_NAND) && \ 284 !defined(CONFIG_SYS_USE_NOR) && \ 285 !defined(CONFIG_USE_SPIFLASH) 286 #define CONFIG_ENV_SIZE (16 << 10) 287 #endif 288 289 /* SD/MMC */ 290 291 #ifdef CONFIG_ENV_IS_IN_MMC 292 #undef CONFIG_ENV_SIZE 293 #undef CONFIG_ENV_OFFSET 294 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 295 #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ 296 #endif 297 298 #ifndef CONFIG_DIRECT_NOR_BOOT 299 /* defines for SPL */ 300 #define CONFIG_SPL_FRAMEWORK 301 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 302 CONFIG_SYS_MALLOC_LEN) 303 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 304 #define CONFIG_SPL_STACK 0x8001ff00 305 #define CONFIG_SPL_TEXT_BASE 0x80000000 306 #define CONFIG_SPL_MAX_FOOTPRINT 32768 307 #define CONFIG_SPL_PAD_TO 32768 308 #endif 309 310 /* additions for new relocation code, must added to all boards */ 311 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 312 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 313 GENERATED_GBL_DATA_SIZE) 314 315 #include <asm/arch/hardware.h> 316 317 #endif /* __CONFIG_H */ 318