1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on davinci_dvevm.h. Original Copyrights follow: 5 * 6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * Board 16 */ 17 #define CONFIG_DRIVER_TI_EMAC 18 #undef CONFIG_USE_SPIFLASH 19 #undef CONFIG_SYS_USE_NOR 20 #define CONFIG_USE_NAND 21 22 /* 23 * Disable DM_* for SPL build and can be re-enabled after adding 24 * DM support in SPL 25 */ 26 #ifdef CONFIG_SPL_BUILD 27 #undef CONFIG_DM_I2C 28 #undef CONFIG_DM_I2C_COMPAT 29 #endif 30 /* 31 * SoC Configuration 32 */ 33 #define CONFIG_MACH_OMAPL138_LCDK 34 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 35 #define CONFIG_SYS_OSCIN_FREQ 24000000 36 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 37 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 38 #define CONFIG_SYS_HZ 1000 39 #define CONFIG_SKIP_LOWLEVEL_INIT 40 41 /* 42 * Memory Info 43 */ 44 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 45 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 46 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ 47 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 48 49 /* memtest start addr */ 50 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 51 52 /* memtest will be run on 16MB */ 53 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 54 55 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 56 57 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 58 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 59 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 60 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 61 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 62 DAVINCI_SYSCFG_SUSPSRC_I2C) 63 64 /* 65 * PLL configuration 66 */ 67 68 /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */ 69 #define CONFIG_SYS_DA850_PLL0_PLLM 18 70 #define CONFIG_SYS_DA850_PLL1_PLLM 21 71 72 /* 73 * DDR2 memory configuration 74 */ 75 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 76 DV_DDR_PHY_EXT_STRBEN | \ 77 (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 78 79 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 80 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ 81 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 82 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 83 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 84 (4 << DV_DDR_SDCR_CL_SHIFT) | \ 85 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ 86 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 87 88 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 89 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 90 91 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 92 (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 93 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ 94 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 95 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ 96 (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 97 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 98 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 99 (1 << DV_DDR_SDTMR1_WTR_SHIFT)) 100 101 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 102 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 103 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ 104 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 105 (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 106 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 107 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 108 (2 << DV_DDR_SDTMR2_CKE_SHIFT)) 109 110 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492 111 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 112 113 /* 114 * Serial Driver info 115 */ 116 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 117 #if !defined(CONFIG_DM_SERIAL) 118 #define CONFIG_SYS_NS16550_SERIAL 119 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 120 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 121 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 122 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 123 #endif 124 125 #define CONFIG_SPI 126 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE 127 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) 128 #define CONFIG_SF_DEFAULT_SPEED 30000000 129 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 130 131 #ifdef CONFIG_USE_SPIFLASH 132 #define CONFIG_SPL_SPI_LOAD 133 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 134 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 135 #endif 136 137 /* 138 * I2C Configuration 139 */ 140 #define CONFIG_SYS_I2C_DAVINCI 141 #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 142 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ 143 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 144 145 /* 146 * Flash & Environment 147 */ 148 #ifdef CONFIG_USE_NAND 149 #define CONFIG_NAND_DAVINCI 150 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 151 #define CONFIG_ENV_SIZE (128 << 9) 152 #define CONFIG_SYS_NAND_USE_FLASH_BBT 153 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 154 #define CONFIG_SYS_NAND_PAGE_2K 155 #define CONFIG_SYS_NAND_CS 3 156 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 157 #define CONFIG_SYS_NAND_MASK_CLE 0x10 158 #define CONFIG_SYS_NAND_MASK_ALE 0x8 159 #undef CONFIG_SYS_NAND_HW_ECC 160 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 161 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 162 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC 163 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 164 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) 165 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 166 #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K 167 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 168 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 169 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 170 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 171 CONFIG_SYS_MALLOC_LEN - \ 172 GENERATED_GBL_DATA_SIZE) 173 #define CONFIG_SYS_NAND_ECCPOS { \ 174 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 175 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 176 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 177 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 } 178 #define CONFIG_SYS_NAND_PAGE_COUNT 64 179 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 180 #define CONFIG_SYS_NAND_ECCSIZE 512 181 #define CONFIG_SYS_NAND_ECCBYTES 10 182 #define CONFIG_SYS_NAND_OOBSIZE 64 183 #define CONFIG_SPL_NAND_BASE 184 #define CONFIG_SPL_NAND_DRIVERS 185 #define CONFIG_SPL_NAND_ECC 186 #define CONFIG_SPL_NAND_LOAD 187 #endif 188 189 #ifdef CONFIG_SYS_USE_NOR 190 #define CONFIG_FLASH_CFI_DRIVER 191 #define CONFIG_SYS_FLASH_CFI 192 #define CONFIG_SYS_FLASH_PROTECTION 193 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 194 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 195 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) 196 #define CONFIG_ENV_SIZE (128 << 10) 197 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 198 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ 199 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ 200 + 3) 201 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 202 #endif 203 204 #ifdef CONFIG_USE_SPIFLASH 205 #define CONFIG_ENV_SIZE (64 << 10) 206 #define CONFIG_ENV_OFFSET (256 << 10) 207 #define CONFIG_ENV_SECT_SIZE (64 << 10) 208 #endif 209 210 /* 211 * Network & Ethernet Configuration 212 */ 213 #ifdef CONFIG_DRIVER_TI_EMAC 214 #define CONFIG_MII 215 #undef CONFIG_DRIVER_TI_EMAC_USE_RMII 216 #define CONFIG_BOOTP_DEFAULT 217 #define CONFIG_BOOTP_DNS2 218 #define CONFIG_BOOTP_SEND_HOSTNAME 219 #define CONFIG_NET_RETRY_COUNT 10 220 #endif 221 222 /* 223 * U-Boot general configuration 224 */ 225 #define CONFIG_MISC_INIT_R 226 #define CONFIG_BOOTFILE "zImage" /* Boot file name */ 227 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 228 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 229 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 230 #define CONFIG_MX_CYCLIC 231 232 /* 233 * Linux Information 234 */ 235 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 236 #define CONFIG_CMDLINE_TAG 237 #define CONFIG_REVISION_TAG 238 #define CONFIG_SETUP_MEMORY_TAGS 239 #define CONFIG_BOOTCOMMAND \ 240 "run envboot; " \ 241 "run mmcboot; " 242 243 #define DEFAULT_LINUX_BOOT_ENV \ 244 "loadaddr=0xc0700000\0" \ 245 "fdtaddr=0xc0600000\0" \ 246 "scriptaddr=0xc0600000\0" 247 248 #include <environment/ti/mmc.h> 249 250 #define CONFIG_EXTRA_ENV_SETTINGS \ 251 DEFAULT_LINUX_BOOT_ENV \ 252 DEFAULT_MMC_TI_ARGS \ 253 "bootpart=0:2\0" \ 254 "bootdir=/boot\0" \ 255 "bootfile=zImage\0" \ 256 "fdtfile=da850-lcdk.dtb\0" \ 257 "boot_fdt=yes\0" \ 258 "boot_fit=0\0" \ 259 "console=ttyS2,115200n8\0" 260 261 #ifdef CONFIG_CMD_BDI 262 #define CONFIG_CLOCKS 263 #endif 264 265 #ifndef CONFIG_DRIVER_TI_EMAC 266 #endif 267 268 #ifdef CONFIG_USE_NAND 269 #define CONFIG_MTD_DEVICE 270 #define CONFIG_MTD_PARTITIONS 271 #endif 272 273 #if !defined(CONFIG_USE_NAND) && \ 274 !defined(CONFIG_SYS_USE_NOR) && \ 275 !defined(CONFIG_USE_SPIFLASH) 276 #define CONFIG_ENV_SIZE (16 << 10) 277 #endif 278 279 /* SD/MMC */ 280 281 #ifdef CONFIG_ENV_IS_IN_MMC 282 #undef CONFIG_ENV_SIZE 283 #undef CONFIG_ENV_OFFSET 284 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 285 #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ 286 #endif 287 288 #ifndef CONFIG_DIRECT_NOR_BOOT 289 /* defines for SPL */ 290 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 291 CONFIG_SYS_MALLOC_LEN) 292 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 293 #define CONFIG_SPL_STACK 0x8001ff00 294 #define CONFIG_SPL_TEXT_BASE 0x80000000 295 #define CONFIG_SPL_MAX_FOOTPRINT 32768 296 #define CONFIG_SPL_PAD_TO 32768 297 #endif 298 299 /* additions for new relocation code, must added to all boards */ 300 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 301 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 302 GENERATED_GBL_DATA_SIZE) 303 304 #include <asm/arch/hardware.h> 305 306 #endif /* __CONFIG_H */ 307