1 /*
2  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  * Based on davinci_dvevm.h. Original Copyrights follow:
5  *
6  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
7  *
8  * SPDX-License-Identifier:	GPL-2.0
9  */
10 
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /*
15  * Board
16  */
17 #define CONFIG_DRIVER_TI_EMAC
18 #undef CONFIG_USE_SPIFLASH
19 #undef	CONFIG_SYS_USE_NOR
20 #define	CONFIG_USE_NAND
21 
22 /*
23  * SoC Configuration
24  */
25 #define CONFIG_MACH_OMAPL138_LCDK
26 #define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
27 #define CONFIG_SYS_OSCIN_FREQ		24000000
28 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
29 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
30 #define CONFIG_SYS_HZ			1000
31 #define CONFIG_SKIP_LOWLEVEL_INIT
32 
33 /*
34  * Memory Info
35  */
36 #define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
37 #define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
38 #define PHYS_SDRAM_1_SIZE	(128 << 20) /* SDRAM size 128MB */
39 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
40 
41 /* memtest start addr */
42 #define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
43 
44 /* memtest will be run on 16MB */
45 #define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
46 
47 #define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
48 
49 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
50 	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
51 	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
52 	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
53 	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
54 	DAVINCI_SYSCFG_SUSPSRC_I2C)
55 
56 /*
57  * PLL configuration
58  */
59 
60 #define CONFIG_SYS_DA850_PLL0_PLLM     37
61 #define CONFIG_SYS_DA850_PLL1_PLLM     21
62 
63 /*
64  * DDR2 memory configuration
65  */
66 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
67 					DV_DDR_PHY_EXT_STRBEN | \
68 					(0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
69 
70 #define CONFIG_SYS_DA850_DDR2_SDBCR (		  \
71 	(1 << DV_DDR_SDCR_DDR2EN_SHIFT)		| \
72 	(1 << DV_DDR_SDCR_DDREN_SHIFT)		| \
73 	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT)	| \
74 	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)	| \
75 	(4 << DV_DDR_SDCR_CL_SHIFT)		| \
76 	(3 << DV_DDR_SDCR_IBANK_SHIFT)		| \
77 	(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
78 
79 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
80 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
81 
82 #define CONFIG_SYS_DA850_DDR2_SDTIMR (		  \
83 	(19 << DV_DDR_SDTMR1_RFC_SHIFT)		| \
84 	(1 << DV_DDR_SDTMR1_RP_SHIFT)		| \
85 	(1 << DV_DDR_SDTMR1_RCD_SHIFT)		| \
86 	(2 << DV_DDR_SDTMR1_WR_SHIFT)		| \
87 	(6 << DV_DDR_SDTMR1_RAS_SHIFT)		| \
88 	(8 << DV_DDR_SDTMR1_RC_SHIFT)		| \
89 	(1 << DV_DDR_SDTMR1_RRD_SHIFT)		| \
90 	(1 << DV_DDR_SDTMR1_WTR_SHIFT))
91 
92 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		  \
93 	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT)	| \
94 	(2 << DV_DDR_SDTMR2_XP_SHIFT)		| \
95 	(0 << DV_DDR_SDTMR2_ODT_SHIFT)		| \
96 	(20 << DV_DDR_SDTMR2_XSNR_SHIFT)	| \
97 	(199 << DV_DDR_SDTMR2_XSRD_SHIFT)	| \
98 	(1 << DV_DDR_SDTMR2_RTP_SHIFT)		| \
99 	(2 << DV_DDR_SDTMR2_CKE_SHIFT))
100 
101 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000492
102 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
103 
104 /*
105  * Serial Driver info
106  */
107 #define CONFIG_SYS_NS16550_SERIAL
108 #define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
109 #define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
110 #define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
111 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
112 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
113 
114 #define CONFIG_SPI
115 #define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
116 #define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
117 #define CONFIG_SF_DEFAULT_SPEED		30000000
118 #define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
119 
120 #ifdef CONFIG_USE_SPIFLASH
121 #define CONFIG_SPL_SPI_LOAD
122 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
123 #define CONFIG_SYS_SPI_U_BOOT_SIZE	0x30000
124 #endif
125 
126 /*
127  * I2C Configuration
128  */
129 #define CONFIG_SYS_I2C
130 #define CONFIG_SYS_I2C_DAVINCI
131 #define CONFIG_SYS_DAVINCI_I2C_SPEED	25000
132 #define CONFIG_SYS_DAVINCI_I2C_SLAVE	10 /* Bogus, master-only in U-Boot */
133 #define CONFIG_SYS_I2C_EXPANDER_ADDR	0x20
134 
135 /*
136  * Flash & Environment
137  */
138 #ifdef CONFIG_USE_NAND
139 #define CONFIG_NAND_DAVINCI
140 #define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
141 #define CONFIG_ENV_SIZE			(128 << 9)
142 #define	CONFIG_SYS_NAND_USE_FLASH_BBT
143 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
144 #define	CONFIG_SYS_NAND_PAGE_2K
145 #define CONFIG_SYS_NAND_CS		3
146 #define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
147 #define CONFIG_SYS_NAND_MASK_CLE	0x10
148 #define CONFIG_SYS_NAND_MASK_ALE	0x8
149 #undef CONFIG_SYS_NAND_HW_ECC
150 #define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
151 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
152 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
153 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
154 #define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
155 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
156 #define CONFIG_SYS_NAND_U_BOOT_SIZE	SZ_512K
157 #define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
158 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
159 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
160 					CONFIG_SYS_NAND_U_BOOT_SIZE - \
161 					CONFIG_SYS_MALLOC_LEN -       \
162 					GENERATED_GBL_DATA_SIZE)
163 #define CONFIG_SYS_NAND_ECCPOS		{				\
164 				6, 7, 8, 9, 10, 11, 12, 13, 14, 15,	\
165 				22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
166 				38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
167 				54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
168 #define CONFIG_SYS_NAND_PAGE_COUNT	64
169 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
170 #define CONFIG_SYS_NAND_ECCSIZE		512
171 #define CONFIG_SYS_NAND_ECCBYTES	10
172 #define CONFIG_SYS_NAND_OOBSIZE		64
173 #define CONFIG_SPL_NAND_BASE
174 #define CONFIG_SPL_NAND_DRIVERS
175 #define CONFIG_SPL_NAND_ECC
176 #define CONFIG_SPL_NAND_LOAD
177 #endif
178 
179 #ifdef CONFIG_SYS_USE_NOR
180 #define CONFIG_FLASH_CFI_DRIVER
181 #define CONFIG_SYS_FLASH_CFI
182 #define CONFIG_SYS_FLASH_PROTECTION
183 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* max number of flash banks */
184 #define CONFIG_SYS_FLASH_SECT_SZ	(128 << 10) /* 128KB */
185 #define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ * 3)
186 #define CONFIG_ENV_SIZE			(128 << 10)
187 #define CONFIG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
188 #define PHYS_FLASH_SIZE			(8 << 20) /* Flash size 8MB */
189 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
190 	       + 3)
191 #define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_FLASH_SECT_SZ
192 #endif
193 
194 #ifdef CONFIG_USE_SPIFLASH
195 #define CONFIG_ENV_SIZE			(64 << 10)
196 #define CONFIG_ENV_OFFSET		(256 << 10)
197 #define CONFIG_ENV_SECT_SIZE		(64 << 10)
198 #endif
199 
200 /*
201  * Network & Ethernet Configuration
202  */
203 #ifdef CONFIG_DRIVER_TI_EMAC
204 #define CONFIG_MII
205 #undef	CONFIG_DRIVER_TI_EMAC_USE_RMII
206 #define CONFIG_BOOTP_DEFAULT
207 #define CONFIG_BOOTP_DNS2
208 #define CONFIG_BOOTP_SEND_HOSTNAME
209 #define CONFIG_NET_RETRY_COUNT	10
210 #endif
211 
212 /*
213  * U-Boot general configuration
214  */
215 #define CONFIG_MISC_INIT_R
216 #define CONFIG_BOOTFILE		"zImage" /* Boot file name */
217 #define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
218 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
219 #define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
220 #define CONFIG_MX_CYCLIC
221 
222 /*
223  * Linux Information
224  */
225 #define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
226 #define CONFIG_CMDLINE_TAG
227 #define CONFIG_REVISION_TAG
228 #define CONFIG_SETUP_MEMORY_TAGS
229 #define CONFIG_BOOTCOMMAND \
230 		"run envboot; " \
231 		"run mmcboot; "
232 
233 #define DEFAULT_LINUX_BOOT_ENV \
234 	"loadaddr=0xc0700000\0" \
235 	"fdtaddr=0xc0600000\0" \
236 	"scriptaddr=0xc0600000\0"
237 
238 #include <environment/ti/mmc.h>
239 
240 #define CONFIG_EXTRA_ENV_SETTINGS \
241 	DEFAULT_LINUX_BOOT_ENV \
242 	DEFAULT_MMC_TI_ARGS \
243 	"bootpart=0:2\0" \
244 	"bootdir=/boot\0" \
245 	"bootfile=zImage\0" \
246 	"fdtfile=da850-lcdk.dtb\0" \
247 	"boot_fdt=yes\0" \
248 	"boot_fit=0\0" \
249 	"console=ttyS2,115200n8\0"
250 
251 #ifdef CONFIG_CMD_BDI
252 #define CONFIG_CLOCKS
253 #endif
254 
255 #ifndef CONFIG_DRIVER_TI_EMAC
256 #endif
257 
258 #ifdef CONFIG_USE_NAND
259 #define CONFIG_MTD_DEVICE
260 #define CONFIG_MTD_PARTITIONS
261 #endif
262 
263 #if !defined(CONFIG_USE_NAND) && \
264 	!defined(CONFIG_SYS_USE_NOR) && \
265 	!defined(CONFIG_USE_SPIFLASH)
266 #define CONFIG_ENV_SIZE		(16 << 10)
267 #endif
268 
269 /* SD/MMC */
270 
271 #ifdef CONFIG_ENV_IS_IN_MMC
272 #undef CONFIG_ENV_SIZE
273 #undef CONFIG_ENV_OFFSET
274 #define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
275 #define CONFIG_ENV_OFFSET	(51 << 9)	/* Sector 51 */
276 #endif
277 
278 #ifndef CONFIG_DIRECT_NOR_BOOT
279 /* defines for SPL */
280 #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
281 						CONFIG_SYS_MALLOC_LEN)
282 #define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
283 #define CONFIG_SPL_STACK	0x8001ff00
284 #define CONFIG_SPL_TEXT_BASE	0x80000000
285 #define CONFIG_SPL_MAX_FOOTPRINT	32768
286 #define CONFIG_SPL_PAD_TO	32768
287 #endif
288 
289 /* additions for new relocation code, must added to all boards */
290 #define CONFIG_SYS_SDRAM_BASE		0xc0000000
291 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
292 					GENERATED_GBL_DATA_SIZE)
293 
294 #include <asm/arch/hardware.h>
295 
296 #endif /* __CONFIG_H */
297