1 /*
2  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  * Based on davinci_dvevm.h. Original Copyrights follow:
5  *
6  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
7  *
8  * SPDX-License-Identifier:	GPL-2.0
9  */
10 
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /*
15  * Board
16  */
17 #define CONFIG_DRIVER_TI_EMAC
18 #undef CONFIG_USE_SPIFLASH
19 #undef	CONFIG_SYS_USE_NOR
20 #define	CONFIG_USE_NAND
21 
22 /*
23  * SoC Configuration
24  */
25 #define CONFIG_MACH_OMAPL138_LCDK
26 #define CONFIG_ARM926EJS		/* arm926ejs CPU core */
27 #define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
28 #define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
29 #define CONFIG_SYS_OSCIN_FREQ		24000000
30 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
31 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
32 #define CONFIG_SYS_HZ			1000
33 #define CONFIG_SKIP_LOWLEVEL_INIT
34 #define CONFIG_SYS_TEXT_BASE		0xc1080000
35 
36 /*
37  * Memory Info
38  */
39 #define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
40 #define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
41 #define PHYS_SDRAM_1_SIZE	(128 << 20) /* SDRAM size 128MB */
42 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
43 
44 /* memtest start addr */
45 #define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
46 
47 /* memtest will be run on 16MB */
48 #define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
49 
50 #define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
51 #define CONFIG_STACKSIZE	(256*1024) /* regular stack */
52 
53 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
54 	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
55 	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
56 	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
57 	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
58 	DAVINCI_SYSCFG_SUSPSRC_I2C)
59 
60 /*
61  * PLL configuration
62  */
63 #define CONFIG_SYS_DV_CLKMODE          0
64 #define CONFIG_SYS_DA850_PLL0_POSTDIV  1
65 #define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
66 #define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
67 #define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
68 #define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
69 #define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
70 #define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
71 #define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
72 
73 #define CONFIG_SYS_DA850_PLL1_POSTDIV  1
74 #define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
75 #define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
76 #define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8003
77 
78 #define CONFIG_SYS_DA850_PLL0_PLLM     37
79 #define CONFIG_SYS_DA850_PLL1_PLLM     21
80 
81 /*
82  * DDR2 memory configuration
83  */
84 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
85 					DV_DDR_PHY_EXT_STRBEN | \
86 					(0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
87 
88 #define CONFIG_SYS_DA850_DDR2_SDBCR (		  \
89 	(1 << DV_DDR_SDCR_DDR2EN_SHIFT)		| \
90 	(1 << DV_DDR_SDCR_DDREN_SHIFT)		| \
91 	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT)	| \
92 	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)	| \
93 	(4 << DV_DDR_SDCR_CL_SHIFT)		| \
94 	(3 << DV_DDR_SDCR_IBANK_SHIFT)		| \
95 	(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
96 
97 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
98 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
99 
100 #define CONFIG_SYS_DA850_DDR2_SDTIMR (		  \
101 	(19 << DV_DDR_SDTMR1_RFC_SHIFT)		| \
102 	(1 << DV_DDR_SDTMR1_RP_SHIFT)		| \
103 	(1 << DV_DDR_SDTMR1_RCD_SHIFT)		| \
104 	(2 << DV_DDR_SDTMR1_WR_SHIFT)		| \
105 	(6 << DV_DDR_SDTMR1_RAS_SHIFT)		| \
106 	(8 << DV_DDR_SDTMR1_RC_SHIFT)		| \
107 	(1 << DV_DDR_SDTMR1_RRD_SHIFT)		| \
108 	(1 << DV_DDR_SDTMR1_WTR_SHIFT))
109 
110 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		  \
111 	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT)	| \
112 	(2 << DV_DDR_SDTMR2_XP_SHIFT)		| \
113 	(0 << DV_DDR_SDTMR2_ODT_SHIFT)		| \
114 	(10 << DV_DDR_SDTMR2_XSNR_SHIFT)	| \
115 	(199 << DV_DDR_SDTMR2_XSRD_SHIFT)	| \
116 	(1 << DV_DDR_SDTMR2_RTP_SHIFT)		| \
117 	(2 << DV_DDR_SDTMR2_CKE_SHIFT))
118 
119 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000492
120 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
121 
122 /*
123  * Serial Driver info
124  */
125 #define CONFIG_SYS_NS16550_SERIAL
126 #define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
127 #define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
128 #define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
129 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
130 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
131 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
132 
133 #define CONFIG_SPI
134 #define CONFIG_DAVINCI_SPI
135 #define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
136 #define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
137 #define CONFIG_SF_DEFAULT_SPEED		30000000
138 #define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
139 
140 #ifdef CONFIG_USE_SPIFLASH
141 #define CONFIG_SPL_SPI_LOAD
142 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
143 #define CONFIG_SYS_SPI_U_BOOT_SIZE	0x30000
144 #endif
145 
146 /*
147  * I2C Configuration
148  */
149 #define CONFIG_SYS_I2C
150 #define CONFIG_SYS_I2C_DAVINCI
151 #define CONFIG_SYS_DAVINCI_I2C_SPEED	25000
152 #define CONFIG_SYS_DAVINCI_I2C_SLAVE	10 /* Bogus, master-only in U-Boot */
153 #define CONFIG_SYS_I2C_EXPANDER_ADDR	0x20
154 
155 /*
156  * Flash & Environment
157  */
158 #ifdef CONFIG_USE_NAND
159 #undef CONFIG_ENV_IS_IN_FLASH
160 #define CONFIG_NAND_DAVINCI
161 #define CONFIG_SYS_NO_FLASH
162 #define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
163 #define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
164 #define CONFIG_ENV_SIZE			(128 << 9)
165 #define	CONFIG_SYS_NAND_USE_FLASH_BBT
166 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
167 #define	CONFIG_SYS_NAND_PAGE_2K
168 #define	CONFIG_SYS_NAND_BUSWIDTH_16BIT
169 #define CONFIG_SYS_NAND_CS		3
170 #define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
171 #define CONFIG_SYS_NAND_MASK_CLE	0x10
172 #define CONFIG_SYS_NAND_MASK_ALE	0x8
173 #undef CONFIG_SYS_NAND_HW_ECC
174 #define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
175 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
176 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
177 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
178 #define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
179 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
180 #define CONFIG_SYS_NAND_U_BOOT_SIZE	SZ_512K
181 #define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
182 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
183 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
184 					CONFIG_SYS_NAND_U_BOOT_SIZE - \
185 					CONFIG_SYS_MALLOC_LEN -       \
186 					GENERATED_GBL_DATA_SIZE)
187 #define CONFIG_SYS_NAND_ECCPOS		{				\
188 				6, 7, 8, 9, 10, 11, 12, 13, 14, 15,	\
189 				22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
190 				38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
191 				54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
192 #define CONFIG_SYS_NAND_PAGE_COUNT	64
193 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
194 #define CONFIG_SYS_NAND_ECCSIZE		512
195 #define CONFIG_SYS_NAND_ECCBYTES	10
196 #define CONFIG_SYS_NAND_OOBSIZE		64
197 #define CONFIG_SPL_NAND_BASE
198 #define CONFIG_SPL_NAND_DRIVERS
199 #define CONFIG_SPL_NAND_ECC
200 #define CONFIG_SPL_NAND_SIMPLE
201 #define CONFIG_SPL_NAND_LOAD
202 #endif
203 
204 #ifdef CONFIG_SYS_USE_NOR
205 #define CONFIG_ENV_IS_IN_FLASH
206 #undef CONFIG_SYS_NO_FLASH
207 #define CONFIG_FLASH_CFI_DRIVER
208 #define CONFIG_SYS_FLASH_CFI
209 #define CONFIG_SYS_FLASH_PROTECTION
210 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* max number of flash banks */
211 #define CONFIG_SYS_FLASH_SECT_SZ	(128 << 10) /* 128KB */
212 #define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ * 3)
213 #define CONFIG_ENV_SIZE			(128 << 10)
214 #define CONFIG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
215 #define PHYS_FLASH_SIZE			(8 << 20) /* Flash size 8MB */
216 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
217 	       + 3)
218 #define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_FLASH_SECT_SZ
219 #endif
220 
221 #ifdef CONFIG_USE_SPIFLASH
222 #undef CONFIG_ENV_IS_IN_FLASH
223 #undef CONFIG_ENV_IS_IN_NAND
224 #define CONFIG_ENV_IS_IN_SPI_FLASH
225 #define CONFIG_ENV_SIZE			(64 << 10)
226 #define CONFIG_ENV_OFFSET		(256 << 10)
227 #define CONFIG_ENV_SECT_SIZE		(64 << 10)
228 #define CONFIG_SYS_NO_FLASH
229 #endif
230 
231 /*
232  * Network & Ethernet Configuration
233  */
234 #ifdef CONFIG_DRIVER_TI_EMAC
235 #define CONFIG_EMAC_MDIO_PHY_NUM	7
236 #define CONFIG_MII
237 #undef	CONFIG_DRIVER_TI_EMAC_USE_RMII
238 #define CONFIG_BOOTP_DEFAULT
239 #define CONFIG_BOOTP_DNS
240 #define CONFIG_BOOTP_DNS2
241 #define CONFIG_BOOTP_SEND_HOSTNAME
242 #define CONFIG_NET_RETRY_COUNT	10
243 #endif
244 
245 /*
246  * U-Boot general configuration
247  */
248 #define CONFIG_MISC_INIT_R
249 #define CONFIG_BOARD_EARLY_INIT_F
250 #define CONFIG_BOOTFILE		"zImage" /* Boot file name */
251 #define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
252 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
253 #define CONFIG_SYS_MAXARGS	16 /* max number of command args */
254 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
255 #define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
256 #define CONFIG_AUTO_COMPLETE
257 #define CONFIG_CMDLINE_EDITING
258 #define CONFIG_SYS_LONGHELP
259 #define CONFIG_CRC32_VERIFY
260 #define CONFIG_MX_CYCLIC
261 
262 /*
263  * Linux Information
264  */
265 #define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
266 #define CONFIG_CMDLINE_TAG
267 #define CONFIG_REVISION_TAG
268 #define CONFIG_SETUP_MEMORY_TAGS
269 #define CONFIG_BOOTARGS		"console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off"
270 #define CONFIG_BOOTCOMMAND \
271 	"if mmc rescan; then " \
272 		"run mmcboot; " \
273 	"else " \
274 		"run spiboot; " \
275 	"fi"
276 #define CONFIG_EXTRA_ENV_SETTINGS \
277 	"fdtaddr=0xc0600000\0" \
278 	"fdtfile=da850-lcdk.dtb\0" \
279 	"fdtboot=bootz 0xc0700000 - ${fdtaddr};\0" \
280 	"mmcboot=" \
281 		"if fatload mmc 0 0xc0600000 boot.scr; then " \
282 			"source 0xc0600000; " \
283 		"else " \
284 			"fatload mmc 0 0xc0700000 " \
285 				__stringify(CONFIG_BOOTFILE) "; " \
286 			"fatload mmc 0 ${fdtaddr} ${fdtfile}; " \
287 			"run fdtboot; " \
288 		"fi;\0" \
289 	"spiboot=" \
290 		"sf probe 0; " \
291 		"sf read 0xc0700000 0x80000 0x220000; " \
292 		"bootz 0xc0700000;\0"
293 
294 /*
295  * U-Boot commands
296  */
297 #define CONFIG_CMD_ENV
298 #define CONFIG_CMD_DIAG
299 #define CONFIG_CMD_SAVES
300 #ifdef CONFIG_CMD_BDI
301 #define CONFIG_CLOCKS
302 #endif
303 
304 #ifndef CONFIG_DRIVER_TI_EMAC
305 #endif
306 
307 #ifdef CONFIG_USE_NAND
308 #define CONFIG_CMD_NAND
309 
310 #define CONFIG_CMD_MTDPARTS
311 #define CONFIG_MTD_DEVICE
312 #define CONFIG_MTD_PARTITIONS
313 #define CONFIG_LZO
314 #define CONFIG_RBTREE
315 #define CONFIG_CMD_UBIFS
316 #endif
317 
318 #ifdef CONFIG_USE_SPIFLASH
319 #endif
320 
321 #if !defined(CONFIG_USE_NAND) && \
322 	!defined(CONFIG_SYS_USE_NOR) && \
323 	!defined(CONFIG_USE_SPIFLASH)
324 #define CONFIG_ENV_IS_NOWHERE
325 #define CONFIG_SYS_NO_FLASH
326 #define CONFIG_ENV_SIZE		(16 << 10)
327 #undef CONFIG_CMD_ENV
328 #endif
329 
330 /* SD/MMC */
331 #define CONFIG_MMC
332 #define CONFIG_GENERIC_MMC
333 #define CONFIG_DAVINCI_MMC
334 
335 #ifdef CONFIG_MMC
336 #define CONFIG_DOS_PARTITION
337 #undef CONFIG_ENV_IS_IN_MMC
338 #endif
339 
340 #ifdef CONFIG_ENV_IS_IN_MMC
341 #undef CONFIG_ENV_SIZE
342 #undef CONFIG_ENV_OFFSET
343 #define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
344 #define CONFIG_ENV_OFFSET	(51 << 9)	/* Sector 51 */
345 #undef CONFIG_ENV_IS_IN_FLASH
346 #undef CONFIG_ENV_IS_IN_NAND
347 #undef CONFIG_ENV_IS_IN_SPI_FLASH
348 #endif
349 
350 #ifndef CONFIG_DIRECT_NOR_BOOT
351 /* defines for SPL */
352 #define CONFIG_SPL_FRAMEWORK
353 #define CONFIG_SPL_BOARD_INIT
354 #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
355 						CONFIG_SYS_MALLOC_LEN)
356 #define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
357 #define CONFIG_SPL_LDSCRIPT	"board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
358 #define CONFIG_SPL_STACK	0x8001ff00
359 #define CONFIG_SPL_TEXT_BASE	0x80000000
360 #define CONFIG_SPL_MAX_FOOTPRINT	32768
361 #define CONFIG_SPL_PAD_TO	32768
362 #endif
363 
364 /* additions for new relocation code, must added to all boards */
365 #define CONFIG_SYS_SDRAM_BASE		0xc0000000
366 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
367 					GENERATED_GBL_DATA_SIZE)
368 #endif /* __CONFIG_H */
369