1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4  *
5  * Based on davinci_dvevm.h. Original Copyrights follow:
6  *
7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
8  */
9 
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 /*
14  * Board
15  */
16 #undef CONFIG_USE_SPIFLASH
17 #undef	CONFIG_SYS_USE_NOR
18 
19 /*
20 * Disable DM_* for SPL build and can be re-enabled after adding
21 * DM support in SPL
22 */
23 #ifdef CONFIG_SPL_BUILD
24 #undef CONFIG_DM_I2C
25 #undef CONFIG_DM_I2C_COMPAT
26 #endif
27 /*
28  * SoC Configuration
29  */
30 #define CONFIG_MACH_OMAPL138_LCDK
31 #define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
32 #define CONFIG_SYS_OSCIN_FREQ		24000000
33 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
34 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
35 #define CONFIG_SYS_HZ			1000
36 #define CONFIG_SKIP_LOWLEVEL_INIT
37 
38 /*
39  * Memory Info
40  */
41 #define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
42 #define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
43 #define PHYS_SDRAM_1_SIZE	(128 << 20) /* SDRAM size 128MB */
44 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
45 
46 /* memtest start addr */
47 #define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
48 
49 /* memtest will be run on 16MB */
50 #define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
51 
52 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
53 	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
54 	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
55 	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
56 	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
57 	DAVINCI_SYSCFG_SUSPSRC_I2C)
58 
59 /*
60  * PLL configuration
61  */
62 
63 /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
64 #define CONFIG_SYS_DA850_PLL0_PLLM     18
65 #define CONFIG_SYS_DA850_PLL1_PLLM     21
66 
67 /*
68  * DDR2 memory configuration
69  */
70 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
71 					DV_DDR_PHY_EXT_STRBEN | \
72 					(0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
73 
74 #define CONFIG_SYS_DA850_DDR2_SDBCR (		  \
75 	(1 << DV_DDR_SDCR_DDR2EN_SHIFT)		| \
76 	(1 << DV_DDR_SDCR_DDREN_SHIFT)		| \
77 	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT)	| \
78 	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)	| \
79 	(4 << DV_DDR_SDCR_CL_SHIFT)		| \
80 	(3 << DV_DDR_SDCR_IBANK_SHIFT)		| \
81 	(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
82 
83 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
84 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
85 
86 #define CONFIG_SYS_DA850_DDR2_SDTIMR (		  \
87 	(19 << DV_DDR_SDTMR1_RFC_SHIFT)		| \
88 	(1 << DV_DDR_SDTMR1_RP_SHIFT)		| \
89 	(1 << DV_DDR_SDTMR1_RCD_SHIFT)		| \
90 	(2 << DV_DDR_SDTMR1_WR_SHIFT)		| \
91 	(6 << DV_DDR_SDTMR1_RAS_SHIFT)		| \
92 	(8 << DV_DDR_SDTMR1_RC_SHIFT)		| \
93 	(1 << DV_DDR_SDTMR1_RRD_SHIFT)		| \
94 	(1 << DV_DDR_SDTMR1_WTR_SHIFT))
95 
96 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		  \
97 	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT)	| \
98 	(2 << DV_DDR_SDTMR2_XP_SHIFT)		| \
99 	(0 << DV_DDR_SDTMR2_ODT_SHIFT)		| \
100 	(20 << DV_DDR_SDTMR2_XSNR_SHIFT)	| \
101 	(199 << DV_DDR_SDTMR2_XSRD_SHIFT)	| \
102 	(1 << DV_DDR_SDTMR2_RTP_SHIFT)		| \
103 	(2 << DV_DDR_SDTMR2_CKE_SHIFT))
104 
105 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000492
106 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
107 
108 /*
109  * Serial Driver info
110  */
111 #define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
112 #if !defined(CONFIG_DM_SERIAL)
113 #define CONFIG_SYS_NS16550_SERIAL
114 #define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
115 #define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
116 #define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
117 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
118 #endif
119 
120 #define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
121 #define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
122 #define CONFIG_SF_DEFAULT_SPEED		30000000
123 #define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
124 
125 #ifdef CONFIG_USE_SPIFLASH
126 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
127 #define CONFIG_SYS_SPI_U_BOOT_SIZE	0x30000
128 #endif
129 
130 /*
131  * I2C Configuration
132  */
133 #define CONFIG_SYS_DAVINCI_I2C_SPEED	25000
134 #define CONFIG_SYS_DAVINCI_I2C_SLAVE	10 /* Bogus, master-only in U-Boot */
135 #define CONFIG_SYS_I2C_EXPANDER_ADDR	0x20
136 
137 /*
138  * Flash & Environment
139  */
140 #ifdef CONFIG_NAND
141 #define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
142 #define CONFIG_ENV_SIZE			(128 << 9)
143 #define	CONFIG_SYS_NAND_USE_FLASH_BBT
144 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
145 #define	CONFIG_SYS_NAND_PAGE_2K
146 #define CONFIG_SYS_NAND_CS		3
147 #define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
148 #define CONFIG_SYS_NAND_MASK_CLE	0x10
149 #define CONFIG_SYS_NAND_MASK_ALE	0x8
150 #undef CONFIG_SYS_NAND_HW_ECC
151 #define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
152 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
153 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
154 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
155 #define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
156 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
157 #define CONFIG_SYS_NAND_U_BOOT_SIZE	SZ_512K
158 #define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
159 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
160 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
161 					CONFIG_SYS_NAND_U_BOOT_SIZE - \
162 					CONFIG_SYS_MALLOC_LEN -       \
163 					GENERATED_GBL_DATA_SIZE)
164 #define CONFIG_SYS_NAND_ECCPOS		{				\
165 				6, 7, 8, 9, 10, 11, 12, 13, 14, 15,	\
166 				22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
167 				38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
168 				54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
169 #define CONFIG_SYS_NAND_PAGE_COUNT	64
170 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
171 #define CONFIG_SYS_NAND_ECCSIZE		512
172 #define CONFIG_SYS_NAND_ECCBYTES	10
173 #define CONFIG_SYS_NAND_OOBSIZE		64
174 #define CONFIG_SPL_NAND_BASE
175 #define CONFIG_SPL_NAND_DRIVERS
176 #define CONFIG_SPL_NAND_ECC
177 #define CONFIG_SPL_NAND_LOAD
178 #endif
179 
180 #ifdef CONFIG_SYS_USE_NOR
181 #define CONFIG_FLASH_CFI_DRIVER
182 #define CONFIG_SYS_FLASH_CFI
183 #define CONFIG_SYS_FLASH_PROTECTION
184 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* max number of flash banks */
185 #define CONFIG_SYS_FLASH_SECT_SZ	(128 << 10) /* 128KB */
186 #define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ * 3)
187 #define CONFIG_ENV_SIZE			(128 << 10)
188 #define CONFIG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
189 #define PHYS_FLASH_SIZE			(8 << 20) /* Flash size 8MB */
190 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
191 	       + 3)
192 #define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_FLASH_SECT_SZ
193 #endif
194 
195 #ifdef CONFIG_USE_SPIFLASH
196 #define CONFIG_ENV_SIZE			(64 << 10)
197 #define CONFIG_ENV_OFFSET		(256 << 10)
198 #define CONFIG_ENV_SECT_SIZE		(64 << 10)
199 #endif
200 
201 /*
202  * Network & Ethernet Configuration
203  */
204 #ifdef CONFIG_DRIVER_TI_EMAC
205 #undef	CONFIG_DRIVER_TI_EMAC_USE_RMII
206 #define CONFIG_BOOTP_DEFAULT
207 #define CONFIG_BOOTP_DNS2
208 #define CONFIG_BOOTP_SEND_HOSTNAME
209 #define CONFIG_NET_RETRY_COUNT	10
210 #endif
211 
212 /*
213  * U-Boot general configuration
214  */
215 #define CONFIG_BOOTFILE		"zImage" /* Boot file name */
216 #define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
217 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
218 #define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
219 #define CONFIG_MX_CYCLIC
220 
221 /*
222  * Linux Information
223  */
224 #define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
225 #define CONFIG_CMDLINE_TAG
226 #define CONFIG_REVISION_TAG
227 #define CONFIG_SETUP_MEMORY_TAGS
228 #define CONFIG_BOOTCOMMAND \
229 		"run envboot; " \
230 		"run mmcboot; "
231 
232 #define DEFAULT_LINUX_BOOT_ENV \
233 	"loadaddr=0xc0700000\0" \
234 	"fdtaddr=0xc0600000\0" \
235 	"scriptaddr=0xc0600000\0"
236 
237 #include <environment/ti/mmc.h>
238 
239 #define CONFIG_EXTRA_ENV_SETTINGS \
240 	DEFAULT_LINUX_BOOT_ENV \
241 	DEFAULT_MMC_TI_ARGS \
242 	"bootpart=0:2\0" \
243 	"bootdir=/boot\0" \
244 	"bootfile=zImage\0" \
245 	"fdtfile=da850-lcdk.dtb\0" \
246 	"boot_fdt=yes\0" \
247 	"boot_fit=0\0" \
248 	"console=ttyS2,115200n8\0"
249 
250 #ifdef CONFIG_CMD_BDI
251 #define CONFIG_CLOCKS
252 #endif
253 
254 #if !defined(CONFIG_NAND) && \
255 	!defined(CONFIG_SYS_USE_NOR) && \
256 	!defined(CONFIG_USE_SPIFLASH)
257 #define CONFIG_ENV_SIZE		(16 << 10)
258 #endif
259 
260 /* SD/MMC */
261 
262 #ifdef CONFIG_ENV_IS_IN_MMC
263 #undef CONFIG_ENV_SIZE
264 #undef CONFIG_ENV_OFFSET
265 #define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
266 #define CONFIG_ENV_OFFSET	(51 << 9)	/* Sector 51 */
267 #endif
268 
269 #ifndef CONFIG_DIRECT_NOR_BOOT
270 /* defines for SPL */
271 #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
272 						CONFIG_SYS_MALLOC_LEN)
273 #define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
274 #define CONFIG_SPL_STACK	0x8001ff00
275 #define CONFIG_SPL_TEXT_BASE	0x80000000
276 #define CONFIG_SPL_MAX_FOOTPRINT	32768
277 #define CONFIG_SPL_PAD_TO	32768
278 #endif
279 
280 /* additions for new relocation code, must added to all boards */
281 #define CONFIG_SYS_SDRAM_BASE		0xc0000000
282 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
283 					GENERATED_GBL_DATA_SIZE)
284 
285 #include <asm/arch/hardware.h>
286 
287 #endif /* __CONFIG_H */
288