1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on davinci_dvevm.h. Original Copyrights follow: 5 * 6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * Board 16 */ 17 #define CONFIG_DRIVER_TI_EMAC 18 #undef CONFIG_USE_SPIFLASH 19 #undef CONFIG_SYS_USE_NOR 20 #define CONFIG_USE_NAND 21 22 /* 23 * SoC Configuration 24 */ 25 #define CONFIG_MACH_OMAPL138_LCDK 26 #define CONFIG_ARM926EJS /* arm926ejs CPU core */ 27 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 28 #define CONFIG_SYS_OSCIN_FREQ 24000000 29 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 30 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 31 #define CONFIG_SYS_HZ 1000 32 #define CONFIG_SKIP_LOWLEVEL_INIT 33 #define CONFIG_SYS_TEXT_BASE 0xc1080000 34 35 /* 36 * Memory Info 37 */ 38 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 39 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 40 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ 41 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 42 43 /* memtest start addr */ 44 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 45 46 /* memtest will be run on 16MB */ 47 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 48 49 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 50 51 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 52 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 53 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 54 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 55 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 56 DAVINCI_SYSCFG_SUSPSRC_I2C) 57 58 /* 59 * PLL configuration 60 */ 61 62 #define CONFIG_SYS_DA850_PLL0_PLLM 37 63 #define CONFIG_SYS_DA850_PLL1_PLLM 21 64 65 /* 66 * DDR2 memory configuration 67 */ 68 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 69 DV_DDR_PHY_EXT_STRBEN | \ 70 (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 71 72 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 73 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ 74 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 75 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 76 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 77 (4 << DV_DDR_SDCR_CL_SHIFT) | \ 78 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ 79 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 80 81 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 82 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 83 84 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 85 (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 86 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ 87 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 88 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ 89 (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 90 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 91 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 92 (1 << DV_DDR_SDTMR1_WTR_SHIFT)) 93 94 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 95 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 96 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ 97 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 98 (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 99 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 100 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 101 (2 << DV_DDR_SDTMR2_CKE_SHIFT)) 102 103 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492 104 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 105 106 /* 107 * Serial Driver info 108 */ 109 #define CONFIG_SYS_NS16550_SERIAL 110 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 111 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 112 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 113 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 114 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 115 116 #define CONFIG_SPI 117 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE 118 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) 119 #define CONFIG_SF_DEFAULT_SPEED 30000000 120 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 121 122 #ifdef CONFIG_USE_SPIFLASH 123 #define CONFIG_SPL_SPI_LOAD 124 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 125 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 126 #endif 127 128 /* 129 * I2C Configuration 130 */ 131 #define CONFIG_SYS_I2C 132 #define CONFIG_SYS_I2C_DAVINCI 133 #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 134 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ 135 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 136 137 /* 138 * Flash & Environment 139 */ 140 #ifdef CONFIG_USE_NAND 141 #define CONFIG_NAND_DAVINCI 142 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 143 #define CONFIG_ENV_SIZE (128 << 9) 144 #define CONFIG_SYS_NAND_USE_FLASH_BBT 145 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 146 #define CONFIG_SYS_NAND_PAGE_2K 147 #define CONFIG_SYS_NAND_CS 3 148 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 149 #define CONFIG_SYS_NAND_MASK_CLE 0x10 150 #define CONFIG_SYS_NAND_MASK_ALE 0x8 151 #undef CONFIG_SYS_NAND_HW_ECC 152 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 153 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 154 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC 155 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 156 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) 157 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 158 #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K 159 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 160 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 161 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 162 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 163 CONFIG_SYS_MALLOC_LEN - \ 164 GENERATED_GBL_DATA_SIZE) 165 #define CONFIG_SYS_NAND_ECCPOS { \ 166 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 167 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 168 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 169 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 } 170 #define CONFIG_SYS_NAND_PAGE_COUNT 64 171 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 172 #define CONFIG_SYS_NAND_ECCSIZE 512 173 #define CONFIG_SYS_NAND_ECCBYTES 10 174 #define CONFIG_SYS_NAND_OOBSIZE 64 175 #define CONFIG_SPL_NAND_BASE 176 #define CONFIG_SPL_NAND_DRIVERS 177 #define CONFIG_SPL_NAND_ECC 178 #define CONFIG_SPL_NAND_LOAD 179 #endif 180 181 #ifdef CONFIG_SYS_USE_NOR 182 #define CONFIG_FLASH_CFI_DRIVER 183 #define CONFIG_SYS_FLASH_CFI 184 #define CONFIG_SYS_FLASH_PROTECTION 185 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 186 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 187 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) 188 #define CONFIG_ENV_SIZE (128 << 10) 189 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 190 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ 191 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ 192 + 3) 193 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 194 #endif 195 196 #ifdef CONFIG_USE_SPIFLASH 197 #define CONFIG_ENV_SIZE (64 << 10) 198 #define CONFIG_ENV_OFFSET (256 << 10) 199 #define CONFIG_ENV_SECT_SIZE (64 << 10) 200 #endif 201 202 /* 203 * Network & Ethernet Configuration 204 */ 205 #ifdef CONFIG_DRIVER_TI_EMAC 206 #define CONFIG_MII 207 #undef CONFIG_DRIVER_TI_EMAC_USE_RMII 208 #define CONFIG_BOOTP_DEFAULT 209 #define CONFIG_BOOTP_DNS 210 #define CONFIG_BOOTP_DNS2 211 #define CONFIG_BOOTP_SEND_HOSTNAME 212 #define CONFIG_NET_RETRY_COUNT 10 213 #endif 214 215 /* 216 * U-Boot general configuration 217 */ 218 #define CONFIG_MISC_INIT_R 219 #define CONFIG_BOOTFILE "zImage" /* Boot file name */ 220 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 221 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 222 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 223 #define CONFIG_AUTO_COMPLETE 224 #define CONFIG_CMDLINE_EDITING 225 #define CONFIG_SYS_LONGHELP 226 #define CONFIG_MX_CYCLIC 227 228 /* 229 * Linux Information 230 */ 231 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 232 #define CONFIG_CMDLINE_TAG 233 #define CONFIG_REVISION_TAG 234 #define CONFIG_SETUP_MEMORY_TAGS 235 #define CONFIG_BOOTCOMMAND \ 236 "run envboot; " \ 237 "run mmcboot; " 238 239 #define DEFAULT_LINUX_BOOT_ENV \ 240 "loadaddr=0xc0700000\0" \ 241 "fdtaddr=0xc0600000\0" \ 242 "scriptaddr=0xc0600000\0" 243 244 #include <environment/ti/mmc.h> 245 246 #define CONFIG_EXTRA_ENV_SETTINGS \ 247 DEFAULT_LINUX_BOOT_ENV \ 248 DEFAULT_MMC_TI_ARGS \ 249 "bootpart=0:2\0" \ 250 "bootdir=/boot\0" \ 251 "bootfile=zImage\0" \ 252 "fdtfile=da850-lcdk.dtb\0" \ 253 "boot_fdt=yes\0" \ 254 "boot_fit=0\0" \ 255 "console=ttyS2,115200n8\0" 256 257 #ifdef CONFIG_CMD_BDI 258 #define CONFIG_CLOCKS 259 #endif 260 261 #ifndef CONFIG_DRIVER_TI_EMAC 262 #endif 263 264 #ifdef CONFIG_USE_NAND 265 #define CONFIG_MTD_DEVICE 266 #define CONFIG_MTD_PARTITIONS 267 #endif 268 269 #if !defined(CONFIG_USE_NAND) && \ 270 !defined(CONFIG_SYS_USE_NOR) && \ 271 !defined(CONFIG_USE_SPIFLASH) 272 #define CONFIG_ENV_SIZE (16 << 10) 273 #endif 274 275 /* SD/MMC */ 276 277 #ifdef CONFIG_ENV_IS_IN_MMC 278 #undef CONFIG_ENV_SIZE 279 #undef CONFIG_ENV_OFFSET 280 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 281 #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ 282 #endif 283 284 #ifndef CONFIG_DIRECT_NOR_BOOT 285 /* defines for SPL */ 286 #define CONFIG_SPL_FRAMEWORK 287 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 288 CONFIG_SYS_MALLOC_LEN) 289 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 290 #define CONFIG_SPL_STACK 0x8001ff00 291 #define CONFIG_SPL_TEXT_BASE 0x80000000 292 #define CONFIG_SPL_MAX_FOOTPRINT 32768 293 #define CONFIG_SPL_PAD_TO 32768 294 #endif 295 296 /* additions for new relocation code, must added to all boards */ 297 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 298 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 299 GENERATED_GBL_DATA_SIZE) 300 301 #include <asm/arch/hardware.h> 302 303 #endif /* __CONFIG_H */ 304