1 /*
2  * (C) Copyright 2006-2008
3  * Texas Instruments.
4  * Richard Woodruff <r-woodruff2@ti.com>
5  * Syed Mohammed Khasim <x0khasim@ti.com>
6  * Nishanth Menon <nm@ti.com>
7  *
8  * Configuration settings for the TI OMAP3430 Zoom MDK board.
9  *
10  * See file CREDITS for list of people who contributed to this
11  * project.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License as
15  * published by the Free Software Foundation; either version 2 of
16  * the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software
25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26  * MA 02111-1307 USA
27  */
28 
29 #ifndef __CONFIG_H
30 #define __CONFIG_H
31 
32 /*
33  * High Level Configuration Options
34  */
35 #define CONFIG_OMAP		1	/* in a TI OMAP core */
36 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
37 #define CONFIG_OMAP3_ZOOM1	1	/* working with Zoom MDK Rev1 */
38 
39 #define CONFIG_SDRC	/* The chip has SDRC controller */
40 
41 #include <asm/arch/cpu.h>		/* get chip and board defs */
42 #include <asm/arch/omap3.h>
43 
44 /*
45  * Display CPU and Board information
46  */
47 #define CONFIG_DISPLAY_CPUINFO		1
48 #define CONFIG_DISPLAY_BOARDINFO	1
49 
50 /* Clock Defines */
51 #define V_OSCK			26000000	/* Clock output from T2 */
52 #define V_SCLK			(V_OSCK >> 1)
53 
54 #undef CONFIG_USE_IRQ				/* no support for IRQs */
55 #define CONFIG_MISC_INIT_R
56 
57 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
58 #define CONFIG_SETUP_MEMORY_TAGS	1
59 #define CONFIG_INITRD_TAG		1
60 #define CONFIG_REVISION_TAG		1
61 
62 #define CONFIG_OF_LIBFDT		1
63 
64 /*
65  * Size of malloc() pool
66  */
67 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
68 						/* Sector */
69 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
70 
71 /*
72  * Hardware drivers
73  */
74 
75 /*
76  * NS16550 Configuration
77  */
78 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
79 
80 #define CONFIG_SYS_NS16550
81 #define CONFIG_SYS_NS16550_SERIAL
82 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
83 #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
84 
85 /*
86  * select serial console configuration
87  */
88 #define CONFIG_CONS_INDEX		3
89 #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
90 #define CONFIG_SERIAL3			3	/* UART3 */
91 
92 /* allow to overwrite serial and ethaddr */
93 #define CONFIG_ENV_OVERWRITE
94 #define CONFIG_BAUDRATE			115200
95 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
96 					115200}
97 #define CONFIG_GENERIC_MMC		1
98 #define CONFIG_MMC			1
99 #define CONFIG_OMAP_HSMMC		1
100 #define CONFIG_DOS_PARTITION		1
101 
102 /* USB */
103 #define CONFIG_MUSB_UDC			1
104 #define CONFIG_USB_OMAP3		1
105 #define CONFIG_TWL4030_USB		1
106 
107 /* USB device configuration */
108 #define CONFIG_USB_DEVICE		1
109 #define CONFIG_USB_TTY			1
110 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
111 /* Change these to suit your needs */
112 #define CONFIG_USBD_VENDORID		0x0451
113 #define CONFIG_USBD_PRODUCTID		0x5678
114 #define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
115 #define CONFIG_USBD_PRODUCT_NAME	"Zoom1"
116 
117 /* commands to include */
118 #include <config_cmd_default.h>
119 
120 #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
121 #define CONFIG_CMD_FAT		/* FAT support			*/
122 #define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
123 
124 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
125 #define CONFIG_CMD_MMC		/* MMC support			*/
126 #define CONFIG_CMD_NAND		/* NAND support			*/
127 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
128 
129 #undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
130 #undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
131 #undef CONFIG_CMD_IMI		/* iminfo			*/
132 #undef CONFIG_CMD_IMLS		/* List all found images	*/
133 #undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
134 #undef CONFIG_CMD_NFS		/* NFS support			*/
135 
136 #define CONFIG_SYS_NO_FLASH
137 #define CONFIG_HARD_I2C			1
138 #define CONFIG_SYS_I2C_SPEED		100000
139 #define CONFIG_SYS_I2C_SLAVE		1
140 #define CONFIG_SYS_I2C_BUS		0
141 #define CONFIG_SYS_I2C_BUS_SELECT	1
142 #define CONFIG_DRIVER_OMAP34XX_I2C	1
143 
144 /*
145  * TWL4030
146  */
147 #define CONFIG_TWL4030_POWER		1
148 #define CONFIG_TWL4030_LED		1
149 
150 /*
151  * Board NAND Info.
152  */
153 #define CONFIG_NAND_OMAP_GPMC
154 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
155 							/* to access nand */
156 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
157 							/* to access nand at */
158 							/* CS0 */
159 #define GPMC_NAND_ECC_LP_x16_LAYOUT	1
160 
161 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
162 							/* devices */
163 #define CONFIG_JFFS2_NAND
164 /* nand device jffs2 lives on */
165 #define CONFIG_JFFS2_DEV		"nand0"
166 /* start of jffs2 partition */
167 #define CONFIG_JFFS2_PART_OFFSET	0x680000
168 #define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
169 							/* partition */
170 
171 /* Environment information */
172 #define CONFIG_BOOTDELAY		10
173 
174 #define CONFIG_EXTRA_ENV_SETTINGS \
175 	"loadaddr=0x82000000\0" \
176 	"usbtty=cdc_acm\0" \
177 	"console=ttyS2,115200n8\0" \
178 	"mmcdev=0\0" \
179 	"videomode=1024x768@60,vxres=1024,vyres=768\0" \
180 	"videospec=omapfb:vram:2M,vram:4M\0" \
181 	"mmcargs=setenv bootargs console=${console} " \
182 		"video=${videospec},mode:${videomode} " \
183 		"root=/dev/mmcblk0p2 rw " \
184 		"rootfstype=ext3 rootwait\0" \
185 	"nandargs=setenv bootargs console=${console} " \
186 		"video=${videospec},mode:${videomode} " \
187 		"root=/dev/mtdblock4 rw " \
188 		"rootfstype=jffs2\0" \
189 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
190 	"bootscript=echo Running bootscript from mmc ...; " \
191 		"source ${loadaddr}\0" \
192 	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
193 	"mmcboot=echo Booting from mmc ...; " \
194 		"run mmcargs; " \
195 		"bootm ${loadaddr}\0" \
196 	"nandboot=echo Booting from nand ...; " \
197 		"run nandargs; " \
198 		"nand read ${loadaddr} 280000 400000; " \
199 		"bootm ${loadaddr}\0" \
200 
201 #define CONFIG_BOOTCOMMAND \
202 	"if mmc rescan ${mmcdev}; then " \
203 		"if run loadbootscript; then " \
204 			"run bootscript; " \
205 		"else " \
206 			"if run loaduimage; then " \
207 				"run mmcboot; " \
208 			"else run nandboot; " \
209 			"fi; " \
210 		"fi; " \
211 	"else run nandboot; fi"
212 
213 #define CONFIG_AUTO_COMPLETE		1
214 /*
215  * Miscellaneous configurable options
216  */
217 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
218 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
219 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
220 #define CONFIG_SYS_PROMPT		"OMAP3 Zoom1 # "
221 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
222 /* Print Buffer Size */
223 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
224 					sizeof(CONFIG_SYS_PROMPT) + 16)
225 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
226 /* Boot Argument Buffer Size */
227 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
228 
229 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
230 								/* works on */
231 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
232 					0x01F00000) /* 31MB */
233 
234 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
235 							/* load address */
236 
237 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
238 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
239 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
240 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
241 					 CONFIG_SYS_INIT_RAM_SIZE - \
242 					 GENERATED_GBL_DATA_SIZE)
243 /*
244  * OMAP3 has 12 GP timers, they can be driven by the system clock
245  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
246  * This rate is divided by a local divisor.
247  */
248 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
249 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
250 #define CONFIG_SYS_HZ			1000
251 
252 /*-----------------------------------------------------------------------
253  * Stack sizes
254  *
255  * The stack sizes are set up in start.S using the settings below
256  */
257 #define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
258 
259 /*-----------------------------------------------------------------------
260  * Physical Memory Map
261  */
262 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
263 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
264 #define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
265 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
266 
267 /*-----------------------------------------------------------------------
268  * FLASH and environment organization
269  */
270 
271 /* **** PISMO SUPPORT *** */
272 
273 /* Configure the PISMO */
274 #define PISMO1_NAND_SIZE		GPMC_SIZE_128M
275 #define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
276 
277 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
278 
279 #if defined(CONFIG_CMD_NAND)
280 #define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
281 #endif
282 
283 /* Monitor at start of flash */
284 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
285 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
286 
287 #define CONFIG_ENV_IS_IN_NAND		1
288 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
289 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
290 
291 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
292 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
293 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
294 
295 #define CONFIG_SYS_CACHELINE_SIZE	64
296 
297 #endif				/* __CONFIG_H */
298