1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * Nishanth Menon <nm@ti.com> 7 * 8 * Configuration settings for the TI OMAP3430 Zoom MDK board. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* 33 * High Level Configuration Options 34 */ 35 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ 36 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 37 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 38 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 39 #define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */ 40 41 #include <asm/arch/cpu.h> /* get chip and board defs */ 42 #include <asm/arch/omap3.h> 43 44 /* 45 * Display CPU and Board information 46 */ 47 #define CONFIG_DISPLAY_CPUINFO 1 48 #define CONFIG_DISPLAY_BOARDINFO 1 49 50 /* Clock Defines */ 51 #define V_OSCK 26000000 /* Clock output from T2 */ 52 #define V_SCLK (V_OSCK >> 1) 53 54 #undef CONFIG_USE_IRQ /* no support for IRQs */ 55 #define CONFIG_MISC_INIT_R 56 57 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 58 #define CONFIG_SETUP_MEMORY_TAGS 1 59 #define CONFIG_INITRD_TAG 1 60 #define CONFIG_REVISION_TAG 1 61 62 /* 63 * Size of malloc() pool 64 */ 65 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 66 /* Sector */ 67 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 68 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ 69 /* initial data */ 70 71 /* 72 * Hardware drivers 73 */ 74 75 /* 76 * NS16550 Configuration 77 */ 78 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 79 80 #define CONFIG_SYS_NS16550 81 #define CONFIG_SYS_NS16550_SERIAL 82 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 83 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 84 85 /* 86 * select serial console configuration 87 */ 88 #define CONFIG_CONS_INDEX 3 89 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 90 #define CONFIG_SERIAL3 3 /* UART3 */ 91 92 /* allow to overwrite serial and ethaddr */ 93 #define CONFIG_ENV_OVERWRITE 94 #define CONFIG_BAUDRATE 115200 95 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 96 115200} 97 #define CONFIG_MMC 1 98 #define CONFIG_OMAP3_MMC 1 99 #define CONFIG_DOS_PARTITION 1 100 101 /* DDR - I use Micron DDR */ 102 #define CONFIG_OMAP3_MICRON_DDR 1 103 104 /* commands to include */ 105 #include <config_cmd_default.h> 106 107 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 108 #define CONFIG_CMD_FAT /* FAT support */ 109 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 110 111 #define CONFIG_CMD_I2C /* I2C serial bus support */ 112 #define CONFIG_CMD_MMC /* MMC support */ 113 #define CONFIG_CMD_NAND /* NAND support */ 114 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */ 115 116 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 117 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 118 #undef CONFIG_CMD_IMI /* iminfo */ 119 #undef CONFIG_CMD_IMLS /* List all found images */ 120 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 121 #undef CONFIG_CMD_NFS /* NFS support */ 122 123 #define CONFIG_SYS_NO_FLASH 124 #define CONFIG_HARD_I2C 1 125 #define CONFIG_SYS_I2C_SPEED 100000 126 #define CONFIG_SYS_I2C_SLAVE 1 127 #define CONFIG_SYS_I2C_BUS 0 128 #define CONFIG_SYS_I2C_BUS_SELECT 1 129 #define CONFIG_DRIVER_OMAP34XX_I2C 1 130 131 /* 132 * TWL4030 133 */ 134 #define CONFIG_TWL4030_POWER 1 135 #define CONFIG_TWL4030_LED 1 136 137 /* 138 * Board NAND Info. 139 */ 140 #define CONFIG_NAND_OMAP_GPMC 141 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 142 /* to access nand */ 143 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 144 /* to access nand at */ 145 /* CS0 */ 146 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 147 148 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 149 /* devices */ 150 151 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ 152 153 #define CONFIG_JFFS2_NAND 154 /* nand device jffs2 lives on */ 155 #define CONFIG_JFFS2_DEV "nand0" 156 /* start of jffs2 partition */ 157 #define CONFIG_JFFS2_PART_OFFSET 0x680000 158 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 159 /* partition */ 160 161 /* Environment information */ 162 #define CONFIG_BOOTDELAY 10 163 164 #define CONFIG_EXTRA_ENV_SETTINGS \ 165 "loadaddr=0x82000000\0" \ 166 "console=ttyS2,115200n8\0" \ 167 "videomode=1024x768@60,vxres=1024,vyres=768\0" \ 168 "videospec=omapfb:vram:2M,vram:4M\0" \ 169 "mmcargs=setenv bootargs console=${console} " \ 170 "video=${videospec},mode:${videomode} " \ 171 "root=/dev/mmcblk0p2 rw " \ 172 "rootfstype=ext3 rootwait\0" \ 173 "nandargs=setenv bootargs console=${console} " \ 174 "video=${videospec},mode:${videomode} " \ 175 "root=/dev/mtdblock4 rw " \ 176 "rootfstype=jffs2\0" \ 177 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 178 "bootscript=echo Running bootscript from mmc ...; " \ 179 "source ${loadaddr}\0" \ 180 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 181 "mmcboot=echo Booting from mmc ...; " \ 182 "run mmcargs; " \ 183 "bootm ${loadaddr}\0" \ 184 "nandboot=echo Booting from nand ...; " \ 185 "run nandargs; " \ 186 "nand read ${loadaddr} 280000 400000; " \ 187 "bootm ${loadaddr}\0" \ 188 189 #define CONFIG_BOOTCOMMAND \ 190 "if mmc init; then " \ 191 "if run loadbootscript; then " \ 192 "run bootscript; " \ 193 "else " \ 194 "if run loaduimage; then " \ 195 "run mmcboot; " \ 196 "else run nandboot; " \ 197 "fi; " \ 198 "fi; " \ 199 "else run nandboot; fi" 200 201 #define CONFIG_AUTO_COMPLETE 1 202 /* 203 * Miscellaneous configurable options 204 */ 205 #define V_PROMPT "OMAP3 Zoom1# " 206 207 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 208 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 209 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 210 #define CONFIG_SYS_PROMPT V_PROMPT 211 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 212 /* Print Buffer Size */ 213 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 214 sizeof(CONFIG_SYS_PROMPT) + 16) 215 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 216 /* Boot Argument Buffer Size */ 217 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 218 219 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 220 /* works on */ 221 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 222 0x01F00000) /* 31MB */ 223 224 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 225 /* load address */ 226 227 /* 228 * OMAP3 has 12 GP timers, they can be driven by the system clock 229 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 230 * This rate is divided by a local divisor. 231 */ 232 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 233 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 234 #define CONFIG_SYS_HZ 1000 235 236 /*----------------------------------------------------------------------- 237 * Stack sizes 238 * 239 * The stack sizes are set up in start.S using the settings below 240 */ 241 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 242 #ifdef CONFIG_USE_IRQ 243 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ 244 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ 245 #endif 246 247 /*----------------------------------------------------------------------- 248 * Physical Memory Map 249 */ 250 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 251 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 252 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 253 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 254 255 /* SDRAM Bank Allocation method */ 256 #define SDRC_R_B_C 1 257 258 /*----------------------------------------------------------------------- 259 * FLASH and environment organization 260 */ 261 262 /* **** PISMO SUPPORT *** */ 263 264 /* Configure the PISMO */ 265 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 266 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 267 268 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ 269 /* one chip */ 270 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 271 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 272 273 #define CONFIG_SYS_FLASH_BASE boot_flash_base 274 275 /* Monitor at start of flash */ 276 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 277 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 278 279 #define CONFIG_ENV_IS_IN_NAND 1 280 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 281 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 282 283 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 284 #define CONFIG_ENV_OFFSET boot_flash_off 285 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 286 287 /*----------------------------------------------------------------------- 288 * CFI FLASH driver setup 289 */ 290 /* timeout values are in ticks */ 291 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 292 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 293 294 /* Flash banks JFFS2 should use */ 295 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 296 CONFIG_SYS_MAX_NAND_DEVICE) 297 #define CONFIG_SYS_JFFS2_MEM_NAND 298 /* use flash_info[2] */ 299 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 300 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 301 302 #ifndef __ASSEMBLY__ 303 extern struct gpmc *gpmc_cfg; 304 extern unsigned int boot_flash_base; 305 extern volatile unsigned int boot_flash_env_addr; 306 extern unsigned int boot_flash_off; 307 extern unsigned int boot_flash_sec; 308 extern unsigned int boot_flash_type; 309 #endif 310 311 #endif /* __CONFIG_H */ 312