1 /* 2 * (C) Copyright 2008-2010 3 * Gražvydas Ignotas <notasas@gmail.com> 4 * 5 * Configuration settings for the OMAP3 Pandora. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 17 #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ 18 #define CONFIG_OMAP_GPIO 19 #define CONFIG_OMAP_COMMON 20 21 #define CONFIG_SDRC /* The chip has SDRC controller */ 22 23 #include <asm/arch/cpu.h> /* get chip and board defs */ 24 #include <asm/arch/omap3.h> 25 26 /* 27 * Display CPU and Board information 28 */ 29 #define CONFIG_DISPLAY_CPUINFO 1 30 #define CONFIG_DISPLAY_BOARDINFO 1 31 32 /* Clock Defines */ 33 #define V_OSCK 26000000 /* Clock output from T2 */ 34 #define V_SCLK (V_OSCK >> 1) 35 36 #define CONFIG_MISC_INIT_R 37 38 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 39 #define CONFIG_SETUP_MEMORY_TAGS 1 40 #define CONFIG_INITRD_TAG 1 41 #define CONFIG_REVISION_TAG 1 42 43 #define CONFIG_OF_LIBFDT 1 44 45 /* 46 * Size of malloc() pool 47 */ 48 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 49 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE) 50 51 /* 52 * Hardware drivers 53 */ 54 55 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 56 #define CONFIG_SYS_DEVICE_NULLDEV 1 57 58 /* USB */ 59 #define CONFIG_MUSB_UDC 1 60 #define CONFIG_USB_OMAP3 1 61 #define CONFIG_TWL4030_USB 1 62 63 /* USB device configuration */ 64 #define CONFIG_USB_DEVICE 1 65 #define CONFIG_USB_TTY 1 66 67 /* 68 * NS16550 Configuration 69 */ 70 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 71 72 #define CONFIG_SYS_NS16550 73 #define CONFIG_SYS_NS16550_SERIAL 74 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 75 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 76 77 /* 78 * select serial console configuration 79 */ 80 #define CONFIG_CONS_INDEX 3 81 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 82 #define CONFIG_SERIAL3 3 83 84 /* allow to overwrite serial and ethaddr */ 85 #define CONFIG_ENV_OVERWRITE 86 #define CONFIG_BAUDRATE 115200 87 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 88 115200} 89 #define CONFIG_GENERIC_MMC 1 90 #define CONFIG_MMC 1 91 #define CONFIG_OMAP_HSMMC 1 92 #define CONFIG_DOS_PARTITION 1 93 94 /* commands to include */ 95 #include <config_cmd_default.h> 96 97 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 98 #define CONFIG_CMD_FAT /* FAT support */ 99 100 #define CONFIG_CMD_I2C /* I2C serial bus support */ 101 #define CONFIG_CMD_MMC /* MMC support */ 102 #define CONFIG_CMD_NAND /* NAND support */ 103 #define CONFIG_CMD_CACHE /* Cache control */ 104 105 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 106 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 107 #undef CONFIG_CMD_IMI /* iminfo */ 108 #undef CONFIG_CMD_IMLS /* List all found images */ 109 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 110 #undef CONFIG_CMD_NFS /* NFS support */ 111 112 #define CONFIG_SYS_NO_FLASH 113 #define CONFIG_SYS_I2C 114 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 115 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 116 #define CONFIG_SYS_I2C_OMAP34XX 117 118 /* 119 * TWL4030 120 */ 121 #define CONFIG_TWL4030_POWER 1 122 #define CONFIG_TWL4030_LED 1 123 124 /* 125 * Board NAND Info. 126 */ 127 #define CONFIG_NAND_OMAP_GPMC 128 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 129 /* to access nand */ 130 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 131 /* to access nand */ 132 /* at CS0 */ 133 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 134 /* devices */ 135 136 #ifdef CONFIG_CMD_NAND 137 #define CONFIG_CMD_MTDPARTS 138 #define CONFIG_MTD_PARTITIONS 139 #define CONFIG_MTD_DEVICE 140 #define CONFIG_CMD_UBI 141 #define CONFIG_CMD_UBIFS 142 #define CONFIG_RBTREE 143 #define CONFIG_LZO 144 145 #define MTDIDS_DEFAULT "nand0=nand" 146 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(xloader),"\ 147 "1920k(uboot),128k(uboot-env),"\ 148 "10m(boot),-(rootfs)" 149 #else 150 #define MTDPARTS_DEFAULT 151 #endif 152 153 /* Environment information */ 154 #define CONFIG_BOOTDELAY 1 155 156 #define CONFIG_EXTRA_ENV_SETTINGS \ 157 "usbtty=cdc_acm\0" \ 158 "loadaddr=0x82000000\0" \ 159 "bootargs=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \ 160 "rw rootflags=bulk_read vram=6272K omapfb.vram=0:3000K\0" \ 161 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 162 163 #define CONFIG_BOOTCOMMAND \ 164 "if mmc rescan && fatload mmc1 0 ${loadaddr} autoboot.scr || " \ 165 "ext2load mmc1 0 ${loadaddr} autoboot.scr; then " \ 166 "source ${loadaddr}; " \ 167 "fi; " \ 168 "ubi part boot && ubifsmount ubi:boot && " \ 169 "ubifsload ${loadaddr} uImage && bootm ${loadaddr}" 170 171 #define CONFIG_AUTO_COMPLETE 1 172 /* 173 * Miscellaneous configurable options 174 */ 175 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 176 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 177 #define CONFIG_SYS_PROMPT "Pandora # " 178 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 179 /* Print Buffer Size */ 180 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 181 sizeof(CONFIG_SYS_PROMPT) + 16) 182 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 183 /* args */ 184 /* Boot Argument Buffer Size */ 185 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 186 /* memtest works on */ 187 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 188 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 189 0x01F00000) /* 31MB */ 190 191 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 192 /* address */ 193 194 /* 195 * OMAP3 has 12 GP timers, they can be driven by the system clock 196 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 197 * This rate is divided by a local divisor. 198 */ 199 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 200 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 201 202 /*----------------------------------------------------------------------- 203 * Physical Memory Map 204 */ 205 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 206 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 207 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 208 209 #define CONFIG_SYS_TEXT_BASE 0x80008000 210 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 211 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 212 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 213 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 214 CONFIG_SYS_INIT_RAM_SIZE - \ 215 GENERATED_GBL_DATA_SIZE) 216 217 /*----------------------------------------------------------------------- 218 * FLASH and environment organization 219 */ 220 221 /* **** PISMO SUPPORT *** */ 222 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 223 224 #if defined(CONFIG_CMD_NAND) 225 #define CONFIG_SYS_FLASH_BASE NAND_BASE 226 #endif 227 228 /* Monitor at start of flash */ 229 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 230 231 #define CONFIG_ENV_IS_IN_NAND 1 232 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 233 234 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 235 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 236 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 237 238 #define CONFIG_SYS_CACHELINE_SIZE 64 239 240 #endif /* __CONFIG_H */ 241