1 /* 2 * (C) Copyright 2008 3 * Grazvydas Ignotas <notasas@gmail.com> 4 * 5 * Configuration settings for the OMAP3 Pandora. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 #include <asm/sizes.h> 26 27 /* 28 * High Level Configuration Options 29 */ 30 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ 31 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 32 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 33 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 34 #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ 35 36 #include <asm/arch/cpu.h> /* get chip and board defs */ 37 #include <asm/arch/omap3.h> 38 39 /* 40 * Display CPU and Board information 41 */ 42 #define CONFIG_DISPLAY_CPUINFO 1 43 #define CONFIG_DISPLAY_BOARDINFO 1 44 45 /* Clock Defines */ 46 #define V_OSCK 26000000 /* Clock output from T2 */ 47 #define V_SCLK (V_OSCK >> 1) 48 49 #undef CONFIG_USE_IRQ /* no support for IRQs */ 50 #define CONFIG_MISC_INIT_R 51 52 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 53 #define CONFIG_SETUP_MEMORY_TAGS 1 54 #define CONFIG_INITRD_TAG 1 55 #define CONFIG_REVISION_TAG 1 56 57 /* 58 * Size of malloc() pool 59 */ 60 #define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ 61 /* Sector */ 62 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) 63 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ 64 /* initial data */ 65 66 /* 67 * Hardware drivers 68 */ 69 70 /* 71 * NS16550 Configuration 72 */ 73 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 74 75 #define CONFIG_SYS_NS16550 76 #define CONFIG_SYS_NS16550_SERIAL 77 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 78 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 79 80 /* 81 * select serial console configuration 82 */ 83 #define CONFIG_CONS_INDEX 3 84 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 85 #define CONFIG_SERIAL3 3 86 87 /* allow to overwrite serial and ethaddr */ 88 #define CONFIG_ENV_OVERWRITE 89 #define CONFIG_BAUDRATE 115200 90 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 91 115200} 92 #define CONFIG_MMC 1 93 #define CONFIG_OMAP3_MMC 1 94 #define CONFIG_DOS_PARTITION 1 95 96 /* commands to include */ 97 #include <config_cmd_default.h> 98 99 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 100 #define CONFIG_CMD_FAT /* FAT support */ 101 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 102 103 #define CONFIG_CMD_I2C /* I2C serial bus support */ 104 #define CONFIG_CMD_MMC /* MMC support */ 105 #define CONFIG_CMD_NAND /* NAND support */ 106 107 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 108 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 109 #undef CONFIG_CMD_IMI /* iminfo */ 110 #undef CONFIG_CMD_IMLS /* List all found images */ 111 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 112 #undef CONFIG_CMD_NFS /* NFS support */ 113 114 #define CONFIG_SYS_NO_FLASH 115 #define CONFIG_SYS_I2C_SPEED 100000 116 #define CONFIG_SYS_I2C_SLAVE 1 117 #define CONFIG_SYS_I2C_BUS 0 118 #define CONFIG_SYS_I2C_BUS_SELECT 1 119 #define CONFIG_DRIVER_OMAP34XX_I2C 1 120 121 /* 122 * Board NAND Info. 123 */ 124 #define CONFIG_NAND_OMAP_GPMC 125 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 126 /* to access nand */ 127 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 128 /* to access nand */ 129 /* at CS0 */ 130 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 131 132 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 133 /* devices */ 134 135 #define CONFIG_JFFS2_NAND 136 /* nand device jffs2 lives on */ 137 #define CONFIG_JFFS2_DEV "nand0" 138 /* start of jffs2 partition */ 139 #define CONFIG_JFFS2_PART_OFFSET 0x680000 140 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 141 /* partition */ 142 143 /* Environment information */ 144 #define CONFIG_BOOTDELAY 1 145 146 #define CONFIG_EXTRA_ENV_SETTINGS \ 147 "loadaddr=0x82000000\0" \ 148 "console=ttyS0,115200n8\0" \ 149 "videospec=omapfb:vram:2M,vram:4M\0" \ 150 "mmcargs=setenv bootargs console=${console} " \ 151 "video=${videospec} " \ 152 "root=/dev/mmcblk0p2 rw " \ 153 "rootfstype=ext3 rootwait\0" \ 154 "nandargs=setenv bootargs console=${console} " \ 155 "video=${videospec} " \ 156 "root=/dev/mtdblock4 rw " \ 157 "rootfstype=jffs2\0" \ 158 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 159 "bootscript=echo Running bootscript from mmc ...; " \ 160 "source ${loadaddr}\0" \ 161 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 162 "mmcboot=echo Booting from mmc ...; " \ 163 "run mmcargs; " \ 164 "bootm ${loadaddr}\0" \ 165 "nandboot=echo Booting from nand ...; " \ 166 "run nandargs; " \ 167 "nand read ${loadaddr} 280000 400000; " \ 168 "bootm ${loadaddr}\0" \ 169 170 #define CONFIG_BOOTCOMMAND \ 171 "if mmc init; then " \ 172 "if run loadbootscript; then " \ 173 "run bootscript; " \ 174 "else " \ 175 "if run loaduimage; then " \ 176 "run mmcboot; " \ 177 "else run nandboot; " \ 178 "fi; " \ 179 "fi; " \ 180 "else run nandboot; fi" 181 182 #define CONFIG_AUTO_COMPLETE 1 183 /* 184 * Miscellaneous configurable options 185 */ 186 #define V_PROMPT "Pandora # " 187 188 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 189 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 190 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 191 #define CONFIG_SYS_PROMPT V_PROMPT 192 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 193 /* Print Buffer Size */ 194 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 195 sizeof(CONFIG_SYS_PROMPT) + 16) 196 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 197 /* args */ 198 /* Boot Argument Buffer Size */ 199 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 200 /* memtest works on */ 201 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 202 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 203 0x01F00000) /* 31MB */ 204 205 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 206 /* address */ 207 208 /* 209 * OMAP3 has 12 GP timers, they can be driven by the system clock 210 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 211 * This rate is divided by a local divisor. 212 */ 213 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 214 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 215 #define CONFIG_SYS_HZ 1000 216 217 /*----------------------------------------------------------------------- 218 * Stack sizes 219 * 220 * The stack sizes are set up in start.S using the settings below 221 */ 222 #define CONFIG_STACKSIZE SZ_128K /* regular stack */ 223 #ifdef CONFIG_USE_IRQ 224 #define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ 225 #define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ 226 #endif 227 228 /*----------------------------------------------------------------------- 229 * Physical Memory Map 230 */ 231 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 232 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 233 #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ 234 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 235 236 /* SDRAM Bank Allocation method */ 237 #define SDRC_R_B_C 1 238 239 /*----------------------------------------------------------------------- 240 * FLASH and environment organization 241 */ 242 243 /* **** PISMO SUPPORT *** */ 244 245 /* Configure the PISMO */ 246 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 247 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 248 249 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ 250 /* one chip */ 251 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 252 #define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ 253 254 #define CONFIG_SYS_FLASH_BASE boot_flash_base 255 256 /* Monitor at start of flash */ 257 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 258 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 259 260 #define CONFIG_ENV_IS_IN_NAND 1 261 #define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ 262 #define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ 263 264 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 265 #define CONFIG_ENV_OFFSET boot_flash_off 266 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 267 268 /*----------------------------------------------------------------------- 269 * CFI FLASH driver setup 270 */ 271 /* timeout values are in ticks */ 272 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 273 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 274 275 /* Flash banks JFFS2 should use */ 276 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 277 CONFIG_SYS_MAX_NAND_DEVICE) 278 #define CONFIG_SYS_JFFS2_MEM_NAND 279 /* use flash_info[2] */ 280 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 281 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 282 283 #ifndef __ASSEMBLY__ 284 extern gpmc_csx_t *nand_cs_base; 285 extern gpmc_t *gpmc_cfg_base; 286 extern unsigned int boot_flash_base; 287 extern volatile unsigned int boot_flash_env_addr; 288 extern unsigned int boot_flash_off; 289 extern unsigned int boot_flash_sec; 290 extern unsigned int boot_flash_type; 291 #endif 292 293 #endif /* __CONFIG_H */ 294