1 /* 2 * (C) Copyright 2008 3 * Grazvydas Ignotas <notasas@gmail.com> 4 * 5 * Configuration settings for the OMAP3 Pandora. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * High Level Configuration Options 28 */ 29 #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ 30 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 31 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 32 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 33 #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ 34 35 #define CONFIG_SDRC /* The chip has SDRC controller */ 36 37 #include <asm/arch/cpu.h> /* get chip and board defs */ 38 #include <asm/arch/omap3.h> 39 40 /* 41 * Display CPU and Board information 42 */ 43 #define CONFIG_DISPLAY_CPUINFO 1 44 #define CONFIG_DISPLAY_BOARDINFO 1 45 46 /* Clock Defines */ 47 #define V_OSCK 26000000 /* Clock output from T2 */ 48 #define V_SCLK (V_OSCK >> 1) 49 50 #undef CONFIG_USE_IRQ /* no support for IRQs */ 51 #define CONFIG_MISC_INIT_R 52 53 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 54 #define CONFIG_SETUP_MEMORY_TAGS 1 55 #define CONFIG_INITRD_TAG 1 56 #define CONFIG_REVISION_TAG 1 57 58 /* 59 * Size of malloc() pool 60 */ 61 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 62 /* Sector */ 63 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 64 /* initial data */ 65 66 /* 67 * Hardware drivers 68 */ 69 70 /* 71 * NS16550 Configuration 72 */ 73 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 74 75 #define CONFIG_SYS_NS16550 76 #define CONFIG_SYS_NS16550_SERIAL 77 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 78 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 79 80 /* 81 * select serial console configuration 82 */ 83 #define CONFIG_CONS_INDEX 3 84 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 85 #define CONFIG_SERIAL3 3 86 87 /* allow to overwrite serial and ethaddr */ 88 #define CONFIG_ENV_OVERWRITE 89 #define CONFIG_BAUDRATE 115200 90 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 91 115200} 92 #define CONFIG_MMC 1 93 #define CONFIG_OMAP3_MMC 1 94 #define CONFIG_DOS_PARTITION 1 95 96 /* DDR - I use Micron DDR */ 97 #define CONFIG_OMAP3_MICRON_DDR 1 98 99 /* commands to include */ 100 #include <config_cmd_default.h> 101 102 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 103 #define CONFIG_CMD_FAT /* FAT support */ 104 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 105 106 #define CONFIG_CMD_I2C /* I2C serial bus support */ 107 #define CONFIG_CMD_MMC /* MMC support */ 108 #define CONFIG_CMD_NAND /* NAND support */ 109 110 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 111 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 112 #undef CONFIG_CMD_IMI /* iminfo */ 113 #undef CONFIG_CMD_IMLS /* List all found images */ 114 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 115 #undef CONFIG_CMD_NFS /* NFS support */ 116 117 #define CONFIG_SYS_NO_FLASH 118 #define CONFIG_HARD_I2C 1 119 #define CONFIG_SYS_I2C_SPEED 100000 120 #define CONFIG_SYS_I2C_SLAVE 1 121 #define CONFIG_SYS_I2C_BUS 0 122 #define CONFIG_SYS_I2C_BUS_SELECT 1 123 #define CONFIG_DRIVER_OMAP34XX_I2C 1 124 125 /* 126 * TWL4030 127 */ 128 #define CONFIG_TWL4030_POWER 1 129 #define CONFIG_TWL4030_LED 1 130 131 /* 132 * Board NAND Info. 133 */ 134 #define CONFIG_NAND_OMAP_GPMC 135 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 136 /* to access nand */ 137 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 138 /* to access nand */ 139 /* at CS0 */ 140 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 141 142 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 143 /* devices */ 144 #define CONFIG_JFFS2_NAND 145 /* nand device jffs2 lives on */ 146 #define CONFIG_JFFS2_DEV "nand0" 147 /* start of jffs2 partition */ 148 #define CONFIG_JFFS2_PART_OFFSET 0x680000 149 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 150 /* partition */ 151 152 /* Environment information */ 153 #define CONFIG_BOOTDELAY 1 154 155 #define CONFIG_EXTRA_ENV_SETTINGS \ 156 "loadaddr=0x82000000\0" \ 157 "console=ttyS0,115200n8\0" \ 158 "videospec=omapfb:vram:2M,vram:4M\0" \ 159 "mmcargs=setenv bootargs console=${console} " \ 160 "video=${videospec} " \ 161 "root=/dev/mmcblk0p2 rw " \ 162 "rootfstype=ext3 rootwait\0" \ 163 "nandargs=setenv bootargs console=${console} " \ 164 "video=${videospec} " \ 165 "root=/dev/mtdblock4 rw " \ 166 "rootfstype=jffs2\0" \ 167 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 168 "bootscript=echo Running bootscript from mmc ...; " \ 169 "source ${loadaddr}\0" \ 170 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 171 "mmcboot=echo Booting from mmc ...; " \ 172 "run mmcargs; " \ 173 "bootm ${loadaddr}\0" \ 174 "nandboot=echo Booting from nand ...; " \ 175 "run nandargs; " \ 176 "nand read ${loadaddr} 280000 400000; " \ 177 "bootm ${loadaddr}\0" \ 178 179 #define CONFIG_BOOTCOMMAND \ 180 "if mmc init; then " \ 181 "if run loadbootscript; then " \ 182 "run bootscript; " \ 183 "else " \ 184 "if run loaduimage; then " \ 185 "run mmcboot; " \ 186 "else run nandboot; " \ 187 "fi; " \ 188 "fi; " \ 189 "else run nandboot; fi" 190 191 #define CONFIG_AUTO_COMPLETE 1 192 /* 193 * Miscellaneous configurable options 194 */ 195 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 196 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 197 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 198 #define CONFIG_SYS_PROMPT "Pandora # " 199 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 200 /* Print Buffer Size */ 201 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 202 sizeof(CONFIG_SYS_PROMPT) + 16) 203 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 204 /* args */ 205 /* Boot Argument Buffer Size */ 206 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 207 /* memtest works on */ 208 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 209 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 210 0x01F00000) /* 31MB */ 211 212 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 213 /* address */ 214 215 /* 216 * OMAP3 has 12 GP timers, they can be driven by the system clock 217 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 218 * This rate is divided by a local divisor. 219 */ 220 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 221 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 222 #define CONFIG_SYS_HZ 1000 223 224 /*----------------------------------------------------------------------- 225 * Stack sizes 226 * 227 * The stack sizes are set up in start.S using the settings below 228 */ 229 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 230 #ifdef CONFIG_USE_IRQ 231 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ 232 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ 233 #endif 234 235 /*----------------------------------------------------------------------- 236 * Physical Memory Map 237 */ 238 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 239 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 240 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 241 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 242 243 /* SDRAM Bank Allocation method */ 244 #define SDRC_R_B_C 1 245 246 /*----------------------------------------------------------------------- 247 * FLASH and environment organization 248 */ 249 250 /* **** PISMO SUPPORT *** */ 251 252 /* Configure the PISMO */ 253 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 254 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 255 256 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ 257 /* one chip */ 258 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 259 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 260 261 #define CONFIG_SYS_FLASH_BASE boot_flash_base 262 263 /* Monitor at start of flash */ 264 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 265 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 266 267 #define CONFIG_ENV_IS_IN_NAND 1 268 #define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ 269 #define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ 270 271 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 272 #define CONFIG_ENV_OFFSET boot_flash_off 273 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 274 275 /*----------------------------------------------------------------------- 276 * CFI FLASH driver setup 277 */ 278 /* timeout values are in ticks */ 279 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 280 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 281 282 /* Flash banks JFFS2 should use */ 283 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 284 CONFIG_SYS_MAX_NAND_DEVICE) 285 #define CONFIG_SYS_JFFS2_MEM_NAND 286 /* use flash_info[2] */ 287 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 288 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 289 290 #ifndef __ASSEMBLY__ 291 extern unsigned int boot_flash_base; 292 extern volatile unsigned int boot_flash_env_addr; 293 extern unsigned int boot_flash_off; 294 extern unsigned int boot_flash_sec; 295 extern unsigned int boot_flash_type; 296 #endif 297 298 #endif /* __CONFIG_H */ 299