1 /* 2 * Configuration settings for the Gumstix Overo board. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 23 /* 24 * High Level Configuration Options 25 */ 26 #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ 27 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 28 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 29 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 30 #define CONFIG_OMAP3_OVERO 1 /* working with overo */ 31 32 #define CONFIG_SDRC /* The chip has SDRC controller */ 33 34 #include <asm/arch/cpu.h> /* get chip and board defs */ 35 #include <asm/arch/omap3.h> 36 37 /* 38 * Display CPU and Board information 39 */ 40 #define CONFIG_DISPLAY_CPUINFO 1 41 #define CONFIG_DISPLAY_BOARDINFO 1 42 43 /* Clock Defines */ 44 #define V_OSCK 26000000 /* Clock output from T2 */ 45 #define V_SCLK (V_OSCK >> 1) 46 47 #undef CONFIG_USE_IRQ /* no support for IRQs */ 48 #define CONFIG_MISC_INIT_R 49 50 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 51 #define CONFIG_SETUP_MEMORY_TAGS 1 52 #define CONFIG_INITRD_TAG 1 53 #define CONFIG_REVISION_TAG 1 54 55 /* 56 * Size of malloc() pool 57 */ 58 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 59 /* Sector */ 60 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 61 /* initial data */ 62 63 /* 64 * Hardware drivers 65 */ 66 67 /* 68 * NS16550 Configuration 69 */ 70 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 71 72 #define CONFIG_SYS_NS16550 73 #define CONFIG_SYS_NS16550_SERIAL 74 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 75 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 76 77 /* 78 * select serial console configuration 79 */ 80 #define CONFIG_CONS_INDEX 3 81 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 82 #define CONFIG_SERIAL3 3 83 84 /* allow to overwrite serial and ethaddr */ 85 #define CONFIG_ENV_OVERWRITE 86 #define CONFIG_BAUDRATE 115200 87 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 88 115200} 89 #define CONFIG_GENERIC_MMC 1 90 #define CONFIG_MMC 1 91 #define CONFIG_OMAP_HSMMC 1 92 #define CONFIG_DOS_PARTITION 1 93 94 /* DDR - I use Micron DDR */ 95 #define CONFIG_OMAP3_MICRON_DDR 1 96 97 /* commands to include */ 98 #include <config_cmd_default.h> 99 100 #define CONFIG_CMD_CACHE 101 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 102 #define CONFIG_CMD_FAT /* FAT support */ 103 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 104 105 #define CONFIG_CMD_I2C /* I2C serial bus support */ 106 #define CONFIG_CMD_MMC /* MMC support */ 107 #define CONFIG_CMD_NAND /* NAND support */ 108 109 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 110 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 111 #undef CONFIG_CMD_IMI /* iminfo */ 112 #undef CONFIG_CMD_IMLS /* List all found images */ 113 #undef CONFIG_CMD_NFS /* NFS support */ 114 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 115 116 #define CONFIG_SYS_NO_FLASH 117 #define CONFIG_HARD_I2C 1 118 #define CONFIG_SYS_I2C_SPEED 100000 119 #define CONFIG_SYS_I2C_SLAVE 1 120 #define CONFIG_SYS_I2C_BUS 0 121 #define CONFIG_SYS_I2C_BUS_SELECT 1 122 #define CONFIG_I2C_MULTI_BUS 1 123 #define CONFIG_DRIVER_OMAP34XX_I2C 1 124 125 /* 126 * TWL4030 127 */ 128 #define CONFIG_TWL4030_POWER 1 129 #define CONFIG_TWL4030_LED 1 130 131 /* 132 * Board NAND Info. 133 */ 134 #define CONFIG_SYS_NAND_QUIET_TEST 1 135 #define CONFIG_NAND_OMAP_GPMC 136 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 137 /* to access nand */ 138 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 139 /* to access nand */ 140 /* at CS0 */ 141 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 142 143 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 144 /* devices */ 145 #define CONFIG_JFFS2_NAND 146 /* nand device jffs2 lives on */ 147 #define CONFIG_JFFS2_DEV "nand0" 148 /* start of jffs2 partition */ 149 #define CONFIG_JFFS2_PART_OFFSET 0x680000 150 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 151 /* partition */ 152 153 /* Environment information */ 154 #define CONFIG_BOOTDELAY 5 155 156 #define CONFIG_EXTRA_ENV_SETTINGS \ 157 "loadaddr=0x82000000\0" \ 158 "console=ttyS2,115200n8\0" \ 159 "mpurate=500\0" \ 160 "vram=12M\0" \ 161 "dvimode=1024x768MR-16@60\0" \ 162 "defaultdisplay=dvi\0" \ 163 "mmcdev=0\0" \ 164 "mmcroot=/dev/mmcblk0p2 rw\0" \ 165 "mmcrootfstype=ext3 rootwait\0" \ 166 "nandroot=/dev/mtdblock4 rw\0" \ 167 "nandrootfstype=jffs2\0" \ 168 "mmcargs=setenv bootargs console=${console} " \ 169 "mpurate=${mpurate} " \ 170 "vram=${vram} " \ 171 "omapfb.mode=dvi:${dvimode} " \ 172 "omapfb.debug=y " \ 173 "omapdss.def_disp=${defaultdisplay} " \ 174 "root=${mmcroot} " \ 175 "rootfstype=${mmcrootfstype}\0" \ 176 "nandargs=setenv bootargs console=${console} " \ 177 "mpurate=${mpurate} " \ 178 "vram=${vram} " \ 179 "omapfb.mode=dvi:${dvimode} " \ 180 "omapfb.debug=y " \ 181 "omapdss.def_disp=${defaultdisplay} " \ 182 "root=${nandroot} " \ 183 "rootfstype=${nandrootfstype}\0" \ 184 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 185 "bootscript=echo Running bootscript from mmc ...; " \ 186 "source ${loadaddr}\0" \ 187 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 188 "mmcboot=echo Booting from mmc ...; " \ 189 "run mmcargs; " \ 190 "bootm ${loadaddr}\0" \ 191 "nandboot=echo Booting from nand ...; " \ 192 "run nandargs; " \ 193 "nand read ${loadaddr} 280000 400000; " \ 194 "bootm ${loadaddr}\0" \ 195 196 #define CONFIG_BOOTCOMMAND \ 197 "if mmc rescan ${mmcdev}; then " \ 198 "if run loadbootscript; then " \ 199 "run bootscript; " \ 200 "else " \ 201 "if run loaduimage; then " \ 202 "run mmcboot; " \ 203 "else run nandboot; " \ 204 "fi; " \ 205 "fi; " \ 206 "else run nandboot; fi" 207 208 #define CONFIG_AUTO_COMPLETE 1 209 /* 210 * Miscellaneous configurable options 211 */ 212 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 213 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 214 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 215 #define CONFIG_SYS_PROMPT "Overo # " 216 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 217 /* Print Buffer Size */ 218 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 219 sizeof(CONFIG_SYS_PROMPT) + 16) 220 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 221 /* args */ 222 /* Boot Argument Buffer Size */ 223 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 224 /* memtest works on */ 225 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 226 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 227 0x01F00000) /* 31MB */ 228 229 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 230 /* address */ 231 /* 232 * OMAP3 has 12 GP timers, they can be driven by the system clock 233 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 234 * This rate is divided by a local divisor. 235 */ 236 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 237 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 238 #define CONFIG_SYS_HZ 1000 239 240 /*----------------------------------------------------------------------- 241 * Stack sizes 242 * 243 * The stack sizes are set up in start.S using the settings below 244 */ 245 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 246 #ifdef CONFIG_USE_IRQ 247 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ 248 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ 249 #endif 250 251 /*----------------------------------------------------------------------- 252 * Physical Memory Map 253 */ 254 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 255 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 256 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 257 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 258 259 /* SDRAM Bank Allocation method */ 260 #define SDRC_R_B_C 1 261 262 /*----------------------------------------------------------------------- 263 * FLASH and environment organization 264 */ 265 266 /* **** PISMO SUPPORT *** */ 267 268 /* Configure the PISMO */ 269 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 270 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 271 272 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 273 274 #define CONFIG_SYS_FLASH_BASE boot_flash_base 275 276 /* Monitor at start of flash */ 277 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 278 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 279 280 #define CONFIG_ENV_IS_IN_NAND 1 281 #define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ 282 #define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ 283 284 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 285 #define CONFIG_ENV_OFFSET boot_flash_off 286 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 287 288 #ifndef __ASSEMBLY__ 289 extern unsigned int boot_flash_base; 290 extern volatile unsigned int boot_flash_env_addr; 291 extern unsigned int boot_flash_off; 292 extern unsigned int boot_flash_sec; 293 extern unsigned int boot_flash_type; 294 #endif 295 296 #if defined(CONFIG_CMD_NET) 297 /*---------------------------------------------------------------------------- 298 * SMSC9211 Ethernet from SMSC9118 family 299 *---------------------------------------------------------------------------- 300 */ 301 302 #define CONFIG_NET_MULTI 303 #define CONFIG_SMC911X 1 304 #define CONFIG_SMC911X_32_BIT 305 #define CONFIG_SMC911X_BASE 0x2C000000 306 307 #endif /* (CONFIG_CMD_NET) */ 308 309 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 310 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 311 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 312 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 313 CONFIG_SYS_INIT_RAM_SIZE - \ 314 GENERATED_GBL_DATA_SIZE) 315 316 #endif /* __CONFIG_H */ 317