1 /* 2 * Configuration settings for the Gumstix Overo board. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 #include <asm/sizes.h> 23 24 /* 25 * High Level Configuration Options 26 */ 27 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ 28 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 29 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 30 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 31 #define CONFIG_OMAP3_OVERO 1 /* working with overo */ 32 33 #include <asm/arch/cpu.h> /* get chip and board defs */ 34 #include <asm/arch/omap3.h> 35 36 /* Clock Defines */ 37 #define V_OSCK 26000000 /* Clock output from T2 */ 38 #define V_SCLK (V_OSCK >> 1) 39 40 #undef CONFIG_USE_IRQ /* no support for IRQs */ 41 #define CONFIG_MISC_INIT_R 42 43 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 44 #define CONFIG_SETUP_MEMORY_TAGS 1 45 #define CONFIG_INITRD_TAG 1 46 #define CONFIG_REVISION_TAG 1 47 48 /* 49 * Size of malloc() pool 50 */ 51 #define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ 52 /* Sector */ 53 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) 54 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ 55 /* initial data */ 56 57 /* 58 * Hardware drivers 59 */ 60 61 /* 62 * NS16550 Configuration 63 */ 64 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 65 66 #define CONFIG_SYS_NS16550 67 #define CONFIG_SYS_NS16550_SERIAL 68 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 69 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 70 71 /* 72 * select serial console configuration 73 */ 74 #define CONFIG_CONS_INDEX 3 75 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 76 #define CONFIG_SERIAL3 3 77 78 /* allow to overwrite serial and ethaddr */ 79 #define CONFIG_ENV_OVERWRITE 80 #define CONFIG_BAUDRATE 115200 81 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 82 115200} 83 #define CONFIG_MMC 1 84 #define CONFIG_OMAP3_MMC 1 85 #define CONFIG_DOS_PARTITION 1 86 87 /* commands to include */ 88 #include <config_cmd_default.h> 89 90 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 91 #define CONFIG_CMD_FAT /* FAT support */ 92 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 93 94 #define CONFIG_CMD_I2C /* I2C serial bus support */ 95 #define CONFIG_CMD_MMC /* MMC support */ 96 #define CONFIG_CMD_NAND /* NAND support */ 97 98 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 99 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 100 #undef CONFIG_CMD_IMI /* iminfo */ 101 #undef CONFIG_CMD_IMLS /* List all found images */ 102 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 103 #undef CONFIG_CMD_NFS /* NFS support */ 104 105 #define CONFIG_SYS_NO_FLASH 106 #define CONFIG_SYS_I2C_SPEED 100000 107 #define CONFIG_SYS_I2C_SLAVE 1 108 #define CONFIG_SYS_I2C_BUS 0 109 #define CONFIG_SYS_I2C_BUS_SELECT 1 110 #define CONFIG_DRIVER_OMAP34XX_I2C 1 111 112 /* 113 * Board NAND Info. 114 */ 115 #define CONFIG_NAND_OMAP_GPMC 116 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 117 /* to access nand */ 118 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 119 /* to access nand */ 120 /* at CS0 */ 121 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 122 123 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 124 /* devices */ 125 #define SECTORSIZE 512 126 127 #define NAND_ALLOW_ERASE_ALL 128 #define ADDR_COLUMN 1 129 #define ADDR_PAGE 2 130 #define ADDR_COLUMN_PAGE 3 131 132 #define NAND_ChipID_UNKNOWN 0x00 133 #define NAND_MAX_FLOORS 1 134 #define NAND_MAX_CHIPS 1 135 #define NAND_NO_RB 1 136 #define CONFIG_SYS_NAND_WP 137 138 #define CONFIG_JFFS2_NAND 139 /* nand device jffs2 lives on */ 140 #define CONFIG_JFFS2_DEV "nand0" 141 /* start of jffs2 partition */ 142 #define CONFIG_JFFS2_PART_OFFSET 0x680000 143 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 144 /* partition */ 145 146 /* Environment information */ 147 #define CONFIG_BOOTDELAY 5 148 149 #define CONFIG_EXTRA_ENV_SETTINGS \ 150 "loadaddr=0x82000000\0" \ 151 "console=ttyS2,115200n8\0" \ 152 "videomode=1024x768@60,vxres=1024,vyres=768\0" \ 153 "videospec=omapfb:vram:2M,vram:4M\0" \ 154 "mmcargs=setenv bootargs console=${console} " \ 155 "video=${videospec},mode:${videomode} " \ 156 "root=/dev/mmcblk0p2 rw " \ 157 "rootfstype=ext3 rootwait\0" \ 158 "nandargs=setenv bootargs console=${console} " \ 159 "video=${videospec},mode:${videomode} " \ 160 "root=/dev/mtdblock4 rw " \ 161 "rootfstype=jffs2\0" \ 162 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 163 "bootscript=echo Running bootscript from mmc ...; " \ 164 "autoscr ${loadaddr}\0" \ 165 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 166 "mmcboot=echo Booting from mmc ...; " \ 167 "run mmcargs; " \ 168 "bootm ${loadaddr}\0" \ 169 "nandboot=echo Booting from nand ...; " \ 170 "run nandargs; " \ 171 "nand read ${loadaddr} 280000 400000; " \ 172 "bootm ${loadaddr}\0" \ 173 174 #define CONFIG_BOOTCOMMAND \ 175 "if mmcinit; then " \ 176 "if run loadbootscript; then " \ 177 "run bootscript; " \ 178 "else " \ 179 "if run loaduimage; then " \ 180 "run mmcboot; " \ 181 "else run nandboot; " \ 182 "fi; " \ 183 "fi; " \ 184 "else run nandboot; fi" 185 186 #define CONFIG_AUTO_COMPLETE 1 187 /* 188 * Miscellaneous configurable options 189 */ 190 #define V_PROMPT "Overo # " 191 192 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 193 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 194 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 195 #define CONFIG_SYS_PROMPT V_PROMPT 196 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 197 /* Print Buffer Size */ 198 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 199 sizeof(CONFIG_SYS_PROMPT) + 16) 200 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 201 /* args */ 202 /* Boot Argument Buffer Size */ 203 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 204 /* memtest works on */ 205 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 206 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 207 0x01F00000) /* 31MB */ 208 209 #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, */ 210 /* in Hz */ 211 212 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 213 /* address */ 214 215 /* 216 * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by 217 * 32KHz clk, or from external sig. This rate is divided by a local divisor. 218 */ 219 #define V_PVT 7 220 221 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 222 #define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ 223 #define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) 224 225 /*----------------------------------------------------------------------- 226 * Stack sizes 227 * 228 * The stack sizes are set up in start.S using the settings below 229 */ 230 #define CONFIG_STACKSIZE SZ_128K /* regular stack */ 231 #ifdef CONFIG_USE_IRQ 232 #define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ 233 #define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ 234 #endif 235 236 /*----------------------------------------------------------------------- 237 * Physical Memory Map 238 */ 239 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 240 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 241 #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ 242 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 243 244 /* SDRAM Bank Allocation method */ 245 #define SDRC_R_B_C 1 246 247 /*----------------------------------------------------------------------- 248 * FLASH and environment organization 249 */ 250 251 /* **** PISMO SUPPORT *** */ 252 253 /* Configure the PISMO */ 254 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 255 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 256 257 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ 258 /* one chip */ 259 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 260 #define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ 261 262 #define CONFIG_SYS_FLASH_BASE boot_flash_base 263 264 /* Monitor at start of flash */ 265 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 266 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 267 268 #define CONFIG_ENV_IS_IN_NAND 1 269 #define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ 270 #define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ 271 272 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 273 #define CONFIG_ENV_OFFSET boot_flash_off 274 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 275 276 /*----------------------------------------------------------------------- 277 * CFI FLASH driver setup 278 */ 279 /* timeout values are in ticks */ 280 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 281 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 282 283 /* Flash banks JFFS2 should use */ 284 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 285 CONFIG_SYS_MAX_NAND_DEVICE) 286 #define CONFIG_SYS_JFFS2_MEM_NAND 287 /* use flash_info[2] */ 288 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 289 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 290 291 #ifndef __ASSEMBLY__ 292 extern gpmc_csx_t *nand_cs_base; 293 extern gpmc_t *gpmc_cfg_base; 294 extern unsigned int boot_flash_base; 295 extern volatile unsigned int boot_flash_env_addr; 296 extern unsigned int boot_flash_off; 297 extern unsigned int boot_flash_sec; 298 extern unsigned int boot_flash_type; 299 #endif 300 301 302 #define WRITE_NAND_COMMAND(d, adr)\ 303 writel(d, &nand_cs_base->nand_cmd) 304 #define WRITE_NAND_ADDRESS(d, adr)\ 305 writel(d, &nand_cs_base->nand_adr) 306 #define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) 307 #define READ_NAND(adr) readl(&nand_cs_base->nand_dat) 308 309 /* Other NAND Access APIs */ 310 #define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ 311 while (0) 312 #define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ 313 while (0) 314 #define NAND_DISABLE_CE(nand) 315 #define NAND_ENABLE_CE(nand) 316 #define NAND_WAIT_READY(nand) udelay(10) 317 318 #endif /* __CONFIG_H */ 319