1 /* 2 * Configuration settings for the Gumstix Overo board. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc. 17 */ 18 19 #ifndef __CONFIG_H 20 #define __CONFIG_H 21 22 /* 23 * High Level Configuration Options 24 */ 25 #define CONFIG_OMAP /* in a TI OMAP core */ 26 #define CONFIG_OMAP34XX /* which is a 34XX */ 27 #define CONFIG_OMAP3_OVERO /* working with overo */ 28 #define CONFIG_OMAP_GPIO 29 30 #define CONFIG_SDRC /* The chip has SDRC controller */ 31 32 #include <asm/arch/cpu.h> /* get chip and board defs */ 33 #include <asm/arch/omap3.h> 34 35 /* 36 * Display CPU and Board information 37 */ 38 #define CONFIG_DISPLAY_CPUINFO 39 #define CONFIG_DISPLAY_BOARDINFO 40 41 /* Clock Defines */ 42 #define V_OSCK 26000000 /* Clock output from T2 */ 43 #define V_SCLK (V_OSCK >> 1) 44 45 #define CONFIG_MISC_INIT_R 46 47 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 48 #define CONFIG_SETUP_MEMORY_TAGS 49 #define CONFIG_INITRD_TAG 50 #define CONFIG_REVISION_TAG 51 52 #define CONFIG_OF_LIBFDT 53 54 /* 55 * Size of malloc() pool 56 */ 57 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 58 /* Sector */ 59 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 60 61 /* 62 * Hardware drivers 63 */ 64 65 /* 66 * NS16550 Configuration 67 */ 68 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 69 70 #define CONFIG_SYS_NS16550 71 #define CONFIG_SYS_NS16550_SERIAL 72 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 73 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 74 75 /* 76 * select serial console configuration 77 */ 78 #define CONFIG_CONS_INDEX 3 79 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 80 #define CONFIG_SERIAL3 3 81 82 /* allow to overwrite serial and ethaddr */ 83 #define CONFIG_ENV_OVERWRITE 84 #define CONFIG_BAUDRATE 115200 85 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 86 115200} 87 #define CONFIG_GENERIC_MMC 88 #define CONFIG_MMC 89 #define CONFIG_OMAP_HSMMC 90 #define CONFIG_DOS_PARTITION 91 92 /* commands to include */ 93 #include <config_cmd_default.h> 94 95 #define CONFIG_CMD_CACHE 96 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 97 #define CONFIG_CMD_FAT /* FAT support */ 98 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 99 100 #define CONFIG_CMD_I2C /* I2C serial bus support */ 101 #define CONFIG_CMD_MMC /* MMC support */ 102 #define CONFIG_CMD_NAND /* NAND support */ 103 104 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 105 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 106 #undef CONFIG_CMD_IMI /* iminfo */ 107 #undef CONFIG_CMD_IMLS /* List all found images */ 108 #undef CONFIG_CMD_NFS /* NFS support */ 109 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 110 111 #define CONFIG_SYS_NO_FLASH 112 #define CONFIG_HARD_I2C 113 #define CONFIG_SYS_I2C_SPEED 100000 114 #define CONFIG_SYS_I2C_SLAVE 1 115 #define CONFIG_I2C_MULTI_BUS 116 #define CONFIG_DRIVER_OMAP34XX_I2C 117 118 /* 119 * TWL4030 120 */ 121 #define CONFIG_TWL4030_POWER 122 #define CONFIG_TWL4030_LED 123 124 /* 125 * Board NAND Info. 126 */ 127 #define CONFIG_SYS_NAND_QUIET_TEST 128 #define CONFIG_NAND_OMAP_GPMC 129 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 130 /* to access nand */ 131 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 132 /* to access nand */ 133 /* at CS0 */ 134 #define GPMC_NAND_ECC_LP_x16_LAYOUT 135 136 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 137 /* devices */ 138 #define CONFIG_JFFS2_NAND 139 /* nand device jffs2 lives on */ 140 #define CONFIG_JFFS2_DEV "nand0" 141 /* start of jffs2 partition */ 142 #define CONFIG_JFFS2_PART_OFFSET 0x680000 143 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 144 /* partition */ 145 146 /* Environment information */ 147 #define CONFIG_BOOTDELAY 5 148 149 #define CONFIG_EXTRA_ENV_SETTINGS \ 150 "loadaddr=0x82000000\0" \ 151 "console=ttyO2,115200n8\0" \ 152 "mpurate=500\0" \ 153 "optargs=\0" \ 154 "vram=12M\0" \ 155 "dvimode=1024x768MR-16@60\0" \ 156 "defaultdisplay=dvi\0" \ 157 "mmcdev=0\0" \ 158 "mmcroot=/dev/mmcblk0p2 rw\0" \ 159 "mmcrootfstype=ext3 rootwait\0" \ 160 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 161 "nandrootfstype=ubifs\0" \ 162 "mmcargs=setenv bootargs console=${console} " \ 163 "${optargs} " \ 164 "mpurate=${mpurate} " \ 165 "vram=${vram} " \ 166 "omapfb.mode=dvi:${dvimode} " \ 167 "omapdss.def_disp=${defaultdisplay} " \ 168 "root=${mmcroot} " \ 169 "rootfstype=${mmcrootfstype}\0" \ 170 "nandargs=setenv bootargs console=${console} " \ 171 "${optargs} " \ 172 "mpurate=${mpurate} " \ 173 "vram=${vram} " \ 174 "omapfb.mode=dvi:${dvimode} " \ 175 "omapdss.def_disp=${defaultdisplay} " \ 176 "root=${nandroot} " \ 177 "rootfstype=${nandrootfstype}\0" \ 178 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 179 "bootscript=echo Running bootscript from mmc ...; " \ 180 "source ${loadaddr}\0" \ 181 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 182 "mmcboot=echo Booting from mmc ...; " \ 183 "run mmcargs; " \ 184 "bootm ${loadaddr}\0" \ 185 "nandboot=echo Booting from nand ...; " \ 186 "run nandargs; " \ 187 "nand read ${loadaddr} 280000 400000; " \ 188 "bootm ${loadaddr}\0" \ 189 190 #define CONFIG_BOOTCOMMAND \ 191 "mmc dev ${mmcdev}; if mmc rescan; then " \ 192 "if run loadbootscript; then " \ 193 "run bootscript; " \ 194 "else " \ 195 "if run loaduimage; then " \ 196 "run mmcboot; " \ 197 "else run nandboot; " \ 198 "fi; " \ 199 "fi; " \ 200 "else run nandboot; fi" 201 202 #define CONFIG_AUTO_COMPLETE 1 203 /* 204 * Miscellaneous configurable options 205 */ 206 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 207 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 208 #define CONFIG_SYS_PROMPT "Overo # " 209 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 210 /* Print Buffer Size */ 211 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 212 sizeof(CONFIG_SYS_PROMPT) + 16) 213 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 214 /* args */ 215 /* Boot Argument Buffer Size */ 216 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 217 /* memtest works on */ 218 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 219 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 220 0x01F00000) /* 31MB */ 221 222 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 223 /* address */ 224 /* 225 * OMAP3 has 12 GP timers, they can be driven by the system clock 226 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 227 * This rate is divided by a local divisor. 228 */ 229 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 230 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 231 #define CONFIG_SYS_HZ 1000 232 233 /*----------------------------------------------------------------------- 234 * Physical Memory Map 235 */ 236 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 237 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 238 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 239 240 /*----------------------------------------------------------------------- 241 * FLASH and environment organization 242 */ 243 244 /* **** PISMO SUPPORT *** */ 245 246 /* Configure the PISMO */ 247 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 248 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 249 250 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 251 252 #if defined(CONFIG_CMD_NAND) 253 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE 254 #endif 255 256 /* Monitor at start of flash */ 257 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 258 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 259 260 #define CONFIG_ENV_IS_IN_NAND 261 #define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ 262 #define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ 263 264 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 265 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 266 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 267 268 #if defined(CONFIG_CMD_NET) 269 /*---------------------------------------------------------------------------- 270 * SMSC9211 Ethernet from SMSC9118 family 271 *---------------------------------------------------------------------------- 272 */ 273 274 #define CONFIG_SMC911X 275 #define CONFIG_SMC911X_32_BIT 276 #define CONFIG_SMC911X_BASE 0x2C000000 277 278 #endif /* (CONFIG_CMD_NET) */ 279 280 /* 281 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 282 * and older u-boot.bin with the new U-Boot SPL. 283 */ 284 #define CONFIG_SYS_TEXT_BASE 0x80008000 285 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 286 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 287 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 288 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 289 CONFIG_SYS_INIT_RAM_SIZE - \ 290 GENERATED_GBL_DATA_SIZE) 291 292 #define CONFIG_SYS_CACHELINE_SIZE 64 293 294 /* Defines for SPL */ 295 #define CONFIG_SPL 296 #define CONFIG_SPL_FRAMEWORK 297 #define CONFIG_SPL_NAND_SIMPLE 298 #define CONFIG_SPL_TEXT_BASE 0x40200800 299 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 300 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 301 302 /* move malloc and bss high to prevent clashing with the main image */ 303 #define CONFIG_SYS_SPL_MALLOC_START 0x87000000 304 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 305 #define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */ 306 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 307 308 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 309 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 310 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 311 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" 312 313 #define CONFIG_SPL_BOARD_INIT 314 #define CONFIG_SPL_LIBCOMMON_SUPPORT 315 #define CONFIG_SPL_LIBDISK_SUPPORT 316 #define CONFIG_SPL_I2C_SUPPORT 317 #define CONFIG_SPL_LIBGENERIC_SUPPORT 318 #define CONFIG_SPL_MMC_SUPPORT 319 #define CONFIG_SPL_FAT_SUPPORT 320 #define CONFIG_SPL_SERIAL_SUPPORT 321 #define CONFIG_SPL_NAND_SUPPORT 322 #define CONFIG_SPL_NAND_BASE 323 #define CONFIG_SPL_NAND_DRIVERS 324 #define CONFIG_SPL_NAND_ECC 325 #define CONFIG_SPL_GPIO_SUPPORT 326 #define CONFIG_SPL_POWER_SUPPORT 327 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 328 329 /* NAND boot config */ 330 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 331 #define CONFIG_SYS_NAND_PAGE_COUNT 64 332 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 333 #define CONFIG_SYS_NAND_OOBSIZE 64 334 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 335 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 336 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 337 10, 11, 12, 13} 338 #define CONFIG_SYS_NAND_ECCSIZE 512 339 #define CONFIG_SYS_NAND_ECCBYTES 3 340 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 341 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 342 343 #endif /* __CONFIG_H */ 344