1 /* 2 * Configuration settings for the Gumstix Overo board. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 23 /* 24 * High Level Configuration Options 25 */ 26 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 27 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 28 #define CONFIG_OMAP3_OVERO 1 /* working with overo */ 29 30 #define CONFIG_SDRC /* The chip has SDRC controller */ 31 32 #include <asm/arch/cpu.h> /* get chip and board defs */ 33 #include <asm/arch/omap3.h> 34 35 /* 36 * Display CPU and Board information 37 */ 38 #define CONFIG_DISPLAY_CPUINFO 1 39 #define CONFIG_DISPLAY_BOARDINFO 1 40 41 /* Clock Defines */ 42 #define V_OSCK 26000000 /* Clock output from T2 */ 43 #define V_SCLK (V_OSCK >> 1) 44 45 #undef CONFIG_USE_IRQ /* no support for IRQs */ 46 #define CONFIG_MISC_INIT_R 47 48 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 49 #define CONFIG_SETUP_MEMORY_TAGS 1 50 #define CONFIG_INITRD_TAG 1 51 #define CONFIG_REVISION_TAG 1 52 53 #define CONFIG_OF_LIBFDT 1 54 55 /* 56 * Size of malloc() pool 57 */ 58 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 59 /* Sector */ 60 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 61 62 /* 63 * Hardware drivers 64 */ 65 66 /* 67 * NS16550 Configuration 68 */ 69 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 70 71 #define CONFIG_SYS_NS16550 72 #define CONFIG_SYS_NS16550_SERIAL 73 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 74 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 75 76 /* 77 * select serial console configuration 78 */ 79 #define CONFIG_CONS_INDEX 3 80 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 81 #define CONFIG_SERIAL3 3 82 83 /* allow to overwrite serial and ethaddr */ 84 #define CONFIG_ENV_OVERWRITE 85 #define CONFIG_BAUDRATE 115200 86 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 87 115200} 88 #define CONFIG_GENERIC_MMC 1 89 #define CONFIG_MMC 1 90 #define CONFIG_OMAP_HSMMC 1 91 #define CONFIG_DOS_PARTITION 1 92 93 /* DDR - I use Micron DDR */ 94 #define CONFIG_OMAP3_MICRON_DDR 1 95 96 /* commands to include */ 97 #include <config_cmd_default.h> 98 99 #define CONFIG_CMD_CACHE 100 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 101 #define CONFIG_CMD_FAT /* FAT support */ 102 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 103 104 #define CONFIG_CMD_I2C /* I2C serial bus support */ 105 #define CONFIG_CMD_MMC /* MMC support */ 106 #define CONFIG_CMD_NAND /* NAND support */ 107 108 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 109 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 110 #undef CONFIG_CMD_IMI /* iminfo */ 111 #undef CONFIG_CMD_IMLS /* List all found images */ 112 #undef CONFIG_CMD_NFS /* NFS support */ 113 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 114 115 #define CONFIG_SYS_NO_FLASH 116 #define CONFIG_HARD_I2C 1 117 #define CONFIG_SYS_I2C_SPEED 100000 118 #define CONFIG_SYS_I2C_SLAVE 1 119 #define CONFIG_SYS_I2C_BUS 0 120 #define CONFIG_SYS_I2C_BUS_SELECT 1 121 #define CONFIG_I2C_MULTI_BUS 1 122 #define CONFIG_DRIVER_OMAP34XX_I2C 1 123 124 /* 125 * TWL4030 126 */ 127 #define CONFIG_TWL4030_POWER 1 128 #define CONFIG_TWL4030_LED 1 129 130 /* 131 * Board NAND Info. 132 */ 133 #define CONFIG_SYS_NAND_QUIET_TEST 1 134 #define CONFIG_NAND_OMAP_GPMC 135 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 136 /* to access nand */ 137 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 138 /* to access nand */ 139 /* at CS0 */ 140 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 141 142 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 143 /* devices */ 144 #define CONFIG_JFFS2_NAND 145 /* nand device jffs2 lives on */ 146 #define CONFIG_JFFS2_DEV "nand0" 147 /* start of jffs2 partition */ 148 #define CONFIG_JFFS2_PART_OFFSET 0x680000 149 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 150 /* partition */ 151 152 /* Environment information */ 153 #define CONFIG_BOOTDELAY 5 154 155 #define CONFIG_EXTRA_ENV_SETTINGS \ 156 "loadaddr=0x82000000\0" \ 157 "console=ttyO2,115200n8\0" \ 158 "mpurate=500\0" \ 159 "optargs=\0" \ 160 "vram=12M\0" \ 161 "dvimode=1024x768MR-16@60\0" \ 162 "defaultdisplay=dvi\0" \ 163 "mmcdev=0\0" \ 164 "mmcroot=/dev/mmcblk0p2 rw\0" \ 165 "mmcrootfstype=ext3 rootwait\0" \ 166 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 167 "nandrootfstype=ubifs\0" \ 168 "mmcargs=setenv bootargs console=${console} " \ 169 "${optargs} " \ 170 "mpurate=${mpurate} " \ 171 "vram=${vram} " \ 172 "omapfb.mode=dvi:${dvimode} " \ 173 "omapdss.def_disp=${defaultdisplay} " \ 174 "root=${mmcroot} " \ 175 "rootfstype=${mmcrootfstype}\0" \ 176 "nandargs=setenv bootargs console=${console} " \ 177 "${optargs} " \ 178 "mpurate=${mpurate} " \ 179 "vram=${vram} " \ 180 "omapfb.mode=dvi:${dvimode} " \ 181 "omapdss.def_disp=${defaultdisplay} " \ 182 "root=${nandroot} " \ 183 "rootfstype=${nandrootfstype}\0" \ 184 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 185 "bootscript=echo Running bootscript from mmc ...; " \ 186 "source ${loadaddr}\0" \ 187 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 188 "mmcboot=echo Booting from mmc ...; " \ 189 "run mmcargs; " \ 190 "bootm ${loadaddr}\0" \ 191 "nandboot=echo Booting from nand ...; " \ 192 "run nandargs; " \ 193 "nand read ${loadaddr} 280000 400000; " \ 194 "bootm ${loadaddr}\0" \ 195 196 #define CONFIG_BOOTCOMMAND \ 197 "if mmc rescan ${mmcdev}; then " \ 198 "if run loadbootscript; then " \ 199 "run bootscript; " \ 200 "else " \ 201 "if run loaduimage; then " \ 202 "run mmcboot; " \ 203 "else run nandboot; " \ 204 "fi; " \ 205 "fi; " \ 206 "else run nandboot; fi" 207 208 #define CONFIG_AUTO_COMPLETE 1 209 /* 210 * Miscellaneous configurable options 211 */ 212 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 213 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 214 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 215 #define CONFIG_SYS_PROMPT "Overo # " 216 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 217 /* Print Buffer Size */ 218 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 219 sizeof(CONFIG_SYS_PROMPT) + 16) 220 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 221 /* args */ 222 /* Boot Argument Buffer Size */ 223 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 224 /* memtest works on */ 225 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 226 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 227 0x01F00000) /* 31MB */ 228 229 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 230 /* address */ 231 /* 232 * OMAP3 has 12 GP timers, they can be driven by the system clock 233 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 234 * This rate is divided by a local divisor. 235 */ 236 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 237 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 238 #define CONFIG_SYS_HZ 1000 239 240 /*----------------------------------------------------------------------- 241 * Stack sizes 242 * 243 * The stack sizes are set up in start.S using the settings below 244 */ 245 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 246 247 /*----------------------------------------------------------------------- 248 * Physical Memory Map 249 */ 250 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 251 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 252 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 253 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 254 255 /*----------------------------------------------------------------------- 256 * FLASH and environment organization 257 */ 258 259 /* **** PISMO SUPPORT *** */ 260 261 /* Configure the PISMO */ 262 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 263 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 264 265 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 266 267 #if defined(CONFIG_CMD_NAND) 268 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE 269 #endif 270 271 /* Monitor at start of flash */ 272 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 273 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 274 275 #define CONFIG_ENV_IS_IN_NAND 1 276 #define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ 277 #define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ 278 279 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 280 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 281 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 282 283 #if defined(CONFIG_CMD_NET) 284 /*---------------------------------------------------------------------------- 285 * SMSC9211 Ethernet from SMSC9118 family 286 *---------------------------------------------------------------------------- 287 */ 288 289 #define CONFIG_SMC911X 1 290 #define CONFIG_SMC911X_32_BIT 291 #define CONFIG_SMC911X_BASE 0x2C000000 292 293 #endif /* (CONFIG_CMD_NET) */ 294 295 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 296 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 297 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 298 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 299 CONFIG_SYS_INIT_RAM_SIZE - \ 300 GENERATED_GBL_DATA_SIZE) 301 302 #define CONFIG_SYS_CACHELINE_SIZE 64 303 304 #endif /* __CONFIG_H */ 305