1 /*
2  * Common configuration settings for IGEP technology based boards
3  *
4  * (C) Copyright 2012
5  * ISEE 2007 SL, <www.iseebcn.com>
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __IGEP00X0_H
11 #define __IGEP00X0_H
12 
13 #ifdef CONFIG_BOOT_NAND
14 #define CONFIG_NAND
15 #endif
16 
17 #define CONFIG_NR_DRAM_BANKS            2
18 
19 #include <configs/ti_omap3_common.h>
20 #include <asm/mach-types.h>
21 
22 #undef CONFIG_BOOTDELAY
23 
24 /*
25  * Display CPU and Board information
26  */
27 #define CONFIG_DISPLAY_CPUINFO		1
28 #define CONFIG_DISPLAY_BOARDINFO	1
29 
30 #define CONFIG_MISC_INIT_R
31 
32 #define CONFIG_REVISION_TAG		1
33 
34 /* Status LED available for IGEP0020 and IGEP0030 but not IGEP0032 */
35 #if (CONFIG_MACH_TYPE != MACH_TYPE_IGEP0032)
36 #define CONFIG_STATUS_LED
37 #define CONFIG_BOARD_SPECIFIC_LED
38 #define CONFIG_GPIO_LED
39 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
40 #define RED_LED_GPIO 27
41 #elif (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
42 #define RED_LED_GPIO 16
43 #else
44 #error "status LED not defined for this machine."
45 #endif
46 #define RED_LED_DEV			0
47 #define STATUS_LED_BIT			RED_LED_GPIO
48 #define STATUS_LED_STATE		STATUS_LED_ON
49 #define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
50 #define STATUS_LED_BOOT			RED_LED_DEV
51 #endif
52 
53 /* GPIO banks */
54 #define CONFIG_OMAP3_GPIO_3		/* GPIO64 .. 95 is in GPIO bank 3 */
55 #define CONFIG_OMAP3_GPIO_5		/* GPIO128..159 is in GPIO bank 5 */
56 #define CONFIG_OMAP3_GPIO_6		/* GPIO160..191 is in GPIO bank 6 */
57 
58 /* USB */
59 #define CONFIG_USB_MUSB_UDC		1
60 #define CONFIG_USB_OMAP3		1
61 #define CONFIG_TWL4030_USB		1
62 
63 /* USB device configuration */
64 #define CONFIG_USB_DEVICE		1
65 #define CONFIG_USB_TTY			1
66 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
67 
68 /* Change these to suit your needs */
69 #define CONFIG_USBD_VENDORID		0x0451
70 #define CONFIG_USBD_PRODUCTID		0x5678
71 #define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
72 #define CONFIG_USBD_PRODUCT_NAME	"IGEP"
73 
74 #define CONFIG_CMD_CACHE
75 #ifdef CONFIG_BOOT_ONENAND
76 #define CONFIG_CMD_ONENAND	/* ONENAND support		*/
77 #endif
78 #define CONFIG_CMD_DHCP
79 #define CONFIG_CMD_PING
80 
81 #ifndef CONFIG_SPL_BUILD
82 
83 /* Environment */
84 #define ENV_DEVICE_SETTINGS \
85 	"stdin=serial\0" \
86 	"stdout=serial\0" \
87 	"stderr=serial\0"
88 
89 #define MEM_LAYOUT_SETTINGS \
90 	DEFAULT_LINUX_BOOT_ENV \
91 	"scriptaddr=0x87E00000\0" \
92 	"pxefile_addr_r=0x87F00000\0"
93 
94 #define BOOT_TARGET_DEVICES(func) \
95 	func(MMC, mmc, 0)
96 
97 #include <config_distro_bootcmd.h>
98 
99 
100 #define CONFIG_EXTRA_ENV_SETTINGS \
101 	ENV_DEVICE_SETTINGS \
102 	MEM_LAYOUT_SETTINGS \
103 	BOOTENV
104 
105 #endif
106 
107 /*
108  * FLASH and environment organization
109  */
110 
111 #ifdef CONFIG_BOOT_ONENAND
112 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
113 
114 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
115 
116 #define CONFIG_ENV_IS_IN_ONENAND	1
117 #define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
118 #define CONFIG_ENV_ADDR			ONENAND_ENV_OFFSET
119 #endif
120 
121 #ifdef CONFIG_NAND
122 #define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
123 #define CONFIG_ENV_IS_IN_NAND	        1
124 #define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
125 #define CONFIG_ENV_ADDR			NAND_ENV_OFFSET
126 #endif
127 
128 /*
129  * SMSC911x Ethernet
130  */
131 #if defined(CONFIG_CMD_NET)
132 #define CONFIG_SMC911X
133 #define CONFIG_SMC911X_32_BIT
134 #define CONFIG_SMC911X_BASE		0x2C000000
135 #endif /* (CONFIG_CMD_NET) */
136 
137 /* OneNAND boot config */
138 #ifdef CONFIG_BOOT_ONENAND
139 #define CONFIG_SPL_ONENAND_SUPPORT
140 #define CONFIG_SYS_ONENAND_U_BOOT_OFFS  0x80000
141 #define CONFIG_SYS_ONENAND_PAGE_SIZE	2048
142 #define CONFIG_SPL_ONENAND_LOAD_ADDR    0x80000
143 #define CONFIG_SPL_ONENAND_LOAD_SIZE    \
144 	(512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
145 
146 #endif
147 
148 /* NAND boot config */
149 #ifdef CONFIG_NAND
150 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
151 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
152 #define CONFIG_SYS_NAND_PAGE_COUNT	64
153 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
154 #define CONFIG_SYS_NAND_OOBSIZE		64
155 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
156 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
157 #define CONFIG_SYS_NAND_ECCPOS		{ 2,  3,  4,  5,  6,  7,  8,  9, \
158 					 10, 11, 12, 13, 14, 15, 16, 17, \
159 					 18, 19, 20, 21, 22, 23, 24, 25, \
160 					 26, 27, 28, 29, 30, 31, 32, 33, \
161 					 34, 35, 36, 37, 38, 39, 40, 41, \
162 					 42, 43, 44, 45, 46, 47, 48, 49, \
163 					 50, 51, 52, 53, 54, 55, 56, 57, }
164 #define CONFIG_SYS_NAND_ECCSIZE		512
165 #define CONFIG_SYS_NAND_ECCBYTES	14
166 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
167 #define CONFIG_NAND_OMAP_GPMC
168 #define CONFIG_BCH
169 
170 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
171 /* NAND: SPL falcon mode configs */
172 #ifdef CONFIG_SPL_OS_BOOT
173 #define CONFIG_CMD_SPL_NAND_OFS		0x240000
174 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
175 #define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
176 #endif
177 #endif
178 
179 #endif /* __IGEP00X0_H */
180