1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Author : 5 * Manikandan Pillai <mani.pillai@ti.com> 6 * Derived from Beagle Board and 3430 SDP code by 7 * Richard Woodruff <r-woodruff2@ti.com> 8 * Syed Mohammed Khasim <khasim@ti.com> 9 * 10 * Manikandan Pillai <mani.pillai@ti.com> 11 * 12 * Configuration settings for the TI OMAP3 EVM board. 13 * 14 * See file CREDITS for list of people who contributed to this 15 * project. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * MA 02111-1307 USA 31 */ 32 33 #ifndef __CONFIG_H 34 #define __CONFIG_H 35 #include <asm/sizes.h> 36 37 /* 38 * High Level Configuration Options 39 */ 40 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ 41 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 42 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 43 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 44 #define CONFIG_OMAP3_EVM 1 /* working with EVM */ 45 46 #include <asm/arch/cpu.h> /* get chip and board defs */ 47 #include <asm/arch/omap3.h> 48 49 /* Clock Defines */ 50 #define V_OSCK 26000000 /* Clock output from T2 */ 51 #define V_SCLK (V_OSCK >> 1) 52 53 #undef CONFIG_USE_IRQ /* no support for IRQs */ 54 #define CONFIG_MISC_INIT_R 55 56 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 57 #define CONFIG_SETUP_MEMORY_TAGS 1 58 #define CONFIG_INITRD_TAG 1 59 #define CONFIG_REVISION_TAG 1 60 61 /* 62 * Size of malloc() pool 63 */ 64 #define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ 65 /* Sector */ 66 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) 67 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ 68 /* initial data */ 69 70 /* 71 * Hardware drivers 72 */ 73 74 /* 75 * NS16550 Configuration 76 */ 77 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 78 79 #define CONFIG_SYS_NS16550 80 #define CONFIG_SYS_NS16550_SERIAL 81 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 82 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 83 84 /* 85 * select serial console configuration 86 */ 87 #define CONFIG_CONS_INDEX 1 88 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 89 #define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ 90 91 /* allow to overwrite serial and ethaddr */ 92 #define CONFIG_ENV_OVERWRITE 93 #define CONFIG_BAUDRATE 115200 94 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 95 115200} 96 #define CONFIG_MMC 1 97 #define CONFIG_OMAP3_MMC 1 98 #define CONFIG_DOS_PARTITION 1 99 100 /* commands to include */ 101 #include <config_cmd_default.h> 102 103 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 104 #define CONFIG_CMD_FAT /* FAT support */ 105 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 106 107 #define CONFIG_CMD_I2C /* I2C serial bus support */ 108 #define CONFIG_CMD_MMC /* MMC support */ 109 #define CONFIG_CMD_ONENAND /* ONENAND support */ 110 #define CONFIG_CMD_DHCP 111 #define CONFIG_CMD_PING 112 113 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 114 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 115 #undef CONFIG_CMD_IMI /* iminfo */ 116 #undef CONFIG_CMD_IMLS /* List all found images */ 117 118 #define CONFIG_SYS_NO_FLASH 119 #define CONFIG_SYS_I2C_SPEED 100000 120 #define CONFIG_SYS_I2C_SLAVE 1 121 #define CONFIG_SYS_I2C_BUS 0 122 #define CONFIG_SYS_I2C_BUS_SELECT 1 123 #define CONFIG_DRIVER_OMAP34XX_I2C 1 124 125 /* 126 * Board NAND Info. 127 */ 128 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 129 /* to access nand */ 130 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 131 /* to access */ 132 /* nand at CS0 */ 133 134 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 135 /* NAND devices */ 136 #define SECTORSIZE 512 137 138 #define NAND_ALLOW_ERASE_ALL 139 #define ADDR_COLUMN 1 140 #define ADDR_PAGE 2 141 #define ADDR_COLUMN_PAGE 3 142 143 #define NAND_ChipID_UNKNOWN 0x00 144 #define NAND_MAX_FLOORS 1 145 #define NAND_MAX_CHIPS 1 146 #define NAND_NO_RB 1 147 #define CONFIG_SYS_NAND_WP 148 149 #define CONFIG_JFFS2_NAND 150 /* nand device jffs2 lives on */ 151 #define CONFIG_JFFS2_DEV "nand0" 152 /* start of jffs2 partition */ 153 #define CONFIG_JFFS2_PART_OFFSET 0x680000 154 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 155 156 /* Environment information */ 157 #define CONFIG_BOOTDELAY 10 158 159 #define CONFIG_EXTRA_ENV_SETTINGS \ 160 "loadaddr=0x82000000\0" \ 161 "console=ttyS2,115200n8\0" \ 162 "mmcargs=setenv bootargs console=${console} " \ 163 "root=/dev/mmcblk0p2 rw " \ 164 "rootfstype=ext3 rootwait\0" \ 165 "nandargs=setenv bootargs console=${console} " \ 166 "root=/dev/mtdblock4 rw " \ 167 "rootfstype=jffs2\0" \ 168 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 169 "bootscript=echo Running bootscript from mmc ...; " \ 170 "autoscr ${loadaddr}\0" \ 171 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 172 "mmcboot=echo Booting from mmc ...; " \ 173 "run mmcargs; " \ 174 "bootm ${loadaddr}\0" \ 175 "nandboot=echo Booting from nand ...; " \ 176 "run nandargs; " \ 177 "onenand read ${loadaddr} 280000 400000; " \ 178 "bootm ${loadaddr}\0" \ 179 180 #define CONFIG_BOOTCOMMAND \ 181 "if mmcinit; then " \ 182 "if run loadbootscript; then " \ 183 "run bootscript; " \ 184 "else " \ 185 "if run loaduimage; then " \ 186 "run mmcboot; " \ 187 "else run nandboot; " \ 188 "fi; " \ 189 "fi; " \ 190 "else run nandboot; fi" 191 192 #define CONFIG_AUTO_COMPLETE 1 193 /* 194 * Miscellaneous configurable options 195 */ 196 #define V_PROMPT "OMAP3_EVM # " 197 198 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 199 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 200 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 201 #define CONFIG_SYS_PROMPT V_PROMPT 202 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 203 /* Print Buffer Size */ 204 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 205 sizeof(CONFIG_SYS_PROMPT) + 16) 206 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 207 /* args */ 208 /* Boot Argument Buffer Size */ 209 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 210 /* memtest works on */ 211 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 212 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 213 0x01F00000) /* 31MB */ 214 215 #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, */ 216 /* in Hz */ 217 218 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 219 /* address */ 220 221 /* 222 * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by 223 * 32KHz clk, or from external sig. This rate is divided by a local divisor. 224 */ 225 #define V_PVT 7 226 227 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 228 #define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ 229 #define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) 230 231 /*----------------------------------------------------------------------- 232 * Stack sizes 233 * 234 * The stack sizes are set up in start.S using the settings below 235 */ 236 #define CONFIG_STACKSIZE SZ_128K /* regular stack */ 237 #ifdef CONFIG_USE_IRQ 238 #define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ 239 #define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ 240 #endif 241 242 /*----------------------------------------------------------------------- 243 * Physical Memory Map 244 */ 245 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 246 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 247 #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ 248 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 249 250 /* SDRAM Bank Allocation method */ 251 #define SDRC_R_B_C 1 252 253 /*----------------------------------------------------------------------- 254 * FLASH and environment organization 255 */ 256 257 /* **** PISMO SUPPORT *** */ 258 259 /* Configure the PISMO */ 260 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 261 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 262 263 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 264 /* on one chip */ 265 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 266 #define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ 267 268 #define CONFIG_SYS_FLASH_BASE boot_flash_base 269 270 /* Monitor at start of flash */ 271 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 272 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 273 274 #define CONFIG_ENV_IS_IN_ONENAND 1 275 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 276 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 277 278 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 279 #define CONFIG_ENV_OFFSET boot_flash_off 280 #define CONFIG_ENV_ADDR boot_flash_env_addr 281 282 /*----------------------------------------------------------------------- 283 * CFI FLASH driver setup 284 */ 285 /* timeout values are in ticks */ 286 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 287 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 288 289 /* Flash banks JFFS2 should use */ 290 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 291 CONFIG_SYS_MAX_NAND_DEVICE) 292 #define CONFIG_SYS_JFFS2_MEM_NAND 293 /* use flash_info[2] */ 294 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 295 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 296 297 #ifndef __ASSEMBLY__ 298 extern gpmc_csx_t *nand_cs_base; 299 extern gpmc_t *gpmc_cfg_base; 300 extern unsigned int boot_flash_base; 301 extern volatile unsigned int boot_flash_env_addr; 302 extern unsigned int boot_flash_off; 303 extern unsigned int boot_flash_sec; 304 extern unsigned int boot_flash_type; 305 #endif 306 307 308 #define WRITE_NAND_COMMAND(d, adr)\ 309 writel(d, &nand_cs_base->nand_cmd) 310 #define WRITE_NAND_ADDRESS(d, adr)\ 311 writel(d, &nand_cs_base->nand_adr) 312 #define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) 313 #define READ_NAND(adr) readl(&nand_cs_base->nand_dat) 314 315 /* Other NAND Access APIs */ 316 #define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ 317 while (0) 318 #define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ 319 while (0) 320 #define NAND_DISABLE_CE(nand) 321 #define NAND_ENABLE_CE(nand) 322 #define NAND_WAIT_READY(nand) udelay(10) 323 324 /*---------------------------------------------------------------------------- 325 * SMSC9115 Ethernet from SMSC9118 family 326 *---------------------------------------------------------------------------- 327 */ 328 #if defined(CONFIG_CMD_NET) 329 330 #define CONFIG_DRIVER_SMC911X 331 #define CONFIG_DRIVER_SMC911X_32_BIT 332 #define CONFIG_DRIVER_SMC911X_BASE 0x2C000000 333 334 #endif /* (CONFIG_CMD_NET) */ 335 336 /* 337 * BOOTP fields 338 */ 339 340 #define CONFIG_BOOTP_SUBNETMASK 0x00000001 341 #define CONFIG_BOOTP_GATEWAY 0x00000002 342 #define CONFIG_BOOTP_HOSTNAME 0x00000004 343 #define CONFIG_BOOTP_BOOTPATH 0x00000010 344 345 #endif /* __CONFIG_H */ 346