1 /* 2 * Configuration settings for the TI OMAP3 EVM board. 3 * 4 * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * Author : 7 * Manikandan Pillai <mani.pillai@ti.com> 8 * Derived from Beagle Board and 3430 SDP code by 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <khasim@ti.com> 11 * 12 * Manikandan Pillai <mani.pillai@ti.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __OMAP3EVM_CONFIG_H 18 #define __OMAP3EVM_CONFIG_H 19 20 #include <asm/arch/cpu.h> 21 #include <asm/arch/omap.h> 22 23 /* ---------------------------------------------------------------------------- 24 * Supported U-Boot commands 25 * ---------------------------------------------------------------------------- 26 */ 27 28 #define CONFIG_CMD_JFFS2 29 30 #define CONFIG_CMD_NAND 31 32 /* ---------------------------------------------------------------------------- 33 * Supported U-Boot features 34 * ---------------------------------------------------------------------------- 35 */ 36 #define CONFIG_SYS_LONGHELP 37 38 /* Allow to overwrite serial and ethaddr */ 39 #define CONFIG_ENV_OVERWRITE 40 41 /* Add auto-completion support */ 42 #define CONFIG_AUTO_COMPLETE 43 44 /* ---------------------------------------------------------------------------- 45 * Supported hardware 46 * ---------------------------------------------------------------------------- 47 */ 48 49 /* MMC */ 50 #define CONFIG_MMC 51 #define CONFIG_GENERIC_MMC 52 #define CONFIG_OMAP_HSMMC 53 54 /* SPL */ 55 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 56 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 57 58 /* Partition tables */ 59 #define CONFIG_EFI_PARTITION 60 #define CONFIG_DOS_PARTITION 61 62 /* USB 63 * 64 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard 65 * Enable CONFIG_USB_MUSB_UDD for Device functionalities. 66 */ 67 #define CONFIG_USB_OMAP3 68 #define CONFIG_USB_MUSB_HCD 69 /* #define CONFIG_USB_MUSB_UDC */ 70 71 /* NAND SPL */ 72 #define CONFIG_SPL_NAND_SIMPLE 73 #define CONFIG_SPL_NAND_BASE 74 #define CONFIG_SPL_NAND_DRIVERS 75 #define CONFIG_SPL_NAND_ECC 76 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 77 #define CONFIG_SYS_NAND_PAGE_COUNT 64 78 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 79 #define CONFIG_SYS_NAND_OOBSIZE 64 80 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 81 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 82 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 83 10, 11, 12, 13} 84 #define CONFIG_SYS_NAND_ECCSIZE 512 85 #define CONFIG_SYS_NAND_ECCBYTES 3 86 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 87 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 88 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 89 90 /* 91 * High level configuration options 92 */ 93 #define CONFIG_OMAP /* This is TI OMAP core */ 94 #define CONFIG_OMAP_GPIO 95 /* Common ARM Erratas */ 96 #define CONFIG_ARM_ERRATA_454179 97 #define CONFIG_ARM_ERRATA_430973 98 #define CONFIG_ARM_ERRATA_621766 99 100 #define CONFIG_SDRC /* The chip has SDRC controller */ 101 102 #define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */ 103 #define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */ 104 105 /* 106 * Clock related definitions 107 */ 108 #define V_OSCK 26000000 /* Clock output from T2 */ 109 #define V_SCLK (V_OSCK >> 1) 110 111 /* 112 * OMAP3 has 12 GP timers, they can be driven by the system clock 113 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 114 * This rate is divided by a local divisor. 115 */ 116 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 117 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 118 119 /* Size of environment - 128KB */ 120 #define CONFIG_ENV_SIZE (128 << 10) 121 122 /* Size of malloc pool */ 123 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 124 125 /* 126 * Physical Memory Map 127 * Note 1: CS1 may or may not be populated 128 * Note 2: SDRAM size is expected to be at least 32MB 129 */ 130 #define CONFIG_NR_DRAM_BANKS 2 131 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 132 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 133 134 /* Limits for memtest */ 135 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 136 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 137 0x01F00000) /* 31MB */ 138 139 /* Default load address */ 140 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) 141 142 /* ----------------------------------------------------------------------------- 143 * Hardware drivers 144 * ----------------------------------------------------------------------------- 145 */ 146 147 /* 148 * NS16550 Configuration 149 */ 150 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 151 152 #define CONFIG_SYS_NS16550_SERIAL 153 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 154 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 155 156 /* 157 * select serial console configuration 158 */ 159 #define CONFIG_CONS_INDEX 1 160 #define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ 161 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 162 #define CONFIG_BAUDRATE 115200 163 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 164 115200} 165 166 /* 167 * I2C 168 */ 169 #define CONFIG_SYS_I2C 170 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 171 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 172 #define CONFIG_SYS_I2C_OMAP34XX 173 174 /* 175 * PISMO support 176 */ 177 /* Monitor at start of flash - Reserve 2 sectors */ 178 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 179 180 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 181 182 /* Start location & size of environment */ 183 #define ONENAND_ENV_OFFSET 0x260000 184 #define SMNAND_ENV_OFFSET 0x260000 185 186 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 187 188 /* 189 * NAND 190 */ 191 /* Physical address to access NAND */ 192 #define CONFIG_SYS_NAND_ADDR NAND_BASE 193 194 /* Physical address to access NAND at CS0 */ 195 #define CONFIG_SYS_NAND_BASE NAND_BASE 196 197 /* Max number of NAND devices */ 198 #define CONFIG_SYS_MAX_NAND_DEVICE 1 199 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 200 /* Timeout values (in ticks) */ 201 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 202 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 203 204 /* Flash banks JFFS2 should use */ 205 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 206 CONFIG_SYS_MAX_NAND_DEVICE) 207 208 #define CONFIG_SYS_JFFS2_MEM_NAND 209 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 210 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 211 212 #define CONFIG_JFFS2_NAND 213 /* nand device jffs2 lives on */ 214 #define CONFIG_JFFS2_DEV "nand0" 215 /* Start of jffs2 partition */ 216 #define CONFIG_JFFS2_PART_OFFSET 0x680000 217 /* Size of jffs2 partition */ 218 #define CONFIG_JFFS2_PART_SIZE 0xf980000 219 220 /* 221 * USB 222 */ 223 #ifdef CONFIG_USB_OMAP3 224 225 #ifdef CONFIG_USB_MUSB_HCD 226 227 #define CONGIG_CMD_STORAGE 228 229 #ifdef CONFIG_USB_KEYBOARD 230 #define CONFIG_SYS_USB_EVENT_POLL 231 #define CONFIG_PREBOOT "usb start" 232 #endif /* CONFIG_USB_KEYBOARD */ 233 234 #endif /* CONFIG_USB_MUSB_HCD */ 235 236 #ifdef CONFIG_USB_MUSB_UDC 237 /* USB device configuration */ 238 #define CONFIG_USB_DEVICE 239 #define CONFIG_USB_TTY 240 241 /* Change these to suit your needs */ 242 #define CONFIG_USBD_VENDORID 0x0451 243 #define CONFIG_USBD_PRODUCTID 0x5678 244 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 245 #define CONFIG_USBD_PRODUCT_NAME "EVM" 246 #endif /* CONFIG_USB_MUSB_UDC */ 247 248 #endif /* CONFIG_USB_OMAP3 */ 249 250 /* ---------------------------------------------------------------------------- 251 * U-Boot features 252 * ---------------------------------------------------------------------------- 253 */ 254 #define CONFIG_SYS_MAXARGS 16 /* max args for a command */ 255 256 #define CONFIG_MISC_INIT_R 257 258 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 259 #define CONFIG_SETUP_MEMORY_TAGS 260 #define CONFIG_INITRD_TAG 261 #define CONFIG_REVISION_TAG 262 263 /* Size of Console IO buffer */ 264 #define CONFIG_SYS_CBSIZE 512 265 266 /* Size of print buffer */ 267 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 268 sizeof(CONFIG_SYS_PROMPT) + 16) 269 270 /* Size of bootarg buffer */ 271 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 272 273 #define CONFIG_BOOTFILE "uImage" 274 275 /* 276 * NAND / OneNAND 277 */ 278 #if defined(CONFIG_CMD_NAND) 279 #define CONFIG_SYS_FLASH_BASE NAND_BASE 280 281 #define CONFIG_NAND_OMAP_GPMC 282 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 283 #elif defined(CONFIG_CMD_ONENAND) 284 #define CONFIG_SYS_FLASH_BASE ONENAND_MAP 285 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 286 #endif 287 288 #if !defined(CONFIG_ENV_IS_NOWHERE) 289 #if defined(CONFIG_CMD_NAND) 290 #define CONFIG_ENV_IS_IN_NAND 291 #elif defined(CONFIG_CMD_ONENAND) 292 #define CONFIG_ENV_IS_IN_ONENAND 293 #define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET 294 #endif 295 #endif /* CONFIG_ENV_IS_NOWHERE */ 296 297 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 298 299 #if defined(CONFIG_CMD_NET) 300 301 /* Ethernet (SMSC9115 from SMSC9118 family) */ 302 #define CONFIG_SMC911X 303 #define CONFIG_SMC911X_32_BIT 304 #define CONFIG_SMC911X_BASE 0x2C000000 305 306 /* BOOTP fields */ 307 #define CONFIG_BOOTP_SUBNETMASK 0x00000001 308 #define CONFIG_BOOTP_GATEWAY 0x00000002 309 #define CONFIG_BOOTP_HOSTNAME 0x00000004 310 #define CONFIG_BOOTP_BOOTPATH 0x00000010 311 312 #endif /* CONFIG_CMD_NET */ 313 314 /* Support for relocation */ 315 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 316 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 317 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 318 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 319 CONFIG_SYS_INIT_RAM_SIZE - \ 320 GENERATED_GBL_DATA_SIZE) 321 322 /* ----------------------------------------------------------------------------- 323 * Board specific 324 * ----------------------------------------------------------------------------- 325 */ 326 #define CONFIG_SYS_NO_FLASH 327 328 /* Uncomment to define the board revision statically */ 329 /* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */ 330 331 /* Defines for SPL */ 332 #define CONFIG_SPL_FRAMEWORK 333 #define CONFIG_SPL_TEXT_BASE 0x40200800 334 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 335 CONFIG_SPL_TEXT_BASE) 336 337 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 338 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 339 340 #define CONFIG_SPL_BOARD_INIT 341 #define CONFIG_SPL_OMAP3_ID_NAND 342 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 343 344 /* 345 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 346 * 64 bytes before this address should be set aside for u-boot.img's 347 * header. That is 0x800FFFC0--0x80100000 should not be used for any 348 * other needs. 349 */ 350 #define CONFIG_SYS_TEXT_BASE 0x80100000 351 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 352 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 353 354 /* ----------------------------------------------------------------------------- 355 * Default environment 356 * ----------------------------------------------------------------------------- 357 */ 358 359 #define CONFIG_EXTRA_ENV_SETTINGS \ 360 "loadaddr=0x82000000\0" \ 361 "usbtty=cdc_acm\0" \ 362 "mmcdev=0\0" \ 363 "console=ttyO0,115200n8\0" \ 364 "mmcargs=setenv bootargs console=${console} " \ 365 "root=/dev/mmcblk0p2 rw " \ 366 "rootfstype=ext3 rootwait\0" \ 367 "nandargs=setenv bootargs console=${console} " \ 368 "root=/dev/mtdblock4 rw " \ 369 "rootfstype=jffs2\0" \ 370 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 371 "bootscript=echo Running bootscript from mmc ...; " \ 372 "source ${loadaddr}\0" \ 373 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 374 "mmcboot=echo Booting from mmc ...; " \ 375 "run mmcargs; " \ 376 "bootm ${loadaddr}\0" \ 377 "nandboot=echo Booting from nand ...; " \ 378 "run nandargs; " \ 379 "onenand read ${loadaddr} 280000 400000; " \ 380 "bootm ${loadaddr}\0" \ 381 382 #define CONFIG_BOOTCOMMAND \ 383 "mmc dev ${mmcdev}; if mmc rescan; then " \ 384 "if run loadbootscript; then " \ 385 "run bootscript; " \ 386 "else " \ 387 "if run loaduimage; then " \ 388 "run mmcboot; " \ 389 "else run nandboot; " \ 390 "fi; " \ 391 "fi; " \ 392 "else run nandboot; fi" 393 394 #endif /* __OMAP3EVM_CONFIG_H */ 395