1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Author : 5 * Manikandan Pillai <mani.pillai@ti.com> 6 * Derived from Beagle Board and 3430 SDP code by 7 * Richard Woodruff <r-woodruff2@ti.com> 8 * Syed Mohammed Khasim <khasim@ti.com> 9 * 10 * Manikandan Pillai <mani.pillai@ti.com> 11 * 12 * Configuration settings for the TI OMAP3 EVM board. 13 * 14 * See file CREDITS for list of people who contributed to this 15 * project. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * MA 02111-1307 USA 31 */ 32 33 #ifndef __CONFIG_H 34 #define __CONFIG_H 35 36 /* 37 * High Level Configuration Options 38 */ 39 #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ 40 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 41 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 42 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 43 #define CONFIG_OMAP3_EVM 1 /* working with EVM */ 44 45 #define CONFIG_SDRC /* The chip has SDRC controller */ 46 47 #include <asm/arch/cpu.h> /* get chip and board defs */ 48 #include <asm/arch/omap3.h> 49 50 /* 51 * Display CPU and Board information 52 */ 53 #define CONFIG_DISPLAY_CPUINFO 1 54 #define CONFIG_DISPLAY_BOARDINFO 1 55 56 /* Clock Defines */ 57 #define V_OSCK 26000000 /* Clock output from T2 */ 58 #define V_SCLK (V_OSCK >> 1) 59 60 #undef CONFIG_USE_IRQ /* no support for IRQs */ 61 #define CONFIG_MISC_INIT_R 62 63 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 64 #define CONFIG_SETUP_MEMORY_TAGS 1 65 #define CONFIG_INITRD_TAG 1 66 #define CONFIG_REVISION_TAG 1 67 68 /* 69 * Size of malloc() pool 70 */ 71 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 72 /* Sector */ 73 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 74 /* initial data */ 75 /* 76 * Hardware drivers 77 */ 78 79 /* 80 * NS16550 Configuration 81 */ 82 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 83 84 #define CONFIG_SYS_NS16550 85 #define CONFIG_SYS_NS16550_SERIAL 86 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 87 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 88 89 /* 90 * select serial console configuration 91 */ 92 #define CONFIG_CONS_INDEX 1 93 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 94 #define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ 95 96 /* allow to overwrite serial and ethaddr */ 97 #define CONFIG_ENV_OVERWRITE 98 #define CONFIG_BAUDRATE 115200 99 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 100 115200} 101 #define CONFIG_MMC 1 102 #define CONFIG_OMAP3_MMC 1 103 #define CONFIG_DOS_PARTITION 1 104 105 /* DDR - I use Micron DDR */ 106 #define CONFIG_OMAP3_MICRON_DDR 1 107 108 /* USB 109 * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard 110 * Enable CONFIG_MUSB_UDD for Device functionalities. 111 */ 112 #define CONFIG_USB_OMAP3 1 113 #define CONFIG_MUSB_HCD 1 114 /* #define CONFIG_MUSB_UDC 1 */ 115 116 #ifdef CONFIG_USB_OMAP3 117 118 #ifdef CONFIG_MUSB_HCD 119 #define CONFIG_CMD_USB 120 121 #define CONFIG_USB_STORAGE 122 #define CONGIG_CMD_STORAGE 123 #define CONFIG_CMD_FAT 124 125 #ifdef CONFIG_USB_KEYBOARD 126 #define CONFIG_SYS_USB_EVENT_POLL 127 #define CONFIG_PREBOOT "usb start" 128 #endif /* CONFIG_USB_KEYBOARD */ 129 130 #endif /* CONFIG_MUSB_HCD */ 131 132 #ifdef CONFIG_MUSB_UDC 133 /* USB device configuration */ 134 #define CONFIG_USB_DEVICE 1 135 #define CONFIG_USB_TTY 1 136 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 137 /* Change these to suit your needs */ 138 #define CONFIG_USBD_VENDORID 0x0451 139 #define CONFIG_USBD_PRODUCTID 0x5678 140 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 141 #define CONFIG_USBD_PRODUCT_NAME "EVM" 142 #endif /* CONFIG_MUSB_UDC */ 143 144 #endif /* CONFIG_USB_OMAP3 */ 145 146 /* commands to include */ 147 #include <config_cmd_default.h> 148 149 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 150 #define CONFIG_CMD_FAT /* FAT support */ 151 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 152 153 #define CONFIG_CMD_I2C /* I2C serial bus support */ 154 #define CONFIG_CMD_MMC /* MMC support */ 155 #define CONFIG_CMD_NAND /* NAND support */ 156 #define CONFIG_CMD_DHCP 157 #define CONFIG_CMD_PING 158 159 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 160 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 161 #undef CONFIG_CMD_IMI /* iminfo */ 162 #undef CONFIG_CMD_IMLS /* List all found images */ 163 164 #define CONFIG_SYS_NO_FLASH 165 #define CONFIG_HARD_I2C 1 166 #define CONFIG_SYS_I2C_SPEED 100000 167 #define CONFIG_SYS_I2C_SLAVE 1 168 #define CONFIG_SYS_I2C_BUS 0 169 #define CONFIG_SYS_I2C_BUS_SELECT 1 170 #define CONFIG_DRIVER_OMAP34XX_I2C 1 171 172 /* 173 * TWL4030 174 */ 175 #define CONFIG_TWL4030_POWER 1 176 177 /* 178 * Board NAND Info. 179 */ 180 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 181 /* to access nand */ 182 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 183 /* to access */ 184 /* nand at CS0 */ 185 186 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 187 /* NAND devices */ 188 #define CONFIG_JFFS2_NAND 189 /* nand device jffs2 lives on */ 190 #define CONFIG_JFFS2_DEV "nand0" 191 /* start of jffs2 partition */ 192 #define CONFIG_JFFS2_PART_OFFSET 0x680000 193 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 194 195 /* Environment information */ 196 #define CONFIG_BOOTDELAY 10 197 198 #define CONFIG_BOOTFILE uImage 199 200 #define CONFIG_EXTRA_ENV_SETTINGS \ 201 "loadaddr=0x82000000\0" \ 202 "usbtty=cdc_acm\0" \ 203 "console=ttyS2,115200n8\0" \ 204 "mmcargs=setenv bootargs console=${console} " \ 205 "root=/dev/mmcblk0p2 rw " \ 206 "rootfstype=ext3 rootwait\0" \ 207 "nandargs=setenv bootargs console=${console} " \ 208 "root=/dev/mtdblock4 rw " \ 209 "rootfstype=jffs2\0" \ 210 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 211 "bootscript=echo Running bootscript from mmc ...; " \ 212 "source ${loadaddr}\0" \ 213 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 214 "mmcboot=echo Booting from mmc ...; " \ 215 "run mmcargs; " \ 216 "bootm ${loadaddr}\0" \ 217 "nandboot=echo Booting from nand ...; " \ 218 "run nandargs; " \ 219 "onenand read ${loadaddr} 280000 400000; " \ 220 "bootm ${loadaddr}\0" \ 221 222 #define CONFIG_BOOTCOMMAND \ 223 "if mmc init; then " \ 224 "if run loadbootscript; then " \ 225 "run bootscript; " \ 226 "else " \ 227 "if run loaduimage; then " \ 228 "run mmcboot; " \ 229 "else run nandboot; " \ 230 "fi; " \ 231 "fi; " \ 232 "else run nandboot; fi" 233 234 #define CONFIG_AUTO_COMPLETE 1 235 /* 236 * Miscellaneous configurable options 237 */ 238 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 239 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 240 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 241 #define CONFIG_SYS_PROMPT "OMAP3_EVM # " 242 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 243 /* Print Buffer Size */ 244 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 245 sizeof(CONFIG_SYS_PROMPT) + 16) 246 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 247 /* args */ 248 /* Boot Argument Buffer Size */ 249 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 250 /* memtest works on */ 251 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 252 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 253 0x01F00000) /* 31MB */ 254 255 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 256 /* address */ 257 258 /* 259 * OMAP3 has 12 GP timers, they can be driven by the system clock 260 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 261 * This rate is divided by a local divisor. 262 */ 263 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 264 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 265 #define CONFIG_SYS_HZ 1000 266 267 /*----------------------------------------------------------------------- 268 * Stack sizes 269 * 270 * The stack sizes are set up in start.S using the settings below 271 */ 272 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 273 #ifdef CONFIG_USE_IRQ 274 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ 275 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ 276 #endif 277 278 /*----------------------------------------------------------------------- 279 * Physical Memory Map 280 */ 281 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 282 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 283 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 284 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 285 286 /* SDRAM Bank Allocation method */ 287 #define SDRC_R_B_C 1 288 289 /*----------------------------------------------------------------------- 290 * FLASH and environment organization 291 */ 292 293 /* **** PISMO SUPPORT *** */ 294 295 /* Configure the PISMO */ 296 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 297 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 298 299 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 300 /* on one chip */ 301 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 302 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 303 304 #define CONFIG_SYS_FLASH_BASE boot_flash_base 305 306 /* Monitor at start of flash */ 307 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 308 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 309 310 #if defined(CONFIG_CMD_NAND) 311 #define CONFIG_NAND_OMAP_GPMC 312 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 313 #define CONFIG_ENV_IS_IN_NAND 314 #elif defined(CONFIG_CMD_ONENAND) 315 #define CONFIG_ENV_IS_IN_ONENAND 1 316 #endif 317 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 318 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 319 320 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 321 #define CONFIG_ENV_OFFSET boot_flash_off 322 #define CONFIG_ENV_ADDR boot_flash_env_addr 323 324 /*----------------------------------------------------------------------- 325 * CFI FLASH driver setup 326 */ 327 /* timeout values are in ticks */ 328 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 329 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 330 331 /* Flash banks JFFS2 should use */ 332 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 333 CONFIG_SYS_MAX_NAND_DEVICE) 334 #define CONFIG_SYS_JFFS2_MEM_NAND 335 /* use flash_info[2] */ 336 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 337 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 338 339 #ifndef __ASSEMBLY__ 340 extern unsigned int boot_flash_base; 341 extern volatile unsigned int boot_flash_env_addr; 342 extern unsigned int boot_flash_off; 343 extern unsigned int boot_flash_sec; 344 extern unsigned int boot_flash_type; 345 #endif 346 347 /*---------------------------------------------------------------------------- 348 * SMSC9115 Ethernet from SMSC9118 family 349 *---------------------------------------------------------------------------- 350 */ 351 #if defined(CONFIG_CMD_NET) 352 353 #define CONFIG_NET_MULTI 354 #define CONFIG_SMC911X 355 #define CONFIG_SMC911X_32_BIT 356 #define CONFIG_SMC911X_BASE 0x2C000000 357 358 #endif /* (CONFIG_CMD_NET) */ 359 360 /* 361 * BOOTP fields 362 */ 363 364 #define CONFIG_BOOTP_SUBNETMASK 0x00000001 365 #define CONFIG_BOOTP_GATEWAY 0x00000002 366 #define CONFIG_BOOTP_HOSTNAME 0x00000004 367 #define CONFIG_BOOTP_BOOTPATH 0x00000010 368 369 #endif /* __CONFIG_H */ 370