1 /*
2  * Configuration settings for the QUIPOS Cairo board.
3  *
4  * Copyright (C) DENX GmbH
5  *
6  * Author :
7  *	Albert ARIBAUD <albert.aribaud@3adev.fr>
8  *
9  * Derived from EVM  code by
10  *	Manikandan Pillai <mani.pillai@ti.com>
11  * Itself derived from Beagle Board and 3430 SDP code by
12  *	Richard Woodruff <r-woodruff2@ti.com>
13  *	Syed Mohammed Khasim <khasim@ti.com>
14  *
15  * Also derived from include/configs/omap3_beagle.h
16  *
17  * SPDX-License-Identifier:	GPL-2.0+
18  */
19 
20 #ifndef __OMAP3_CAIRO_CONFIG_H
21 #define __OMAP3_CAIRO_CONFIG_H
22 
23 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
24 
25 /*
26  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
27  * 64 bytes before this address should be set aside for u-boot.img's
28  * header. That is 0x800FFFC0--0x80100000 should not be used for any
29  * other needs.  We use this rather than the inherited defines from
30  * ti_armv7_common.h for backwards compatibility.
31  */
32 #define CONFIG_SYS_TEXT_BASE		0x80100000
33 #define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
34 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
35 #define CONFIG_SPL_BSS_MAX_SIZE		(512 << 10)	/* 512 KB */
36 #define CONFIG_SYS_SPL_MALLOC_START	0x80208000
37 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
38 
39 #define CONFIG_NAND
40 
41 #include <configs/ti_omap3_common.h>
42 
43 #define CONFIG_MISC_INIT_R
44 
45 #define CONFIG_REVISION_TAG		1
46 #define CONFIG_ENV_OVERWRITE
47 
48 /* Enable Multi Bus support for I2C */
49 #define CONFIG_I2C_MULTI_BUS		1
50 
51 /* Probe all devices */
52 #define CONFIG_SYS_I2C_NOPROBES		{ {0x0, 0x0} }
53 
54 #define CONFIG_NAND
55 
56 /* commands to include */
57 #define CONFIG_CMD_NAND_LOCK_UNLOCK
58 
59 /*
60  * TWL4030
61  */
62 #define CONFIG_TWL4030_LED		1
63 
64 /*
65  * Board NAND Info.
66  */
67 #define CONFIG_NAND_OMAP_GPMC
68 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
69 							/* devices */
70 #define CONFIG_EXTRA_ENV_SETTINGS \
71 	"machid=ffffffff\0" \
72 	"fdt_high=0x87000000\0" \
73 	"baudrate=115200\0" \
74 	"fec_addr=00:50:C2:7E:90:F0\0" \
75 	"netmask=255.255.255.0\0" \
76 	"ipaddr=192.168.2.9\0" \
77 	"gateway=192.168.2.1\0" \
78 	"serverip=192.168.2.10\0" \
79 	"nfshost=192.168.2.10\0" \
80 	"stdin=serial\0" \
81 	"stdout=serial\0" \
82 	"stderr=serial\0" \
83 	"bootargs_mmc_ramdisk=mem=128M " \
84 		"console=ttyO1,115200n8 " \
85 		"root=/dev/ram0 rw " \
86 		"initrd=0x81600000,16M " \
87 		"mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
88 		"omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
89 	"mmcboot=mmc init; " \
90 		"fatload mmc 0 0x80000000 uImage; " \
91 		"fatload mmc 0 0x81600000 ramdisk.gz; " \
92 		"setenv bootargs ${bootargs_mmc_ramdisk}; " \
93 		"bootm 0x80000000\0" \
94 	"bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
95 	"root=/dev/nfs " \
96 	"nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
97 	"mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
98 	"omap_vout.vid1_static_vrfb_alloc=y\0" \
99 	"boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
100 	"bootm 0x80000000\0" \
101 	"bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
102 	"root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
103 	"omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
104 	"omapfb.rotate_type=1\0" \
105 	"boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
106 	"bootargs ${bootargs_nand}; bootm 0x80000000\0" \
107 	"ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
108 	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
109 	"i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
110 	"ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
111 	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
112 	"mw 60 09 00 1; i2c mw 60 06 10 1\0" \
113 	"ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
114 	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
115 	"i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
116 	"ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
117 	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
118 	"i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
119 	"flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
120 		"nand erase 0 20000; " \
121 		"fatload mmc 0 0x81600000 MLO; " \
122 		"nandecc hw; " \
123 		"nand write.i 0x81600000 0 20000;\0" \
124 	"flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
125 		"nand erase 80000 40000; " \
126 		"fatload mmc 0 0x81600000 u-boot.bin; " \
127 		"nandecc sw; " \
128 		"nand write.i 0x81600000 80000 40000;\0" \
129 	"flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
130 		"nand erase 280000 300000; " \
131 		"fatload mmc 0 0x81600000 uImage; " \
132 		"nandecc sw; " \
133 		"nand write.i 0x81600000 280000 300000;\0" \
134 	"flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
135 		"nandecc sw; " \
136 		"nand write.jffs2 0x680000 0xFF ${filesize}; " \
137 		"nand erase 680000 ${filesize}; " \
138 		"nand write.jffs2 81600000 680000 ${filesize};\0" \
139 	"flash_scrub=nand scrub; " \
140 		"run flash_xloader; " \
141 		"run flash_uboot; " \
142 		"run flash_kernel; " \
143 		"run flash_rootfs;\0" \
144 	"flash_all=run ledred; " \
145 		"nand erase.chip; " \
146 		"run ledorange; " \
147 		"run flash_xloader; " \
148 		"run flash_uboot; " \
149 		"run flash_kernel; " \
150 		"run flash_rootfs; " \
151 		"run ledgreen; " \
152 		"run boot_nand; \0" \
153 
154 #define CONFIG_BOOTCOMMAND \
155 	"if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
156 	"else run boot_nand; fi"
157 
158 /*
159  * OMAP3 has 12 GP timers, they can be driven by the system clock
160  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
161  * This rate is divided by a local divisor.
162  */
163 #define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
164 
165 /*-----------------------------------------------------------------------
166  * FLASH and environment organization
167  */
168 
169 /* **** PISMO SUPPORT *** */
170 #if defined(CONFIG_CMD_NAND)
171 #define CONFIG_SYS_FLASH_BASE		NAND_BASE
172 #endif
173 
174 /* Monitor at start of flash */
175 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
176 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
177 
178 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
179 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
180 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
181 
182 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
183 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
184 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
185 
186 #define CONFIG_OMAP3_SPI
187 
188 /* Defines for SPL */
189 #define CONFIG_SPL_OMAP3_ID_NAND
190 
191 /* NAND boot config */
192 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
193 #define CONFIG_SYS_NAND_PAGE_COUNT	64
194 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
195 #define CONFIG_SYS_NAND_OOBSIZE		64
196 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
197 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
198 #define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
199 						10, 11, 12, 13}
200 #define CONFIG_SYS_NAND_ECCSIZE		512
201 #define CONFIG_SYS_NAND_ECCBYTES	3
202 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
203 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
204 /* NAND: SPL falcon mode configs */
205 #ifdef CONFIG_SPL_OS_BOOT
206 #define CONFIG_CMD_SPL_NAND_OFS		0x240000
207 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
208 #define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
209 #endif
210 
211 /* env defaults */
212 #define CONFIG_BOOTFILE			"uImage"
213 
214 /* Override OMAP3 common serial console configuration from UART3
215  * to UART2.
216  *
217  * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
218  * are needed and peripheral clocks for UART2 must be enabled in
219  * function per_clocks_enable().
220  */
221 #undef CONFIG_CONS_INDEX
222 #define CONFIG_CONS_INDEX		2
223 #ifdef CONFIG_SPL_BUILD
224 #undef CONFIG_SYS_NS16550_COM3
225 #define CONFIG_SYS_NS16550_COM2		OMAP34XX_UART2
226 #undef CONFIG_SERIAL3
227 #define CONFIG_SERIAL2
228 #endif
229 
230 /* Provide the MACH_TYPE value the vendor kernel requires */
231 #define CONFIG_MACH_TYPE	3063
232 
233 /*-----------------------------------------------------------------------
234  * FLASH and environment organization
235  */
236 
237 /* **** PISMO SUPPORT *** */
238 
239 #define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
240 						/* on one chip */
241 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
242 
243 /*-----------------------------------------------------------------------
244  * CFI FLASH driver setup
245  */
246 /* timeout values are in ticks */
247 #define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
248 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
249 
250 /* Flash banks JFFS2 should use */
251 #define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
252 					CONFIG_SYS_MAX_NAND_DEVICE)
253 #define CONFIG_SYS_JFFS2_MEM_NAND
254 /* use flash_info[2] */
255 #define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
256 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
257 
258 #endif /* __OMAP3_CAIRO_CONFIG_H */
259