xref: /openbmc/u-boot/include/configs/omap3_cairo.h (revision 9ae63f46a387573236372b937ada34daa55b893d)
1 /*
2  * Configuration settings for the QUIPOS Cairo board.
3  *
4  * Copyright (C) DENX GmbH
5  *
6  * Author :
7  *	Albert ARIBAUD <albert.aribaud@3adev.fr>
8  *
9  * Derived from EVM  code by
10  *	Manikandan Pillai <mani.pillai@ti.com>
11  * Itself derived from Beagle Board and 3430 SDP code by
12  *	Richard Woodruff <r-woodruff2@ti.com>
13  *	Syed Mohammed Khasim <khasim@ti.com>
14  *
15  * Also derived from include/configs/omap3_beagle.h
16  *
17  * SPDX-License-Identifier:	GPL-2.0+
18  */
19 
20 #ifndef __OMAP3_CAIRO_CONFIG_H
21 #define __OMAP3_CAIRO_CONFIG_H
22 
23 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
24 
25 /*
26  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
27  * 64 bytes before this address should be set aside for u-boot.img's
28  * header. That is 0x800FFFC0--0x80100000 should not be used for any
29  * other needs.  We use this rather than the inherited defines from
30  * ti_armv7_common.h for backwards compatibility.
31  */
32 #define CONFIG_SYS_TEXT_BASE		0x80100000
33 #define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
34 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
35 #define CONFIG_SPL_BSS_MAX_SIZE		(512 << 10)	/* 512 KB */
36 #define CONFIG_SYS_SPL_MALLOC_START	0x80208000
37 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
38 
39 #define CONFIG_NAND
40 
41 #include <configs/ti_omap3_common.h>
42 
43 /*
44  * Display CPU and Board information
45  */
46 #define CONFIG_DISPLAY_CPUINFO		1
47 #define CONFIG_DISPLAY_BOARDINFO	1
48 
49 #define CONFIG_MISC_INIT_R
50 
51 #define CONFIG_REVISION_TAG		1
52 #define CONFIG_ENV_OVERWRITE
53 
54 /* Enable Multi Bus support for I2C */
55 #define CONFIG_I2C_MULTI_BUS		1
56 
57 /* Probe all devices */
58 #define CONFIG_SYS_I2C_NOPROBES		{ {0x0, 0x0} }
59 
60 #define CONFIG_NAND
61 
62 /* commands to include */
63 #define CONFIG_CMD_NAND_LOCK_UNLOCK
64 
65 /*
66  * TWL4030
67  */
68 #define CONFIG_TWL4030_LED		1
69 
70 /*
71  * Board NAND Info.
72  */
73 #define CONFIG_NAND_OMAP_GPMC
74 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
75 							/* devices */
76 /* override default CONFIG_BOOTDELAY */
77 
78 #define CONFIG_EXTRA_ENV_SETTINGS \
79 	"machid=ffffffff\0" \
80 	"fdt_high=0x87000000\0" \
81 	"baudrate=115200\0" \
82 	"fec_addr=00:50:C2:7E:90:F0\0" \
83 	"netmask=255.255.255.0\0" \
84 	"ipaddr=192.168.2.9\0" \
85 	"gateway=192.168.2.1\0" \
86 	"serverip=192.168.2.10\0" \
87 	"nfshost=192.168.2.10\0" \
88 	"stdin=serial\0" \
89 	"stdout=serial\0" \
90 	"stderr=serial\0" \
91 	"bootargs_mmc_ramdisk=mem=128M " \
92 		"console=ttyO1,115200n8 " \
93 		"root=/dev/ram0 rw " \
94 		"initrd=0x81600000,16M " \
95 		"mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
96 		"omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
97 	"mmcboot=mmc init; " \
98 		"fatload mmc 0 0x80000000 uImage; " \
99 		"fatload mmc 0 0x81600000 ramdisk.gz; " \
100 		"setenv bootargs ${bootargs_mmc_ramdisk}; " \
101 		"bootm 0x80000000\0" \
102 	"bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
103 	"root=/dev/nfs " \
104 	"nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
105 	"mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
106 	"omap_vout.vid1_static_vrfb_alloc=y\0" \
107 	"boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
108 	"bootm 0x80000000\0" \
109 	"bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
110 	"root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
111 	"omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
112 	"omapfb.rotate_type=1\0" \
113 	"boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
114 	"bootargs ${bootargs_nand}; bootm 0x80000000\0" \
115 	"ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
116 	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
117 	"i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
118 	"ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
119 	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
120 	"mw 60 09 00 1; i2c mw 60 06 10 1\0" \
121 	"ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
122 	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
123 	"i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
124 	"ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
125 	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
126 	"i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
127 	"flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
128 		"nand erase 0 20000; " \
129 		"fatload mmc 0 0x81600000 MLO; " \
130 		"nandecc hw; " \
131 		"nand write.i 0x81600000 0 20000;\0" \
132 	"flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
133 		"nand erase 80000 40000; " \
134 		"fatload mmc 0 0x81600000 u-boot.bin; " \
135 		"nandecc sw; " \
136 		"nand write.i 0x81600000 80000 40000;\0" \
137 	"flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
138 		"nand erase 280000 300000; " \
139 		"fatload mmc 0 0x81600000 uImage; " \
140 		"nandecc sw; " \
141 		"nand write.i 0x81600000 280000 300000;\0" \
142 	"flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
143 		"nandecc sw; " \
144 		"nand write.jffs2 0x680000 0xFF ${filesize}; " \
145 		"nand erase 680000 ${filesize}; " \
146 		"nand write.jffs2 81600000 680000 ${filesize};\0" \
147 	"flash_scrub=nand scrub; " \
148 		"run flash_xloader; " \
149 		"run flash_uboot; " \
150 		"run flash_kernel; " \
151 		"run flash_rootfs;\0" \
152 	"flash_all=run ledred; " \
153 		"nand erase.chip; " \
154 		"run ledorange; " \
155 		"run flash_xloader; " \
156 		"run flash_uboot; " \
157 		"run flash_kernel; " \
158 		"run flash_rootfs; " \
159 		"run ledgreen; " \
160 		"run boot_nand; \0" \
161 
162 #define CONFIG_BOOTCOMMAND \
163 	"if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
164 	"else run boot_nand; fi"
165 
166 /*
167  * OMAP3 has 12 GP timers, they can be driven by the system clock
168  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
169  * This rate is divided by a local divisor.
170  */
171 #define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
172 
173 /*-----------------------------------------------------------------------
174  * FLASH and environment organization
175  */
176 
177 /* **** PISMO SUPPORT *** */
178 #if defined(CONFIG_CMD_NAND)
179 #define CONFIG_SYS_FLASH_BASE		NAND_BASE
180 #endif
181 
182 /* Monitor at start of flash */
183 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
184 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
185 
186 #define CONFIG_ENV_IS_IN_NAND		1
187 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
188 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
189 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
190 
191 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
192 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
193 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
194 
195 #define CONFIG_OMAP3_SPI
196 
197 #define CONFIG_SYS_CACHELINE_SIZE	64
198 
199 /* Defines for SPL */
200 #define CONFIG_SPL_OMAP3_ID_NAND
201 
202 /* NAND boot config */
203 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
204 #define CONFIG_SYS_NAND_PAGE_COUNT	64
205 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
206 #define CONFIG_SYS_NAND_OOBSIZE		64
207 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
208 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
209 #define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
210 						10, 11, 12, 13}
211 #define CONFIG_SYS_NAND_ECCSIZE		512
212 #define CONFIG_SYS_NAND_ECCBYTES	3
213 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
214 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
215 /* NAND: SPL falcon mode configs */
216 #ifdef CONFIG_SPL_OS_BOOT
217 #define CONFIG_CMD_SPL_NAND_OFS		0x240000
218 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
219 #define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
220 #endif
221 
222 /* env defaults */
223 #define CONFIG_BOOTFILE			"uImage"
224 
225 /* Override OMAP3 common serial console configuration from UART3
226  * to UART2.
227  *
228  * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
229  * are needed and peripheral clocks for UART2 must be enabled in
230  * function per_clocks_enable().
231  */
232 #undef CONFIG_CONS_INDEX
233 #define CONFIG_CONS_INDEX		2
234 #ifdef CONFIG_SPL_BUILD
235 #undef CONFIG_SYS_NS16550_COM3
236 #define CONFIG_SYS_NS16550_COM2		OMAP34XX_UART2
237 #undef CONFIG_SERIAL3
238 #define CONFIG_SERIAL2
239 #endif
240 
241 /* Provide MACH_TYPE for compatibility with non-DT kernels */
242 #define MACH_TYPE_OMAP3_CAIRO	3063
243 #define CONFIG_MACH_TYPE	MACH_TYPE_OMAP3_CAIRO
244 
245 /*-----------------------------------------------------------------------
246  * FLASH and environment organization
247  */
248 
249 /* **** PISMO SUPPORT *** */
250 
251 #define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
252 						/* on one chip */
253 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
254 
255 /*-----------------------------------------------------------------------
256  * CFI FLASH driver setup
257  */
258 /* timeout values are in ticks */
259 #define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
260 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
261 
262 /* Flash banks JFFS2 should use */
263 #define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
264 					CONFIG_SYS_MAX_NAND_DEVICE)
265 #define CONFIG_SYS_JFFS2_MEM_NAND
266 /* use flash_info[2] */
267 #define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
268 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
269 
270 #endif /* __OMAP3_CAIRO_CONFIG_H */
271