1 /* 2 * Configuration settings for the QUIPOS Cairo board. 3 * 4 * Copyright (C) DENX GmbH 5 * 6 * Author : 7 * Albert ARIBAUD <albert.aribaud@3adev.fr> 8 * 9 * Derived from EVM code by 10 * Manikandan Pillai <mani.pillai@ti.com> 11 * Itself derived from Beagle Board and 3430 SDP code by 12 * Richard Woodruff <r-woodruff2@ti.com> 13 * Syed Mohammed Khasim <khasim@ti.com> 14 * 15 * Also derived from include/configs/omap3_beagle.h 16 * 17 * SPDX-License-Identifier: GPL-2.0+ 18 */ 19 20 #ifndef __OMAP3_CAIRO_CONFIG_H 21 #define __OMAP3_CAIRO_CONFIG_H 22 23 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 24 25 /* 26 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 27 * 64 bytes before this address should be set aside for u-boot.img's 28 * header. That is 0x800FFFC0--0x80100000 should not be used for any 29 * other needs. We use this rather than the inherited defines from 30 * ti_armv7_common.h for backwards compatibility. 31 */ 32 #define CONFIG_SYS_TEXT_BASE 0x80100000 33 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 34 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 35 #define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */ 36 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 37 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 38 39 #define CONFIG_NAND 40 41 #include <configs/ti_omap3_common.h> 42 43 /* 44 * Display CPU and Board information 45 */ 46 #define CONFIG_DISPLAY_CPUINFO 1 47 #define CONFIG_DISPLAY_BOARDINFO 1 48 49 #define CONFIG_MISC_INIT_R 50 51 #define CONFIG_REVISION_TAG 1 52 #define CONFIG_ENV_OVERWRITE 53 54 /* Enable Multi Bus support for I2C */ 55 #define CONFIG_I2C_MULTI_BUS 1 56 57 /* Probe all devices */ 58 #define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} } 59 60 #define CONFIG_NAND 61 62 /* commands to include */ 63 #include <config_cmd_default.h> 64 65 #define CONFIG_CMD_SETEXPR /* Evaluate expressions */ 66 #define CONFIG_CMD_NAND_LOCK_UNLOCK 67 68 /* Disable some commands */ 69 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 70 #undef CONFIG_CMD_IMI /* iminfo */ 71 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 72 73 /* 74 * TWL4030 75 */ 76 #define CONFIG_TWL4030_LED 1 77 78 /* 79 * Board NAND Info. 80 */ 81 #define CONFIG_SYS_NAND_QUIET_TEST 1 82 #define CONFIG_NAND_OMAP_GPMC 83 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 84 /* devices */ 85 /* override default CONFIG_BOOTDELAY */ 86 #undef CONFIG_BOOTDELAY 87 #define CONFIG_BOOTDELAY 0 88 89 #define CONFIG_EXTRA_ENV_SETTINGS \ 90 "machid=ffffffff\0" \ 91 "fdt_high=0x87000000\0" \ 92 "baudrate=115200\0" \ 93 "fec_addr=00:50:C2:7E:90:F0\0" \ 94 "netmask=255.255.255.0\0" \ 95 "ipaddr=192.168.2.9\0" \ 96 "gateway=192.168.2.1\0" \ 97 "serverip=192.168.2.10\0" \ 98 "nfshost=192.168.2.10\0" \ 99 "stdin=serial\0" \ 100 "stdout=serial\0" \ 101 "stderr=serial\0" \ 102 "bootargs_mmc_ramdisk=mem=128M " \ 103 "console=ttyO1,115200n8 " \ 104 "root=/dev/ram0 rw " \ 105 "initrd=0x81600000,16M " \ 106 "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \ 107 "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \ 108 "mmcboot=mmc init; " \ 109 "fatload mmc 0 0x80000000 uImage; " \ 110 "fatload mmc 0 0x81600000 ramdisk.gz; " \ 111 "setenv bootargs ${bootargs_mmc_ramdisk}; " \ 112 "bootm 0x80000000\0" \ 113 "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \ 114 "root=/dev/nfs " \ 115 "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \ 116 "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \ 117 "omap_vout.vid1_static_vrfb_alloc=y\0" \ 118 "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \ 119 "bootm 0x80000000\0" \ 120 "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \ 121 "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \ 122 "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \ 123 "omapfb.rotate_type=1\0" \ 124 "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \ 125 "bootargs ${bootargs_nand}; bootm 0x80000000\0" \ 126 "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ 127 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ 128 "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \ 129 "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ 130 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \ 131 "mw 60 09 00 1; i2c mw 60 06 10 1\0" \ 132 "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ 133 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ 134 "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \ 135 "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ 136 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ 137 "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \ 138 "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \ 139 "nand erase 0 20000; " \ 140 "fatload mmc 0 0x81600000 MLO; " \ 141 "nandecc hw; " \ 142 "nand write.i 0x81600000 0 20000;\0" \ 143 "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \ 144 "nand erase 80000 40000; " \ 145 "fatload mmc 0 0x81600000 u-boot.bin; " \ 146 "nandecc sw; " \ 147 "nand write.i 0x81600000 80000 40000;\0" \ 148 "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \ 149 "nand erase 280000 300000; " \ 150 "fatload mmc 0 0x81600000 uImage; " \ 151 "nandecc sw; " \ 152 "nand write.i 0x81600000 280000 300000;\0" \ 153 "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \ 154 "nandecc sw; " \ 155 "nand write.jffs2 0x680000 0xFF ${filesize}; " \ 156 "nand erase 680000 ${filesize}; " \ 157 "nand write.jffs2 81600000 680000 ${filesize};\0" \ 158 "flash_scrub=nand scrub; " \ 159 "run flash_xloader; " \ 160 "run flash_uboot; " \ 161 "run flash_kernel; " \ 162 "run flash_rootfs;\0" \ 163 "flash_all=run ledred; " \ 164 "nand erase.chip; " \ 165 "run ledorange; " \ 166 "run flash_xloader; " \ 167 "run flash_uboot; " \ 168 "run flash_kernel; " \ 169 "run flash_rootfs; " \ 170 "run ledgreen; " \ 171 "run boot_nand; \0" \ 172 173 #define CONFIG_BOOTCOMMAND \ 174 "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \ 175 "else run boot_nand; fi" 176 177 /* 178 * OMAP3 has 12 GP timers, they can be driven by the system clock 179 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 180 * This rate is divided by a local divisor. 181 */ 182 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 183 184 /*----------------------------------------------------------------------- 185 * FLASH and environment organization 186 */ 187 188 /* **** PISMO SUPPORT *** */ 189 #if defined(CONFIG_CMD_NAND) 190 #define CONFIG_SYS_FLASH_BASE NAND_BASE 191 #endif 192 193 /* Monitor at start of flash */ 194 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 195 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 196 197 #define CONFIG_ENV_IS_IN_NAND 1 198 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 199 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 200 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 201 202 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 203 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 204 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 205 206 #define CONFIG_OMAP3_SPI 207 208 #define CONFIG_SYS_CACHELINE_SIZE 64 209 210 /* Defines for SPL */ 211 #define CONFIG_SPL_OMAP3_ID_NAND 212 213 /* NAND boot config */ 214 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 215 #define CONFIG_SYS_NAND_PAGE_COUNT 64 216 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 217 #define CONFIG_SYS_NAND_OOBSIZE 64 218 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 219 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 220 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 221 10, 11, 12, 13} 222 #define CONFIG_SYS_NAND_ECCSIZE 512 223 #define CONFIG_SYS_NAND_ECCBYTES 3 224 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 225 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 226 /* NAND: SPL falcon mode configs */ 227 #ifdef CONFIG_SPL_OS_BOOT 228 #define CONFIG_CMD_SPL_NAND_OFS 0x240000 229 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 230 #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 231 #endif 232 233 /* env defaults */ 234 #define CONFIG_BOOTFILE "uImage" 235 236 /* Override OMAP3 common serial console configuration from UART3 237 * to UART2. 238 * 239 * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3) 240 * are needed and peripheral clocks for UART2 must be enabled in 241 * function per_clocks_enable(). 242 */ 243 #undef CONFIG_CONS_INDEX 244 #define CONFIG_CONS_INDEX 2 245 #ifdef CONFIG_SPL_BUILD 246 #undef CONFIG_SYS_NS16550_COM3 247 #define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2 248 #undef CONFIG_SERIAL3 249 #define CONFIG_SERIAL2 250 #endif 251 252 /* Keep old prompt in case some existing script depends on it */ 253 #undef CONFIG_SYS_PROMPT 254 #define CONFIG_SYS_PROMPT "Cairo # " 255 256 /* Provide MACH_TYPE for compatibility with non-DT kernels */ 257 #define MACH_TYPE_OMAP3_CAIRO 3063 258 #define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CAIRO 259 260 /*----------------------------------------------------------------------- 261 * FLASH and environment organization 262 */ 263 264 /* **** PISMO SUPPORT *** */ 265 266 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 267 /* on one chip */ 268 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 269 270 /*----------------------------------------------------------------------- 271 * CFI FLASH driver setup 272 */ 273 /* timeout values are in ticks */ 274 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 275 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 276 277 /* Flash banks JFFS2 should use */ 278 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 279 CONFIG_SYS_MAX_NAND_DEVICE) 280 #define CONFIG_SYS_JFFS2_MEM_NAND 281 /* use flash_info[2] */ 282 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 283 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 284 285 #endif /* __OMAP3_CAIRO_CONFIG_H */ 286