1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Configuration settings for the QUIPOS Cairo board.
4  *
5  * Copyright (C) DENX GmbH
6  *
7  * Author :
8  *	Albert ARIBAUD <albert.aribaud@3adev.fr>
9  *
10  * Derived from EVM  code by
11  *	Manikandan Pillai <mani.pillai@ti.com>
12  * Itself derived from Beagle Board and 3430 SDP code by
13  *	Richard Woodruff <r-woodruff2@ti.com>
14  *	Syed Mohammed Khasim <khasim@ti.com>
15  *
16  * Also derived from include/configs/omap3_beagle.h
17  */
18 
19 #ifndef __OMAP3_CAIRO_CONFIG_H
20 #define __OMAP3_CAIRO_CONFIG_H
21 
22 /*
23  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
24  * 64 bytes before this address should be set aside for u-boot.img's
25  * header. That is 0x800FFFC0--0x80100000 should not be used for any
26  * other needs.  We use this rather than the inherited defines from
27  * ti_armv7_common.h for backwards compatibility.
28  */
29 #define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
30 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
31 #define CONFIG_SPL_BSS_MAX_SIZE		(512 << 10)	/* 512 KB */
32 #define CONFIG_SYS_SPL_MALLOC_START	0x80208000
33 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
34 
35 #include <configs/ti_omap3_common.h>
36 
37 #define CONFIG_REVISION_TAG		1
38 #define CONFIG_ENV_OVERWRITE
39 
40 /* Enable Multi Bus support for I2C */
41 #define CONFIG_I2C_MULTI_BUS		1
42 
43 /* Probe all devices */
44 #define CONFIG_SYS_I2C_NOPROBES		{ {0x0, 0x0} }
45 
46 /*
47  * TWL4030
48  */
49 
50 /*
51  * Board NAND Info.
52  */
53 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
54 							/* devices */
55 #define CONFIG_EXTRA_ENV_SETTINGS \
56 	"machid=ffffffff\0" \
57 	"fdt_high=0x87000000\0" \
58 	"baudrate=115200\0" \
59 	"fec_addr=00:50:C2:7E:90:F0\0" \
60 	"netmask=255.255.255.0\0" \
61 	"ipaddr=192.168.2.9\0" \
62 	"gateway=192.168.2.1\0" \
63 	"serverip=192.168.2.10\0" \
64 	"nfshost=192.168.2.10\0" \
65 	"stdin=serial\0" \
66 	"stdout=serial\0" \
67 	"stderr=serial\0" \
68 	"bootargs_mmc_ramdisk=mem=128M " \
69 		"console=ttyO1,115200n8 " \
70 		"root=/dev/ram0 rw " \
71 		"initrd=0x81600000,16M " \
72 		"mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
73 		"omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
74 	"mmcboot=mmc init; " \
75 		"fatload mmc 0 0x80000000 uImage; " \
76 		"fatload mmc 0 0x81600000 ramdisk.gz; " \
77 		"setenv bootargs ${bootargs_mmc_ramdisk}; " \
78 		"bootm 0x80000000\0" \
79 	"bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
80 	"root=/dev/nfs " \
81 	"nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
82 	"mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
83 	"omap_vout.vid1_static_vrfb_alloc=y\0" \
84 	"boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
85 	"bootm 0x80000000\0" \
86 	"bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
87 	"root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
88 	"omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
89 	"omapfb.rotate_type=1\0" \
90 	"boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
91 	"bootargs ${bootargs_nand}; bootm 0x80000000\0" \
92 	"ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
93 	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
94 	"i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
95 	"ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
96 	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
97 	"mw 60 09 00 1; i2c mw 60 06 10 1\0" \
98 	"ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
99 	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
100 	"i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
101 	"ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
102 	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
103 	"i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
104 	"flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
105 		"nand erase 0 20000; " \
106 		"fatload mmc 0 0x81600000 MLO; " \
107 		"nandecc hw; " \
108 		"nand write.i 0x81600000 0 20000;\0" \
109 	"flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
110 		"nand erase 80000 40000; " \
111 		"fatload mmc 0 0x81600000 u-boot.bin; " \
112 		"nandecc sw; " \
113 		"nand write.i 0x81600000 80000 40000;\0" \
114 	"flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
115 		"nand erase 280000 300000; " \
116 		"fatload mmc 0 0x81600000 uImage; " \
117 		"nandecc sw; " \
118 		"nand write.i 0x81600000 280000 300000;\0" \
119 	"flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
120 		"nandecc sw; " \
121 		"nand write.jffs2 0x680000 0xFF ${filesize}; " \
122 		"nand erase 680000 ${filesize}; " \
123 		"nand write.jffs2 81600000 680000 ${filesize};\0" \
124 	"flash_scrub=nand scrub; " \
125 		"run flash_xloader; " \
126 		"run flash_uboot; " \
127 		"run flash_kernel; " \
128 		"run flash_rootfs;\0" \
129 	"flash_all=run ledred; " \
130 		"nand erase.chip; " \
131 		"run ledorange; " \
132 		"run flash_xloader; " \
133 		"run flash_uboot; " \
134 		"run flash_kernel; " \
135 		"run flash_rootfs; " \
136 		"run ledgreen; " \
137 		"run boot_nand; \0" \
138 
139 #define CONFIG_BOOTCOMMAND \
140 	"if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
141 	"else run boot_nand; fi"
142 
143 /*
144  * OMAP3 has 12 GP timers, they can be driven by the system clock
145  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
146  * This rate is divided by a local divisor.
147  */
148 #define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
149 
150 /*-----------------------------------------------------------------------
151  * FLASH and environment organization
152  */
153 
154 /* **** PISMO SUPPORT *** */
155 #if defined(CONFIG_CMD_NAND)
156 #define CONFIG_SYS_FLASH_BASE		NAND_BASE
157 #endif
158 
159 /* Monitor at start of flash */
160 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
161 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
162 
163 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
164 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
165 
166 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
167 #define CONFIG_ENV_OFFSET		0x260000
168 #define CONFIG_ENV_ADDR			0x260000
169 
170 /* Defines for SPL */
171 
172 /* NAND boot config */
173 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
174 #define CONFIG_SYS_NAND_PAGE_COUNT	64
175 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
176 #define CONFIG_SYS_NAND_OOBSIZE		64
177 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
178 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
179 #define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
180 						10, 11, 12, 13}
181 #define CONFIG_SYS_NAND_ECCSIZE		512
182 #define CONFIG_SYS_NAND_ECCBYTES	3
183 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
184 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
185 /* NAND: SPL falcon mode configs */
186 #ifdef CONFIG_SPL_OS_BOOT
187 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
188 #endif
189 
190 /* env defaults */
191 #define CONFIG_BOOTFILE			"uImage"
192 
193 /* Override OMAP3 common serial console configuration from UART3
194  * to UART2.
195  *
196  * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
197  * are needed and peripheral clocks for UART2 must be enabled in
198  * function per_clocks_enable().
199  */
200 #ifdef CONFIG_SPL_BUILD
201 #endif
202 
203 /* Provide the MACH_TYPE value the vendor kernel requires */
204 #define CONFIG_MACH_TYPE	3063
205 
206 /*-----------------------------------------------------------------------
207  * FLASH and environment organization
208  */
209 
210 /* **** PISMO SUPPORT *** */
211 
212 #define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
213 						/* on one chip */
214 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
215 
216 /*-----------------------------------------------------------------------
217  * CFI FLASH driver setup
218  */
219 /* timeout values are in ticks */
220 #define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
221 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
222 
223 /* Flash banks JFFS2 should use */
224 #define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
225 					CONFIG_SYS_MAX_NAND_DEVICE)
226 #define CONFIG_SYS_JFFS2_MEM_NAND
227 /* use flash_info[2] */
228 #define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
229 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
230 
231 #endif /* __OMAP3_CAIRO_CONFIG_H */
232