1 /* 2 * Configuration settings for the QUIPOS Cairo board. 3 * 4 * Copyright (C) DENX GmbH 5 * 6 * Author : 7 * Albert ARIBAUD <albert.aribaud@3adev.fr> 8 * 9 * Derived from EVM code by 10 * Manikandan Pillai <mani.pillai@ti.com> 11 * Itself derived from Beagle Board and 3430 SDP code by 12 * Richard Woodruff <r-woodruff2@ti.com> 13 * Syed Mohammed Khasim <khasim@ti.com> 14 * 15 * Also derived from include/configs/omap3_beagle.h 16 * 17 * SPDX-License-Identifier: GPL-2.0+ 18 */ 19 20 #ifndef __OMAP3_CAIRO_CONFIG_H 21 #define __OMAP3_CAIRO_CONFIG_H 22 23 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 24 25 /* 26 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 27 * 64 bytes before this address should be set aside for u-boot.img's 28 * header. That is 0x800FFFC0--0x80100000 should not be used for any 29 * other needs. We use this rather than the inherited defines from 30 * ti_armv7_common.h for backwards compatibility. 31 */ 32 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 33 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 34 #define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */ 35 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 36 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 37 38 #include <configs/ti_omap3_common.h> 39 40 #define CONFIG_MISC_INIT_R 41 42 #define CONFIG_REVISION_TAG 1 43 #define CONFIG_ENV_OVERWRITE 44 45 /* Enable Multi Bus support for I2C */ 46 #define CONFIG_I2C_MULTI_BUS 1 47 48 /* Probe all devices */ 49 #define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} } 50 51 /* 52 * TWL4030 53 */ 54 #define CONFIG_TWL4030_LED 1 55 56 /* 57 * Board NAND Info. 58 */ 59 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 60 /* devices */ 61 #define CONFIG_EXTRA_ENV_SETTINGS \ 62 "machid=ffffffff\0" \ 63 "fdt_high=0x87000000\0" \ 64 "baudrate=115200\0" \ 65 "fec_addr=00:50:C2:7E:90:F0\0" \ 66 "netmask=255.255.255.0\0" \ 67 "ipaddr=192.168.2.9\0" \ 68 "gateway=192.168.2.1\0" \ 69 "serverip=192.168.2.10\0" \ 70 "nfshost=192.168.2.10\0" \ 71 "stdin=serial\0" \ 72 "stdout=serial\0" \ 73 "stderr=serial\0" \ 74 "bootargs_mmc_ramdisk=mem=128M " \ 75 "console=ttyO1,115200n8 " \ 76 "root=/dev/ram0 rw " \ 77 "initrd=0x81600000,16M " \ 78 "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \ 79 "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \ 80 "mmcboot=mmc init; " \ 81 "fatload mmc 0 0x80000000 uImage; " \ 82 "fatload mmc 0 0x81600000 ramdisk.gz; " \ 83 "setenv bootargs ${bootargs_mmc_ramdisk}; " \ 84 "bootm 0x80000000\0" \ 85 "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \ 86 "root=/dev/nfs " \ 87 "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \ 88 "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \ 89 "omap_vout.vid1_static_vrfb_alloc=y\0" \ 90 "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \ 91 "bootm 0x80000000\0" \ 92 "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \ 93 "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \ 94 "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \ 95 "omapfb.rotate_type=1\0" \ 96 "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \ 97 "bootargs ${bootargs_nand}; bootm 0x80000000\0" \ 98 "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ 99 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ 100 "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \ 101 "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ 102 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \ 103 "mw 60 09 00 1; i2c mw 60 06 10 1\0" \ 104 "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ 105 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ 106 "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \ 107 "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ 108 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ 109 "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \ 110 "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \ 111 "nand erase 0 20000; " \ 112 "fatload mmc 0 0x81600000 MLO; " \ 113 "nandecc hw; " \ 114 "nand write.i 0x81600000 0 20000;\0" \ 115 "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \ 116 "nand erase 80000 40000; " \ 117 "fatload mmc 0 0x81600000 u-boot.bin; " \ 118 "nandecc sw; " \ 119 "nand write.i 0x81600000 80000 40000;\0" \ 120 "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \ 121 "nand erase 280000 300000; " \ 122 "fatload mmc 0 0x81600000 uImage; " \ 123 "nandecc sw; " \ 124 "nand write.i 0x81600000 280000 300000;\0" \ 125 "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \ 126 "nandecc sw; " \ 127 "nand write.jffs2 0x680000 0xFF ${filesize}; " \ 128 "nand erase 680000 ${filesize}; " \ 129 "nand write.jffs2 81600000 680000 ${filesize};\0" \ 130 "flash_scrub=nand scrub; " \ 131 "run flash_xloader; " \ 132 "run flash_uboot; " \ 133 "run flash_kernel; " \ 134 "run flash_rootfs;\0" \ 135 "flash_all=run ledred; " \ 136 "nand erase.chip; " \ 137 "run ledorange; " \ 138 "run flash_xloader; " \ 139 "run flash_uboot; " \ 140 "run flash_kernel; " \ 141 "run flash_rootfs; " \ 142 "run ledgreen; " \ 143 "run boot_nand; \0" \ 144 145 #define CONFIG_BOOTCOMMAND \ 146 "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \ 147 "else run boot_nand; fi" 148 149 /* 150 * OMAP3 has 12 GP timers, they can be driven by the system clock 151 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 152 * This rate is divided by a local divisor. 153 */ 154 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 155 156 /*----------------------------------------------------------------------- 157 * FLASH and environment organization 158 */ 159 160 /* **** PISMO SUPPORT *** */ 161 #if defined(CONFIG_CMD_NAND) 162 #define CONFIG_SYS_FLASH_BASE NAND_BASE 163 #endif 164 165 /* Monitor at start of flash */ 166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 167 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 168 169 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 170 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 171 172 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 173 #define CONFIG_ENV_OFFSET 0x260000 174 #define CONFIG_ENV_ADDR 0x260000 175 176 /* Defines for SPL */ 177 178 /* NAND boot config */ 179 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 180 #define CONFIG_SYS_NAND_PAGE_COUNT 64 181 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 182 #define CONFIG_SYS_NAND_OOBSIZE 64 183 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 184 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 185 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 186 10, 11, 12, 13} 187 #define CONFIG_SYS_NAND_ECCSIZE 512 188 #define CONFIG_SYS_NAND_ECCBYTES 3 189 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 190 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 191 /* NAND: SPL falcon mode configs */ 192 #ifdef CONFIG_SPL_OS_BOOT 193 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 194 #endif 195 196 /* env defaults */ 197 #define CONFIG_BOOTFILE "uImage" 198 199 /* Override OMAP3 common serial console configuration from UART3 200 * to UART2. 201 * 202 * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3) 203 * are needed and peripheral clocks for UART2 must be enabled in 204 * function per_clocks_enable(). 205 */ 206 #ifdef CONFIG_SPL_BUILD 207 #undef CONFIG_SYS_NS16550_COM3 208 #define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2 209 #undef CONFIG_SERIAL3 210 #define CONFIG_SERIAL2 211 #endif 212 213 /* Provide the MACH_TYPE value the vendor kernel requires */ 214 #define CONFIG_MACH_TYPE 3063 215 216 /*----------------------------------------------------------------------- 217 * FLASH and environment organization 218 */ 219 220 /* **** PISMO SUPPORT *** */ 221 222 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 223 /* on one chip */ 224 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 225 226 /*----------------------------------------------------------------------- 227 * CFI FLASH driver setup 228 */ 229 /* timeout values are in ticks */ 230 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 231 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 232 233 /* Flash banks JFFS2 should use */ 234 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 235 CONFIG_SYS_MAX_NAND_DEVICE) 236 #define CONFIG_SYS_JFFS2_MEM_NAND 237 /* use flash_info[2] */ 238 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 239 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 240 241 #endif /* __OMAP3_CAIRO_CONFIG_H */ 242