1 /*
2  * Configuration settings for the QUIPOS Cairo board.
3  *
4  * Copyright (C) DENX GmbH
5  *
6  * Author :
7  *	Albert ARIBAUD <albert.aribaud@3adev.fr>
8  *
9  * Derived from EVM  code by
10  *	Manikandan Pillai <mani.pillai@ti.com>
11  * Itself derived from Beagle Board and 3430 SDP code by
12  *	Richard Woodruff <r-woodruff2@ti.com>
13  *	Syed Mohammed Khasim <khasim@ti.com>
14  *
15  * Also derived from include/configs/omap3_beagle.h
16  *
17  * SPDX-License-Identifier:	GPL-2.0+
18  */
19 
20 #ifndef __OMAP3_CAIRO_CONFIG_H
21 #define __OMAP3_CAIRO_CONFIG_H
22 
23 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
24 
25 /*
26  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
27  * 64 bytes before this address should be set aside for u-boot.img's
28  * header. That is 0x800FFFC0--0x80100000 should not be used for any
29  * other needs.  We use this rather than the inherited defines from
30  * ti_armv7_common.h for backwards compatibility.
31  */
32 #define CONFIG_SYS_TEXT_BASE		0x80100000
33 #define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
34 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
35 #define CONFIG_SPL_BSS_MAX_SIZE		(512 << 10)	/* 512 KB */
36 #define CONFIG_SYS_SPL_MALLOC_START	0x80208000
37 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
38 
39 #define CONFIG_NAND
40 
41 #include <configs/ti_omap3_common.h>
42 
43 /*
44  * Display CPU and Board information
45  */
46 #define CONFIG_DISPLAY_CPUINFO		1
47 #define CONFIG_DISPLAY_BOARDINFO	1
48 
49 #define CONFIG_MISC_INIT_R
50 
51 #define CONFIG_REVISION_TAG		1
52 #define CONFIG_ENV_OVERWRITE
53 
54 /* Enable Multi Bus support for I2C */
55 #define CONFIG_I2C_MULTI_BUS		1
56 
57 /* Probe all devices */
58 #define CONFIG_SYS_I2C_NOPROBES		{ {0x0, 0x0} }
59 
60 #define CONFIG_NAND
61 
62 /* commands to include */
63 #define CONFIG_CMD_NAND_LOCK_UNLOCK
64 
65 /*
66  * TWL4030
67  */
68 #define CONFIG_TWL4030_LED		1
69 
70 /*
71  * Board NAND Info.
72  */
73 #define CONFIG_SYS_NAND_QUIET_TEST	1
74 #define CONFIG_NAND_OMAP_GPMC
75 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
76 							/* devices */
77 /* override default CONFIG_BOOTDELAY */
78 #undef CONFIG_BOOTDELAY
79 #define CONFIG_BOOTDELAY	0
80 
81 #define CONFIG_EXTRA_ENV_SETTINGS \
82 	"machid=ffffffff\0" \
83 	"fdt_high=0x87000000\0" \
84 	"baudrate=115200\0" \
85 	"fec_addr=00:50:C2:7E:90:F0\0" \
86 	"netmask=255.255.255.0\0" \
87 	"ipaddr=192.168.2.9\0" \
88 	"gateway=192.168.2.1\0" \
89 	"serverip=192.168.2.10\0" \
90 	"nfshost=192.168.2.10\0" \
91 	"stdin=serial\0" \
92 	"stdout=serial\0" \
93 	"stderr=serial\0" \
94 	"bootargs_mmc_ramdisk=mem=128M " \
95 		"console=ttyO1,115200n8 " \
96 		"root=/dev/ram0 rw " \
97 		"initrd=0x81600000,16M " \
98 		"mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
99 		"omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
100 	"mmcboot=mmc init; " \
101 		"fatload mmc 0 0x80000000 uImage; " \
102 		"fatload mmc 0 0x81600000 ramdisk.gz; " \
103 		"setenv bootargs ${bootargs_mmc_ramdisk}; " \
104 		"bootm 0x80000000\0" \
105 	"bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
106 	"root=/dev/nfs " \
107 	"nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
108 	"mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
109 	"omap_vout.vid1_static_vrfb_alloc=y\0" \
110 	"boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
111 	"bootm 0x80000000\0" \
112 	"bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
113 	"root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
114 	"omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
115 	"omapfb.rotate_type=1\0" \
116 	"boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
117 	"bootargs ${bootargs_nand}; bootm 0x80000000\0" \
118 	"ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
119 	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
120 	"i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
121 	"ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
122 	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
123 	"mw 60 09 00 1; i2c mw 60 06 10 1\0" \
124 	"ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
125 	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
126 	"i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
127 	"ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
128 	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
129 	"i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
130 	"flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
131 		"nand erase 0 20000; " \
132 		"fatload mmc 0 0x81600000 MLO; " \
133 		"nandecc hw; " \
134 		"nand write.i 0x81600000 0 20000;\0" \
135 	"flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
136 		"nand erase 80000 40000; " \
137 		"fatload mmc 0 0x81600000 u-boot.bin; " \
138 		"nandecc sw; " \
139 		"nand write.i 0x81600000 80000 40000;\0" \
140 	"flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
141 		"nand erase 280000 300000; " \
142 		"fatload mmc 0 0x81600000 uImage; " \
143 		"nandecc sw; " \
144 		"nand write.i 0x81600000 280000 300000;\0" \
145 	"flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
146 		"nandecc sw; " \
147 		"nand write.jffs2 0x680000 0xFF ${filesize}; " \
148 		"nand erase 680000 ${filesize}; " \
149 		"nand write.jffs2 81600000 680000 ${filesize};\0" \
150 	"flash_scrub=nand scrub; " \
151 		"run flash_xloader; " \
152 		"run flash_uboot; " \
153 		"run flash_kernel; " \
154 		"run flash_rootfs;\0" \
155 	"flash_all=run ledred; " \
156 		"nand erase.chip; " \
157 		"run ledorange; " \
158 		"run flash_xloader; " \
159 		"run flash_uboot; " \
160 		"run flash_kernel; " \
161 		"run flash_rootfs; " \
162 		"run ledgreen; " \
163 		"run boot_nand; \0" \
164 
165 #define CONFIG_BOOTCOMMAND \
166 	"if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
167 	"else run boot_nand; fi"
168 
169 /*
170  * OMAP3 has 12 GP timers, they can be driven by the system clock
171  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
172  * This rate is divided by a local divisor.
173  */
174 #define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
175 
176 /*-----------------------------------------------------------------------
177  * FLASH and environment organization
178  */
179 
180 /* **** PISMO SUPPORT *** */
181 #if defined(CONFIG_CMD_NAND)
182 #define CONFIG_SYS_FLASH_BASE		NAND_BASE
183 #endif
184 
185 /* Monitor at start of flash */
186 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
187 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
188 
189 #define CONFIG_ENV_IS_IN_NAND		1
190 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
191 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
192 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
193 
194 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
195 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
196 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
197 
198 #define CONFIG_OMAP3_SPI
199 
200 #define CONFIG_SYS_CACHELINE_SIZE	64
201 
202 /* Defines for SPL */
203 #define CONFIG_SPL_OMAP3_ID_NAND
204 
205 /* NAND boot config */
206 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
207 #define CONFIG_SYS_NAND_PAGE_COUNT	64
208 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
209 #define CONFIG_SYS_NAND_OOBSIZE		64
210 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
211 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
212 #define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
213 						10, 11, 12, 13}
214 #define CONFIG_SYS_NAND_ECCSIZE		512
215 #define CONFIG_SYS_NAND_ECCBYTES	3
216 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
217 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
218 /* NAND: SPL falcon mode configs */
219 #ifdef CONFIG_SPL_OS_BOOT
220 #define CONFIG_CMD_SPL_NAND_OFS		0x240000
221 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
222 #define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
223 #endif
224 
225 /* env defaults */
226 #define CONFIG_BOOTFILE			"uImage"
227 
228 /* Override OMAP3 common serial console configuration from UART3
229  * to UART2.
230  *
231  * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
232  * are needed and peripheral clocks for UART2 must be enabled in
233  * function per_clocks_enable().
234  */
235 #undef CONFIG_CONS_INDEX
236 #define CONFIG_CONS_INDEX		2
237 #ifdef CONFIG_SPL_BUILD
238 #undef CONFIG_SYS_NS16550_COM3
239 #define CONFIG_SYS_NS16550_COM2		OMAP34XX_UART2
240 #undef CONFIG_SERIAL3
241 #define CONFIG_SERIAL2
242 #endif
243 
244 /* Provide MACH_TYPE for compatibility with non-DT kernels */
245 #define MACH_TYPE_OMAP3_CAIRO	3063
246 #define CONFIG_MACH_TYPE	MACH_TYPE_OMAP3_CAIRO
247 
248 /*-----------------------------------------------------------------------
249  * FLASH and environment organization
250  */
251 
252 /* **** PISMO SUPPORT *** */
253 
254 #define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
255 						/* on one chip */
256 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
257 
258 /*-----------------------------------------------------------------------
259  * CFI FLASH driver setup
260  */
261 /* timeout values are in ticks */
262 #define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
263 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
264 
265 /* Flash banks JFFS2 should use */
266 #define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
267 					CONFIG_SYS_MAX_NAND_DEVICE)
268 #define CONFIG_SYS_JFFS2_MEM_NAND
269 /* use flash_info[2] */
270 #define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
271 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
272 
273 #endif /* __OMAP3_CAIRO_CONFIG_H */
274