1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * Configuration settings for the TI OMAP3530 Beagle board. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 #include <asm/sizes.h> 31 32 /* 33 * High Level Configuration Options 34 */ 35 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ 36 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 37 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 38 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 39 #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ 40 41 #include <asm/arch/cpu.h> /* get chip and board defs */ 42 #include <asm/arch/omap3.h> 43 44 /* Clock Defines */ 45 #define V_OSCK 26000000 /* Clock output from T2 */ 46 #define V_SCLK (V_OSCK >> 1) 47 48 #undef CONFIG_USE_IRQ /* no support for IRQs */ 49 #define CONFIG_MISC_INIT_R 50 51 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 52 #define CONFIG_SETUP_MEMORY_TAGS 1 53 #define CONFIG_INITRD_TAG 1 54 #define CONFIG_REVISION_TAG 1 55 56 /* 57 * Size of malloc() pool 58 */ 59 #define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ 60 /* Sector */ 61 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) 62 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ 63 /* initial data */ 64 65 /* 66 * Hardware drivers 67 */ 68 69 /* 70 * NS16550 Configuration 71 */ 72 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 73 74 #define CONFIG_SYS_NS16550 75 #define CONFIG_SYS_NS16550_SERIAL 76 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 77 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 78 79 /* 80 * select serial console configuration 81 */ 82 #define CONFIG_CONS_INDEX 3 83 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 84 #define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */ 85 86 /* allow to overwrite serial and ethaddr */ 87 #define CONFIG_ENV_OVERWRITE 88 #define CONFIG_BAUDRATE 115200 89 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 90 115200} 91 #define CONFIG_MMC 1 92 #define CONFIG_OMAP3_MMC 1 93 #define CONFIG_DOS_PARTITION 1 94 95 /* commands to include */ 96 #include <config_cmd_default.h> 97 98 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 99 #define CONFIG_CMD_FAT /* FAT support */ 100 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 101 102 #define CONFIG_CMD_I2C /* I2C serial bus support */ 103 #define CONFIG_CMD_MMC /* MMC support */ 104 #define CONFIG_CMD_NAND /* NAND support */ 105 106 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 107 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 108 #undef CONFIG_CMD_IMI /* iminfo */ 109 #undef CONFIG_CMD_IMLS /* List all found images */ 110 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 111 #undef CONFIG_CMD_NFS /* NFS support */ 112 113 #define CONFIG_SYS_NO_FLASH 114 #define CONFIG_SYS_I2C_SPEED 100000 115 #define CONFIG_SYS_I2C_SLAVE 1 116 #define CONFIG_SYS_I2C_BUS 0 117 #define CONFIG_SYS_I2C_BUS_SELECT 1 118 #define CONFIG_DRIVER_OMAP34XX_I2C 1 119 120 /* 121 * Board NAND Info. 122 */ 123 #define CONFIG_NAND_OMAP_GPMC 124 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 125 /* to access nand */ 126 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 127 /* to access nand at */ 128 /* CS0 */ 129 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 130 131 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 132 /* devices */ 133 #define SECTORSIZE 512 134 135 #define NAND_ALLOW_ERASE_ALL 136 #define ADDR_COLUMN 1 137 #define ADDR_PAGE 2 138 #define ADDR_COLUMN_PAGE 3 139 140 #define NAND_ChipID_UNKNOWN 0x00 141 #define NAND_MAX_FLOORS 1 142 #define NAND_MAX_CHIPS 1 143 #define NAND_NO_RB 1 144 #define CONFIG_SYS_NAND_WP 145 146 #define CONFIG_JFFS2_NAND 147 /* nand device jffs2 lives on */ 148 #define CONFIG_JFFS2_DEV "nand0" 149 /* start of jffs2 partition */ 150 #define CONFIG_JFFS2_PART_OFFSET 0x680000 151 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 152 /* partition */ 153 154 /* Environment information */ 155 #define CONFIG_BOOTDELAY 10 156 157 #define CONFIG_EXTRA_ENV_SETTINGS \ 158 "loadaddr=0x82000000\0" \ 159 "console=ttyS2,115200n8\0" \ 160 "videomode=1024x768@60,vxres=1024,vyres=768\0" \ 161 "videospec=omapfb:vram:2M,vram:4M\0" \ 162 "mmcargs=setenv bootargs console=${console} " \ 163 "video=${videospec},mode:${videomode} " \ 164 "root=/dev/mmcblk0p2 rw " \ 165 "rootfstype=ext3 rootwait\0" \ 166 "nandargs=setenv bootargs console=${console} " \ 167 "video=${videospec},mode:${videomode} " \ 168 "root=/dev/mtdblock4 rw " \ 169 "rootfstype=jffs2\0" \ 170 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 171 "bootscript=echo Running bootscript from mmc ...; " \ 172 "autoscr ${loadaddr}\0" \ 173 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 174 "mmcboot=echo Booting from mmc ...; " \ 175 "run mmcargs; " \ 176 "bootm ${loadaddr}\0" \ 177 "nandboot=echo Booting from nand ...; " \ 178 "run nandargs; " \ 179 "nand read ${loadaddr} 280000 400000; " \ 180 "bootm ${loadaddr}\0" \ 181 182 #define CONFIG_BOOTCOMMAND \ 183 "if mmcinit; then " \ 184 "if run loadbootscript; then " \ 185 "run bootscript; " \ 186 "else " \ 187 "if run loaduimage; then " \ 188 "run mmcboot; " \ 189 "else run nandboot; " \ 190 "fi; " \ 191 "fi; " \ 192 "else run nandboot; fi" 193 194 #define CONFIG_AUTO_COMPLETE 1 195 /* 196 * Miscellaneous configurable options 197 */ 198 #define V_PROMPT "OMAP3 beagleboard.org # " 199 200 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 201 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 202 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 203 #define CONFIG_SYS_PROMPT V_PROMPT 204 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 205 /* Print Buffer Size */ 206 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 207 sizeof(CONFIG_SYS_PROMPT) + 16) 208 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 209 /* Boot Argument Buffer Size */ 210 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 211 212 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 213 /* works on */ 214 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 215 0x01F00000) /* 31MB */ 216 217 #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ 218 219 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 220 /* load address */ 221 222 /* 223 * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by 224 * 32KHz clk, or from external sig. This rate is divided by a local divisor. 225 */ 226 #define V_PVT 7 227 228 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 229 #define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ 230 #define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) 231 232 /*----------------------------------------------------------------------- 233 * Stack sizes 234 * 235 * The stack sizes are set up in start.S using the settings below 236 */ 237 #define CONFIG_STACKSIZE SZ_128K /* regular stack */ 238 #ifdef CONFIG_USE_IRQ 239 #define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ 240 #define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ 241 #endif 242 243 /*----------------------------------------------------------------------- 244 * Physical Memory Map 245 */ 246 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 247 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 248 #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ 249 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 250 251 /* SDRAM Bank Allocation method */ 252 #define SDRC_R_B_C 1 253 254 /*----------------------------------------------------------------------- 255 * FLASH and environment organization 256 */ 257 258 /* **** PISMO SUPPORT *** */ 259 260 /* Configure the PISMO */ 261 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 262 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 263 264 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ 265 /* one chip */ 266 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 267 #define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ 268 269 #define CONFIG_SYS_FLASH_BASE boot_flash_base 270 271 /* Monitor at start of flash */ 272 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 273 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 274 275 #define CONFIG_ENV_IS_IN_NAND 1 276 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 277 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 278 279 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 280 #define CONFIG_ENV_OFFSET boot_flash_off 281 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 282 283 /*----------------------------------------------------------------------- 284 * CFI FLASH driver setup 285 */ 286 /* timeout values are in ticks */ 287 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 288 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 289 290 /* Flash banks JFFS2 should use */ 291 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 292 CONFIG_SYS_MAX_NAND_DEVICE) 293 #define CONFIG_SYS_JFFS2_MEM_NAND 294 /* use flash_info[2] */ 295 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 296 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 297 298 #ifndef __ASSEMBLY__ 299 extern gpmc_csx_t *nand_cs_base; 300 extern gpmc_t *gpmc_cfg_base; 301 extern unsigned int boot_flash_base; 302 extern volatile unsigned int boot_flash_env_addr; 303 extern unsigned int boot_flash_off; 304 extern unsigned int boot_flash_sec; 305 extern unsigned int boot_flash_type; 306 #endif 307 308 309 #define WRITE_NAND_COMMAND(d, adr)\ 310 writel(d, &nand_cs_base->nand_cmd) 311 #define WRITE_NAND_ADDRESS(d, adr)\ 312 writel(d, &nand_cs_base->nand_adr) 313 #define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) 314 #define READ_NAND(adr) readl(&nand_cs_base->nand_dat) 315 316 /* Other NAND Access APIs */ 317 #define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ 318 while (0) 319 #define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ 320 while (0) 321 #define NAND_DISABLE_CE(nand) 322 #define NAND_ENABLE_CE(nand) 323 #define NAND_WAIT_READY(nand) udelay(10) 324 325 #endif /* __CONFIG_H */ 326