1 /*
2  * (C) Copyright 2006-2008
3  * Texas Instruments.
4  * Richard Woodruff <r-woodruff2@ti.com>
5  * Syed Mohammed Khasim <x0khasim@ti.com>
6  *
7  * Configuration settings for the TI OMAP3530 Beagle board.
8  *
9  * See file CREDITS for list of people who contributed to this
10  * project.
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License as
14  * published by the Free Software Foundation; either version 2 of
15  * the License, or (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25  * MA 02111-1307 USA
26  */
27 
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
30 
31 /*
32  * High Level Configuration Options
33  */
34 #define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
35 #define CONFIG_OMAP		1	/* in a TI OMAP core */
36 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
37 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
38 #define CONFIG_OMAP3_BEAGLE	1	/* working with BEAGLE */
39 
40 #define CONFIG_SDRC	/* The chip has SDRC controller */
41 
42 #include <asm/arch/cpu.h>		/* get chip and board defs */
43 #include <asm/arch/omap3.h>
44 
45 /*
46  * Display CPU and Board information
47  */
48 #define CONFIG_DISPLAY_CPUINFO		1
49 #define CONFIG_DISPLAY_BOARDINFO	1
50 
51 /* Clock Defines */
52 #define V_OSCK			26000000	/* Clock output from T2 */
53 #define V_SCLK			(V_OSCK >> 1)
54 
55 #undef CONFIG_USE_IRQ				/* no support for IRQs */
56 #define CONFIG_MISC_INIT_R
57 
58 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
59 #define CONFIG_SETUP_MEMORY_TAGS	1
60 #define CONFIG_INITRD_TAG		1
61 #define CONFIG_REVISION_TAG		1
62 
63 /*
64  * Size of malloc() pool
65  */
66 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
67 						/* Sector */
68 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
69 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
70 						/* initial data */
71 
72 /*
73  * Hardware drivers
74  */
75 
76 /*
77  * NS16550 Configuration
78  */
79 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
80 
81 #define CONFIG_SYS_NS16550
82 #define CONFIG_SYS_NS16550_SERIAL
83 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
84 #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
85 
86 /*
87  * select serial console configuration
88  */
89 #define CONFIG_CONS_INDEX		3
90 #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
91 #define CONFIG_SERIAL3			3	/* UART3 on Beagle Rev 2 */
92 
93 /* allow to overwrite serial and ethaddr */
94 #define CONFIG_ENV_OVERWRITE
95 #define CONFIG_BAUDRATE			115200
96 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
97 					115200}
98 #define CONFIG_MMC			1
99 #define CONFIG_OMAP3_MMC		1
100 #define CONFIG_DOS_PARTITION		1
101 
102 /* DDR - I use Micron DDR */
103 #define CONFIG_OMAP3_MICRON_DDR		1
104 
105 /* USB */
106 #define CONFIG_MUSB_UDC			1
107 #define CONFIG_USB_OMAP3		1
108 #define CONFIG_TWL4030_USB		1
109 
110 /* USB device configuration */
111 #define CONFIG_USB_DEVICE		1
112 #define CONFIG_USB_TTY			1
113 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
114 /* Change these to suit your needs */
115 #define CONFIG_USBD_VENDORID		0x0451
116 #define CONFIG_USBD_PRODUCTID		0x5678
117 #define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
118 #define CONFIG_USBD_PRODUCT_NAME	"Beagle"
119 
120 /* commands to include */
121 #include <config_cmd_default.h>
122 
123 #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
124 #define CONFIG_CMD_FAT		/* FAT support			*/
125 #define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
126 #define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
127 #define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
128 #define MTDIDS_DEFAULT			"nand0=nand"
129 #define MTDPARTS_DEFAULT		"mtdparts=nand:512k(x-loader),"\
130 					"1920k(u-boot),128k(u-boot-env),"\
131 					"4m(kernel),-(fs)"
132 
133 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
134 #define CONFIG_CMD_MMC		/* MMC support			*/
135 #define CONFIG_CMD_NAND		/* NAND support			*/
136 
137 #undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
138 #undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
139 #undef CONFIG_CMD_IMI		/* iminfo			*/
140 #undef CONFIG_CMD_IMLS		/* List all found images	*/
141 #undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
142 #undef CONFIG_CMD_NFS		/* NFS support			*/
143 
144 #define CONFIG_SYS_NO_FLASH
145 #define CONFIG_HARD_I2C			1
146 #define CONFIG_SYS_I2C_SPEED		100000
147 #define CONFIG_SYS_I2C_SLAVE		1
148 #define CONFIG_SYS_I2C_BUS		0
149 #define CONFIG_SYS_I2C_BUS_SELECT	1
150 #define CONFIG_DRIVER_OMAP34XX_I2C	1
151 
152 /*
153  * TWL4030
154  */
155 #define CONFIG_TWL4030_POWER		1
156 #define CONFIG_TWL4030_LED		1
157 
158 /*
159  * Board NAND Info.
160  */
161 #define CONFIG_NAND_OMAP_GPMC
162 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
163 							/* to access nand */
164 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
165 							/* to access nand at */
166 							/* CS0 */
167 #define GPMC_NAND_ECC_LP_x16_LAYOUT	1
168 
169 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
170 							/* devices */
171 #define CONFIG_JFFS2_NAND
172 /* nand device jffs2 lives on */
173 #define CONFIG_JFFS2_DEV		"nand0"
174 /* start of jffs2 partition */
175 #define CONFIG_JFFS2_PART_OFFSET	0x680000
176 #define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
177 							/* partition */
178 
179 /* Environment information */
180 #define CONFIG_BOOTDELAY		10
181 
182 #define CONFIG_EXTRA_ENV_SETTINGS \
183 	"loadaddr=0x82000000\0" \
184 	"usbtty=cdc_acm\0" \
185 	"console=ttyS2,115200n8\0" \
186 	"vram=12M\0" \
187 	"dvimode=1024x768MR-16@60\0" \
188 	"defaultdisplay=dvi\0" \
189 	"mmcroot=/dev/mmcblk0p2 rw\0" \
190 	"mmcrootfstype=ext3 rootwait\0" \
191 	"nandroot=/dev/mtdblock4 rw\0" \
192 	"nandrootfstype=jffs2\0" \
193 	"mmcargs=setenv bootargs console=${console} " \
194 		"vram=${vram} " \
195 		"omapfb.mode=dvi:${dvimode} " \
196 		"omapfb.debug=y " \
197 		"omapdss.def_disp=${defaultdisplay} " \
198 		"root=${mmcroot} " \
199 		"rootfstype=${mmcrootfstype}\0" \
200 	"nandargs=setenv bootargs console=${console} " \
201 		"vram=${vram} " \
202 		"omapfb.mode=dvi:${dvimode} " \
203 		"omapfb.debug=y " \
204 		"omapdss.def_disp=${defaultdisplay} " \
205 		"root=${nandroot} " \
206 		"rootfstype=${nandrootfstype}\0" \
207 	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
208 	"bootscript=echo Running bootscript from mmc ...; " \
209 		"source ${loadaddr}\0" \
210 	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
211 	"mmcboot=echo Booting from mmc ...; " \
212 		"run mmcargs; " \
213 		"bootm ${loadaddr}\0" \
214 	"nandboot=echo Booting from nand ...; " \
215 		"run nandargs; " \
216 		"nand read ${loadaddr} 280000 400000; " \
217 		"bootm ${loadaddr}\0" \
218 
219 #define CONFIG_BOOTCOMMAND \
220 	"if mmc init; then " \
221 		"if run loadbootscript; then " \
222 			"run bootscript; " \
223 		"else " \
224 			"if run loaduimage; then " \
225 				"run mmcboot; " \
226 			"else run nandboot; " \
227 			"fi; " \
228 		"fi; " \
229 	"else run nandboot; fi"
230 
231 #define CONFIG_AUTO_COMPLETE		1
232 /*
233  * Miscellaneous configurable options
234  */
235 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
236 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
237 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
238 #define CONFIG_SYS_PROMPT		"OMAP3 beagleboard.org # "
239 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
240 /* Print Buffer Size */
241 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
242 					sizeof(CONFIG_SYS_PROMPT) + 16)
243 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
244 /* Boot Argument Buffer Size */
245 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
246 
247 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
248 								/* works on */
249 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
250 					0x01F00000) /* 31MB */
251 
252 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
253 							/* load address */
254 
255 /*
256  * OMAP3 has 12 GP timers, they can be driven by the system clock
257  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
258  * This rate is divided by a local divisor.
259  */
260 #define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
261 #define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
262 #define CONFIG_SYS_HZ			1000
263 
264 /*-----------------------------------------------------------------------
265  * Stack sizes
266  *
267  * The stack sizes are set up in start.S using the settings below
268  */
269 #define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
270 #ifdef CONFIG_USE_IRQ
271 #define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
272 #define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
273 #endif
274 
275 /*-----------------------------------------------------------------------
276  * Physical Memory Map
277  */
278 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
279 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
280 #define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
281 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
282 
283 /* SDRAM Bank Allocation method */
284 #define SDRC_R_B_C		1
285 
286 /*-----------------------------------------------------------------------
287  * FLASH and environment organization
288  */
289 
290 /* **** PISMO SUPPORT *** */
291 
292 /* Configure the PISMO */
293 #define PISMO1_NAND_SIZE		GPMC_SIZE_128M
294 #define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
295 
296 #define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors on */
297 						/* one chip */
298 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
299 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
300 
301 #define CONFIG_SYS_FLASH_BASE		boot_flash_base
302 
303 /* Monitor at start of flash */
304 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
305 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
306 
307 #define CONFIG_ENV_IS_IN_NAND		1
308 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
309 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
310 
311 #define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
312 #define CONFIG_ENV_OFFSET		boot_flash_off
313 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
314 
315 /*-----------------------------------------------------------------------
316  * CFI FLASH driver setup
317  */
318 /* timeout values are in ticks */
319 #define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
320 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
321 
322 /* Flash banks JFFS2 should use */
323 #define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
324 					CONFIG_SYS_MAX_NAND_DEVICE)
325 #define CONFIG_SYS_JFFS2_MEM_NAND
326 /* use flash_info[2] */
327 #define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
328 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
329 
330 #ifndef __ASSEMBLY__
331 extern unsigned int boot_flash_base;
332 extern volatile unsigned int boot_flash_env_addr;
333 extern unsigned int boot_flash_off;
334 extern unsigned int boot_flash_sec;
335 extern unsigned int boot_flash_type;
336 #endif
337 
338 #endif /* __CONFIG_H */
339